dwe_ioctl.c 9.8 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #include "dwe_ioctl.h"
  54. #include "dwe_regs.h"
  55. #ifndef __KERNEL__
  56. #include <stdlib.h>
  57. #include <unistd.h>
  58. #include <string.h>
  59. #ifdef USE_V4L2
  60. #include <linux/videodev2.h>
  61. #endif
  62. #endif
  63. #ifndef __KERNEL__
  64. #ifdef HAL_CMODEL
  65. #define DEWARP_REGISTER_OFFSET 0
  66. #else
  67. #define DEWARP_REGISTER_OFFSET 0x380000
  68. #endif
  69. #define DEWARP_REGISTER_CTL 0x308250
  70. pReadBar g_read_func;
  71. pWriteBar g_write_func;
  72. void dwe_set_func(pReadBar read_func, pWriteBar write_func)
  73. {
  74. g_read_func = read_func;
  75. g_write_func = write_func;
  76. }
  77. void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val)
  78. {
  79. g_write_func(DEWARP_REGISTER_OFFSET + offset, val);
  80. }
  81. u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset)
  82. {
  83. u32 data;
  84. g_read_func(DEWARP_REGISTER_OFFSET + offset, &data);
  85. return data;
  86. }
  87. void dwe_write_extreg(u32 offset, u32 val)
  88. {
  89. g_write_func(DEWARP_REGISTER_CTL + offset, val);
  90. }
  91. u32 dwe_read_extreg(u32 offset)
  92. {
  93. u32 data;
  94. g_read_func(DEWARP_REGISTER_CTL + offset, &data);
  95. return data;
  96. }
  97. long dwe_copy_data(void *dst, void *src, int size)
  98. {
  99. if (dst != src)
  100. memcpy(dst, src, size);
  101. return 0;
  102. }
  103. #else
  104. void dwe_write_reg(struct dwe_ic_dev *dev, u32 offset, u32 val)
  105. {
  106. __raw_writel(val, dev->base + offset);
  107. }
  108. u32 dwe_read_reg(struct dwe_ic_dev *dev, u32 offset)
  109. {
  110. return __raw_readl(dev->base + offset);
  111. }
  112. #endif
  113. int dwe_reset(struct dwe_ic_dev *dev)
  114. {
  115. pr_debug("enter %s\n", __func__);
  116. #ifdef DWE_REG_RESET
  117. __raw_writel(0, dev->reset);
  118. __raw_writel(1, dev->reset);
  119. #endif
  120. dwe_write_reg(dev, DEWARP_CTRL, 0x0c);
  121. return 0;
  122. }
  123. int dwe_s_params(struct dwe_ic_dev *dev, struct dwe_hw_info *info)
  124. {
  125. u32 reg = 0;
  126. u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16);
  127. u32 vUp = (info->split_v1 & ~0x0F) | 0x0C;
  128. u32 vDown = (info->split_v2 & ~0x0F) | 0x0C;
  129. u32 hLine = (info->split_h & ~0x0F) | 0x0C;
  130. pr_debug("enter %s\n", __func__);
  131. dwe_write_reg(dev, MAP_LUT_SIZE,
  132. ((info->map_w & 0x7ff) | ((info->map_h & 0x7ff) << 16)));
  133. dwe_write_reg(dev, SRC_IMG_SIZE,
  134. ((info->src_w & 0x1fff) |
  135. ((info->src_h & 0x1fff) << 16)));
  136. dwe_write_reg(dev, SRC_IMG_STRIDE, info->src_stride);
  137. dwe_write_reg(dev, DST_IMG_SIZE,
  138. ((info->dst_w & 0x1FFF) |
  139. ((info->dst_h & 0x1FFF) << 16)));
  140. dwe_write_reg(dev, DST_IMG_STRIDE, info->dst_stride);
  141. dwe_write_reg(dev, DST_IMG_Y_SIZE1, reg_y_rbuff_size >> 4);
  142. dwe_write_reg(dev, DST_IMG_UV_SIZE1, info->dst_size_uv >> 4);
  143. dwe_write_reg(dev, VERTICAL_SPLIT_LINE,
  144. (vUp & 0x1fff) | ((vDown & 0x1fff) << 16));
  145. dwe_write_reg(dev, HORIZON_SPLIT_LINE, (hLine & 0x1fff));
  146. reg = 0x4C800001;
  147. reg |= ((info->split_line & 0x1) << 11);
  148. reg |= ((info->in_format & 0x3) << 4);
  149. reg |= ((info->out_format & 0x3) << 6);
  150. reg |=
  151. ((info->src_auto_shadow & 0x1) << 8) |
  152. ((info->dst_auto_shadow & 0x1) << 10);
  153. reg |= ((info->hand_shake & 0x1) << 9);
  154. dwe_write_reg(dev, DEWARP_CTRL, reg);
  155. dwe_write_reg(dev, BOUNDRY_PIXEL,
  156. (((info->boundary_y & 0xff) << 16) |
  157. ((info->boundary_u & 0xff)
  158. << 8) | (info->boundary_v & 0xff)));
  159. dwe_write_reg(dev, SCALE_FACTOR, info->scale_factor);
  160. dwe_write_reg(dev, ROI_START,
  161. ((info->roi_x & 0x1fff) |
  162. ((info->roi_y & 0x1fff) << 16)));
  163. return 0;
  164. }
  165. int dwe_enable_bus(struct dwe_ic_dev *dev, bool enable)
  166. {
  167. u32 reg = dwe_read_reg(dev, BUS_CTRL);
  168. /* pr_debug("enter %s\n", __func__); */
  169. if (enable) {
  170. dwe_write_reg(dev, BUS_CTRL, reg | DEWRAP_BUS_CTRL_ENABLE_MASK);
  171. } else {
  172. dwe_write_reg(dev, BUS_CTRL,
  173. reg & ~DEWRAP_BUS_CTRL_ENABLE_MASK);
  174. }
  175. return 0;
  176. }
  177. int dwe_disable_irq(struct dwe_ic_dev *dev)
  178. {
  179. /* pr_debug("enter %s\n", __func__); */
  180. dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK);
  181. return 0;
  182. }
  183. int dwe_clear_irq(struct dwe_ic_dev *dev)
  184. {
  185. u32 reg_dewarp_ctrl;
  186. /* pr_debug("enter %s\n", __func__); */
  187. reg_dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL);
  188. dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl | 2);
  189. dwe_write_reg(dev, DEWARP_CTRL, reg_dewarp_ctrl);
  190. dwe_write_reg(dev, INTERRUPT_STATUS, INT_CLR_MASK | INT_MSK_STATUS_MASK);
  191. return 0;
  192. }
  193. int dwe_read_irq(struct dwe_ic_dev *dev, u32 *ret)
  194. {
  195. u32 irq = 0;
  196. irq = dwe_read_reg(dev, INTERRUPT_STATUS);
  197. *ret = irq;
  198. return 0;
  199. }
  200. int dwe_start(struct dwe_ic_dev *dev)
  201. {
  202. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  203. dev->src = NULL;
  204. dev->dst = NULL;
  205. dev->error = BUF_ERR_UNDERFLOW;
  206. #endif
  207. return 0;
  208. }
  209. int dwe_stop(struct dwe_ic_dev *dev)
  210. {
  211. dwe_enable_bus(dev, 0);
  212. dwe_disable_irq(dev);
  213. return 0;
  214. }
  215. int dwe_start_dma_read(struct dwe_ic_dev *dev,
  216. struct dwe_hw_info *info, u64 addr)
  217. {
  218. #ifdef DWE_REG_RESET
  219. u32 regStart = 1 << 4;
  220. u32 reg;
  221. #endif
  222. u32 reg_dst_y_base = (u32)addr;
  223. u32 reg_y_rbuff_size = ALIGN_UP(info->src_stride * info->src_h, 16);
  224. u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size;
  225. /* pr_debug("enter %s\n", __func__); */
  226. dwe_write_reg(dev, SRC_IMG_Y_BASE, (reg_dst_y_base) >> 4);
  227. dwe_write_reg(dev, SRC_IMG_UV_BASE, (reg_dst_uv_base) >> 4);
  228. #ifdef DWE_REG_RESET
  229. reg = __raw_readl(dev->reset);
  230. __raw_writel(reg | regStart, dev->reset);
  231. __raw_writel(reg & ~regStart, dev->reset);
  232. #endif
  233. return 0;
  234. }
  235. int dwe_set_buffer(struct dwe_ic_dev *dev, struct dwe_hw_info *info, u64 addr)
  236. {
  237. u32 reg_dst_y_base = (u32) addr;
  238. u32 reg_y_rbuff_size = ALIGN_UP(info->dst_stride * info->dst_h, 16);
  239. u32 reg_dst_uv_base = reg_dst_y_base + reg_y_rbuff_size;
  240. /* pr_debug("enter %s\n", __func__); */
  241. dwe_write_reg(dev, DST_IMG_Y_BASE, (reg_dst_y_base) >> 4);
  242. dwe_write_reg(dev, DST_IMG_UV_BASE, (reg_dst_uv_base) >> 4);
  243. return 0;
  244. }
  245. int dwe_set_lut(struct dwe_ic_dev *dev, u64 addr)
  246. {
  247. dwe_write_reg(dev, MAP_LUT_ADDR, ((u32) addr) >> 4);
  248. return 0;
  249. }
  250. int dwe_ioc_qcap(struct dwe_ic_dev *dev, void __user *args)
  251. {
  252. #ifdef __KERNEL__
  253. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  254. strcpy((char *)cap->driver, "viv_dewarp100");
  255. #endif
  256. return 0;
  257. }
  258. long dwe_priv_ioctl(struct dwe_ic_dev *dev, unsigned int cmd, void __user *args)
  259. {
  260. int ret = -1;
  261. switch (cmd) {
  262. case DWEIOC_RESET:
  263. ret = dwe_reset(dev);
  264. break;
  265. case DWEIOC_S_PARAMS:
  266. viv_check_retval(copy_from_user
  267. (&dev->info[0][0], args, sizeof(dev->info[0][0])));
  268. ret = dwe_s_params(dev, &dev->info[0][0]);
  269. break;
  270. #ifndef ENABLE_IRQ
  271. case DWEIOC_ENABLE_BUS:
  272. ret = dwe_enable_bus(dev, 1);
  273. break;
  274. case DWEIOC_DISABLE_BUS:
  275. ret = dwe_enable_bus(dev, 0);
  276. break;
  277. case DWEIOC_DISABLE_IRQ:
  278. ret = dwe_disable_irq(dev);
  279. break;
  280. case DWEIOC_CLEAR_IRQ:
  281. ret = dwe_clear_irq(dev);
  282. break;
  283. #endif
  284. case DWEIOC_READ_IRQ: {
  285. u32 irq = 0;
  286. #ifndef ENABLE_IRQ
  287. ret = dwe_read_irq(dev, &irq);
  288. #endif
  289. viv_check_retval(copy_to_user(args, &irq, sizeof(irq)));
  290. break;
  291. }
  292. case DWEIOC_START:
  293. ret = dwe_start(dev);
  294. break;
  295. case DWEIOC_STOP:
  296. ret = dwe_stop(dev);
  297. break;
  298. case DWEIOC_START_DMA_READ: {
  299. #ifndef ENABLE_IRQ
  300. u64 addr;
  301. viv_check_retval(copy_from_user(&addr, args, sizeof(addr)));
  302. ret = dwe_start_dma_read(dev, &dev->info[0][0], addr);
  303. #endif
  304. break;
  305. }
  306. case DWEIOC_SET_BUFFER: {
  307. #ifndef ENABLE_IRQ
  308. u64 addr;
  309. viv_check_retval(copy_from_user(&addr, args, sizeof(addr)));
  310. ret = dwe_set_buffer(dev, &dev->info[0][0], addr);
  311. #endif
  312. break;
  313. }
  314. case DWEIOC_SET_LUT: {
  315. struct lut_info info;
  316. viv_check_retval(copy_from_user(&info, args, sizeof(info)));
  317. #ifndef ENABLE_IRQ
  318. ret = dwe_set_lut(dev, info.addr);
  319. #endif
  320. break;
  321. }
  322. #ifdef __KERNEL__
  323. case VIDIOC_QUERYCAP:
  324. ret = dwe_ioc_qcap(dev, args);
  325. break;
  326. #endif
  327. default:
  328. pr_err("unsupported dwe command %d", cmd);
  329. break;
  330. }
  331. return ret;
  332. }