vse_regs.h 13 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifndef _VSE_REGS_H_
  54. #define _VSE_REGS_H_
  55. /* product identification */
  56. #define VSE_REG_ID 0x00000000
  57. #define VSE_REG_CTRL 0x00000004
  58. #define VSE_CONTROL_ENABLE_RAM_CLK 17
  59. #define VSE_CONTROL_AUTO_UPDATE_BIT 16
  60. #define VSE_CONTROL_CONFIG_UPDATE_BIT 15
  61. #define VSE_CONTROL_DMA_FRAME_START_BIT 14
  62. #define VSE_CONTROL_INPUT_SELECT_SHIFT 11
  63. #define VSE_CONTROL_INPUT_SELECT (7 << 11)
  64. #define VSE_CONTROL_INPUT_FORMAT_SHIFT 9
  65. #define VSE_CONTROL_INPUT_FORMAT (3 << 9)
  66. #define VSE_CONTROL_SOFT_RESET_BIT 8
  67. #define VSE_CONTROL_PATH2_ENABLE_BIT 2
  68. #define VSE_CONTROL_PATH1_ENABLE_BIT 1
  69. #define VSE_CONTROL_PATH0_ENABLE_BIT 0
  70. /* input size 28:16 height, 12:0 width */
  71. #define VSE_REG_IN_SIZE 0x00000008
  72. #define VSE_REG_CTRL_SHD 0x0000000C
  73. #define VSE_REG_RSZ0_CTL 0x00000400
  74. #define VSE_REG_RSZ1_CTL 0x00000500
  75. #define VSE_REG_RSZ2_CTL 0x00000600
  76. #define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL))
  77. #define VSE_RSZ_SCALE_HY 0x00000004
  78. #define VSE_RSZ_SCALE_HCB 0x00000008
  79. #define VSE_RSZ_SCALE_HCR 0x0000000C
  80. #define VSE_RSZ_SCALE_VY 0x00000010
  81. #define VSE_RSZ_SCALE_VC 0x00000014
  82. #define VSE_RSZ_PHASE_HY 0x00000018
  83. #define VSE_RSZ_PHASE_HC 0x0000001C
  84. #define VSE_RSZ_PHASE_VY 0x00000020
  85. #define VSE_RSZ_PHASE_VC 0x00000024
  86. #define VSE_RSZ_SCALE_LUT_ADDR 0x00000028
  87. #define VSE_RSZ_SCALE_LUT 0x0000002C
  88. #define VSE_RSZ_CTRL_SHD 0x00000030
  89. #define VSE_RSZ_SCALE_HY_SHD 0x00000034
  90. #define VSE_RSZ_SCALE_HCB_SHD 0x00000038
  91. #define VSE_RSZ_SCALE_HCR_SHD 0x0000003C
  92. #define VSE_RSZ_SCALE_VY_SHD 0x00000040
  93. #define VSE_RSZ_SCALE_VC_SHD 0x00000044
  94. #define VSE_RSZ_PHASE_HY_SHD 0x00000048
  95. #define VSE_RSZ_PHASE_HC_SHD 0x0000004C
  96. #define VSE_RSZ_PHASE_VY_SHD 0x00000050
  97. #define VSE_RSZ_PHASE_VC_SHD 0x00000054
  98. #define VSE_RSZ_CROP_XDIR 0x00000058
  99. #define VSE_RSZ_CROP_YDIR 0x0000005C
  100. #define VSE_RSZ_CROP_XDIR_SHD 0x00000060
  101. #define VSE_RSZ_CROP_YDIR_SHD 0x00000064
  102. #define VSE_RSZ_FRAME_RATE 0x00000068
  103. #define VSE_REG_FORMAT_CONV_CTRL 0x0000006C
  104. #define VSE_REG_HBLANK_VALUE 0x000001A0
  105. #define VSE_REG_VBLANK_VALUE 0x000001A4
  106. #define VSE_REG_VSYNC_WIDTH 0x000001A8
  107. #define VSE_REG_HSYNC_PREAMBLE 0x000001AC
  108. #define VSE_REG_MI_CTRL 0x00000800
  109. #define VSE_REG_MI_CTRL_SHD 0x00000804
  110. #define VSE_REG_MI_PATH_0 0x00000810
  111. #define VSE_REG_MI_PATH_1 0x000008b0
  112. #define VSE_REG_MI_PATH_2 0x00000950
  113. #define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2))
  114. #define VSE_REG_MI_FMT 0x00000004
  115. #define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014
  116. #define VSE_REG_MI_Y_SIZE_INIT 0x00000018
  117. #define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C
  118. #define VSE_REG_MI_Y_LENGTH 0x00000020
  119. #define VSE_REG_MI_Y_PIC_WIDTH 0x00000024
  120. #define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028
  121. #define VSE_REG_MI_Y_PIC_SIZE 0x0000002C
  122. #define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030
  123. #define VSE_REG_MI_CB_SIZE_INIT 0x00000034
  124. #define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038
  125. #define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C
  126. #define VSE_REG_MI_CR_SIZE_INIT 0x00000040
  127. #define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044
  128. #define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048
  129. #define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C
  130. #define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050
  131. #define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054
  132. #define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058
  133. #define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C
  134. #define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060
  135. #define VSE_REG_MI_Y_SIZE_SHD 0x00000064
  136. #define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068
  137. #define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C
  138. #define VSE_REG_MI_CB_SIZE_SHD 0x00000070
  139. #define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074
  140. #define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078
  141. #define VSE_REG_MI_CR_SIZE_SHD 0x0000007C
  142. #define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080
  143. #define VSE_REG_MI_STATUS_CLR 0x00000084
  144. #define VSE_REG_MI_CTRL_STATUS 0x00000088
  145. #define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C
  146. #define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090
  147. #define VSE_REG_DMA_CTRL 0x000009E8
  148. #define VSE_REG_DMA_FORMAT 0x000009EC
  149. #define VSE_REG_DMA_Y_PIC_WIDTH 0x000009F0
  150. #define VSE_REG_DMA_Y_PIC_HEIGHT 0x000009F4
  151. #define VSE_REG_DMA_Y_PIC_STRIDE 0x000009F8
  152. #define VSE_REG_Y_PIC_START_ADDR 0x000009FC
  153. #define VSE_REG_CB_PIC_START_ADDR 0x00000A00
  154. #define VSE_REG_CR_PIC_START_ADDR 0x00000A04
  155. #define VSE_REG_Y_START_ADDR_SHD 0x00000A08
  156. #define VSE_REG_CB_START_ADDR_SHD 0x00000A0C
  157. #define VSE_REG_CR_START_ADDR_SHD 0x00000A10
  158. #define VSE_REG_DMA_STATUS 0x00000A14
  159. #define VSE_REG_MI0_BUS_CONFIG 0x00000A20
  160. #define VSE_REG_MI0_BUS_ID 0x00000A24
  161. #define VSE_REG_MI0_BUS_TIME_OUT 0x00000A28
  162. #define VSE_REG_MI0_AXI_STATUS 0x00000A2C
  163. #define VSE_REG_MI1_BUS_CONFIG 0x00000A30
  164. #define VSE_REG_MI1_BUS_ID 0x00000A34
  165. #define VSE_REG_MI1_BUS_TIME_OUT 0x00000A38
  166. #define VSE_REG_MI1_AXI_STATUS 0x00000A3C
  167. #define VSE_REG_MI_IMSC 0x00000A40
  168. #define VSE_REG_MI_IMSC1 0x00000A44
  169. #define VSE_REG_MI_ISR 0x00000A48
  170. #define VSE_REG_MI_ISR1 0x00000A4C
  171. #define VSE_REG_MI_MSI 0x00000A50
  172. #define VSE_REG_MI_MSI1 0x00000A54
  173. #define VSE_REG_MI_ICR 0x00000A58
  174. #define VSE_REG_MI_ICR1 0x00000A5C
  175. #define VSE_REG_MI_RIS 0x00000A60
  176. #define VSE_REG_MI_RIS1 0x00000A64
  177. #define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10
  178. #define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10)
  179. #define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9
  180. #define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9)
  181. #define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8
  182. #define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8)
  183. #define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7
  184. #define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7)
  185. #define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6
  186. #define VSE_FORMAT_CONV_CBCR_FULL (1 << 6)
  187. #define VSE_FORMAT_CONV_Y_FULL_SHIFT 5
  188. #define VSE_FORMAT_CONV_Y_FULL (1 << 5)
  189. #define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2
  190. #define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2)
  191. #define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0
  192. #define VSE_FORMAT_CONV_INPUT_FORMAT (3)
  193. /* slice of VSE_REG_RSZ0_CTL */
  194. #define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10
  195. #define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9
  196. #define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8
  197. #define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7
  198. #define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6
  199. #define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5
  200. #define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4
  201. #define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3
  202. #define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2
  203. #define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1
  204. #define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0
  205. /* slice of VSE_REG_MI_FMT */
  206. #define VSE_RD_IMG_HSIZE_BN_SHIFT 16
  207. #define VSE_RD_IMG_HSIZE_BN (0x3fff<<16)
  208. #define VSE_MI_FORMAT_WA_MSB_EN_SHIFT 10
  209. #define VSE_MI_FORMAT_WA_MSB_EN (1<<10)
  210. #define VSE_MI_FORMAT_WORD_ALIGNED_SHIFT 9
  211. #define VSE_MI_FORMAT_WORD_ALIGNED (1<<9)
  212. #define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7
  213. #define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7)
  214. #define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6
  215. #define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6)
  216. #define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5
  217. #define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5)
  218. #define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3
  219. #define VSE_MI_FORMAT_WR_YUV_STR (3 << 3)
  220. #define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1
  221. #define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1)
  222. #define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0
  223. #define VSE_MI_FORMAT_WR_YUV_10BIT (1)
  224. /* slice of VSE_REG_MI_CTRL */
  225. #define VSE_MI_CONTROL_RDMA_START_BIT 4
  226. #define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3
  227. #define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2
  228. #define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1
  229. #define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0
  230. /* slice of VSE_REG_MI_PATH */
  231. #define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5
  232. #define VSE_MI_PATH_INIT_BASE_EN_BIT 4
  233. #define VSE_MI_PATH_CONFIG_UPDATE_BIT 3
  234. #define VSE_MI_PATH_ENABLE_SKIP_BIT 2
  235. #define VSE_MI_PATH_AUTO_UPDATE_BIT 1
  236. #define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0
  237. #define VSE_MI_ISR_STATUS_VSE_AND_DEWARP_ALL_DONE_BIT 14
  238. #define VSE_MI_ISR_STATUS_FINAL_FRAME_END_BIT 13
  239. #define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12
  240. #define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11
  241. #define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10
  242. #define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9
  243. #define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8
  244. #define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7
  245. #define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6
  246. #define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5
  247. #define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4
  248. #define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3
  249. #define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2
  250. #define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1
  251. #define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0
  252. #define VSE_MI_MIS_VSE_AND_DEWARP_ALL_DONE_BIT 14
  253. #define VSE_MI_MIS_FINAL_FRAME_END_BIT 13
  254. #define VSE_MI_MIS_DMA_YCBCR_READY_BIT 12
  255. #define VSE_MI_MIS_WRAP_MI2_CR_BIT 11
  256. #define VSE_MI_MIS_WRAP_MI2_CB_BIT 10
  257. #define VSE_MI_MIS_WRAP_MI2_Y_BIT 9
  258. #define VSE_MI_MIS_WRAP_MI1_CR_BIT 8
  259. #define VSE_MI_MIS_WRAP_MI1_CB_BIT 7
  260. #define VSE_MI_MIS_WRAP_MI1_Y_BIT 6
  261. #define VSE_MI_MIS_WRAP_MI0_CR_BIT 5
  262. #define VSE_MI_MIS_WRAP_MI0_CB_BIT 4
  263. #define VSE_MI_MIS_WRAP_MI0_Y_BIT 3
  264. #define VSE_MI_MIS_MI2_FRAME_END_BIT 2
  265. #define VSE_MI_MIS_MI1_FRAME_END_BIT 1
  266. #define VSE_MI_MIS_MI0_FRAME_END_BIT 0
  267. #define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5
  268. #define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4
  269. #define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3
  270. #define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2
  271. #define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1
  272. #define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0
  273. #define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16
  274. #define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16)
  275. #define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12
  276. #define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12)
  277. #define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8
  278. #define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8)
  279. #define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6
  280. #define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6)
  281. #define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4
  282. #define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4)
  283. #define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2
  284. #define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2)
  285. #define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0
  286. #define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0)
  287. #ifndef REG_GET_MASK
  288. #define REG_GET_MASK(reg, mask)\
  289. (((reg) & (mask)) >> (mask##_SHIFT))
  290. #define REG_SET_MASK(reg, mask, value)\
  291. {\
  292. ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\
  293. }
  294. #define REG_GET_BIT(reg, shift)\
  295. (((reg) & 1) >> shift)
  296. #define REG_SET_BIT(reg, shift, value)\
  297. {\
  298. ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\
  299. }
  300. #endif
  301. #endif /* _VSE_REGS_H_ */