/*****************************************************************************
 *
 * Copyright 2013, Dream Chip Technologies GmbH. All rights reserved.
 *
 ****************************************************************************
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 *****************************************************************************
 *
 * The GPL License (GPL)
 *
 * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program;
 *
 *****************************************************************************
 *
 * Note: This software is released under dual MIT and GPL licenses. A
 * recipient may use this file under the terms of either the MIT license or
 * GPL License. If you wish to use only one license not the other, you can
 * indicate your decision by deleting one of the above license notices in your
 * version of this file.
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 *****************************************************************************/
/*
* NOTE: This file is automaticaly generated by sig of theflow Rev.: 1.1_dev_koehler.
*       Modifications can be lost.
*
*****************************************************************************/
/**
*-----------------------------------------------------------------------------
* $HeadURL$
* $Author$
* $Rev$
* $Date$
*-----------------------------------------------------------------------------
* @file mrv_all_regs.h
*
* <pre>
*
* Description:
*   This header file exports the module register structure and masks.
*	It should not be included directly by your driver/application, it will be
*   exported by the <TOP>_regs_io.h header file.
*
* </pre>
*/
/*****************************************************************************/

#ifndef _MRV_ALL_REGS_H
#define _MRV_ALL_REGS_H

/* Definitions of block register sizes */
#define DEGAMMA_R_Y_BLOCK_ARR_SIZE 17
#define DEGAMMA_G_Y_BLOCK_ARR_SIZE 17
#define DEGAMMA_B_Y_BLOCK_ARR_SIZE 17
#define CROSS_TALK_COEF_BLOCK_ARR_SIZE 9
#define GAMMA_OUT_Y_BLOCK_ARR_SIZE 17
#define HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 16
#define NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE 17
#define WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE 33
#define WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE 33
#define AWB_MEAS_ACCU_ARR_SIZE 24
#define ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 32
#define ISP_HDREXP_MEASUREMENT_RESULT_ARR_SIZE 25

/*! degamma_r_y_block register layout */
typedef struct {
	uint32_t isp_gamma_r_y;	/*!< De-Gamma Curve definition y red (rw) MRV_ISP_BASE + 0x448 + (n*0x4) (n=0..16) */
} degamma_r_y_block_t;

/*! degamma_g_y_block register layout */
typedef struct {
	uint32_t isp_gamma_g_y;	/*!< De-Gamma Curve definition y green (rw) MRV_ISP_BASE + 0x490 + (n*0x4) (n=0..16) */
} degamma_g_y_block_t;

/*! degamma_b_y_block register layout */
typedef struct {
	uint32_t isp_gamma_b_y;	/*!< De-Gamma Curve definition y blue (rw) MRV_ISP_BASE + 0x4D8 + (n*0x4) (n=0..16) */
} degamma_b_y_block_t;

/*! cross_talk_coef_block register layout */
typedef struct {
	uint32_t isp_ct_coeff;	/*!< cross-talk configuration register (color correction matrix) (rw) MRV_ISP_BASE + 0x7A0 + (n*0x4) (n=0..8) */
} cross_talk_coef_block_t;

/*! gamma_out_y_block register layout */
typedef struct {
	uint32_t isp_gamma_out_y;	/*!< Gamma Out Curve definition y_ (rw) MRV_ISP_BASE + 0x7F0 + (n*0x4) (n=0..16) */
} gamma_out_y_block_t;

/*! histogram_measurement_result register layout */
typedef struct {
	uint32_t isp_hist_bin;	/*!< histogram measurement result bin (r) MRV_HIST_BASE + 0x2428 + (n*0x4) (n=0..15) */
} histogram_measurement_result_t;

/*! nlf_lookup_table_block register layout */
typedef struct {
	uint32_t isp_dpf_nll_coeff;	/*!< Noise Level Lookup Coefficient (rw) MRV_DPF_BASE + 0x2840 + (n*0x4) (n=0..16) */
} nlf_lookup_table_block_t;

/*! wdr_tone_mapping_curve_y_block register layout */
typedef struct {
	uint32_t isp_wdr_tonecurve_ym;	/*!< Tonemapping curve coefficient Ym_ (rw) MRV_WDR_BASE + 0x2A28 + (n*0x4) (n=0..32) */
} wdr_tone_mapping_curve_y_block_t;

/*! wdr_tone_mapping_curve_y_shd_block register layout */
typedef struct {
	uint32_t isp_wdr_tonecurve_ym_shd;	/*!< Tonemapping curve coefficient shadow register (r) MRV_WDR_BASE + 0x2B60 + (n*0x4) (n=0..32) */
} wdr_tone_mapping_curve_y_shd_block_t;

/*! AWB_MEAS_ACCU register layout */
typedef struct {
	uint32_t awb_meas_accu;	/*!< AWB Accu Read (r) ISP_AWB_BASE + 0x2E90 + (n*0x4) (n=0..23) */
} AWB_MEAS_ACCU_t;

/*! isp64_histogram_measurement_result register layout */
typedef struct {
	uint32_t isp64_hist_bin;	/*!< histogram measurement result bin (sh_r) MRV_HIST_BASE + 0x2EA8 + (n*0x4) (n=0..31) */
} isp64_histogram_measurement_result_t;

typedef struct {
	uint32_t x, y;
} elawb_ellipse_pt;

typedef struct {
	uint32_t a1, a2, a3, a4;
} elawb_ellipse_axis;

/*! MrvAll Register layout */
typedef struct {
	uint32_t vi_ccl;	/*!< Clock control register (rw) MRV_BASE + 0x00000000 */
	uint32_t _notused_0[(0x00000008 - 0x00000004) / 4];	/* gap in address space */
	uint32_t vi_id;		/*!< Revision identification register (r) MRV_BASE + 0x00000008 */
	uint32_t _notused_1[(0x00000010 - 0x0000000c) / 4];	/* gap in address space */
	uint32_t vi_iccl;	/*!< Internal clock  control register (rw) MRV_BASE + 0x00000010 */
	uint32_t vi_ircl;	/*!< Internal reset control register (rw) MRV_BASE + 0x00000014 */
	uint32_t vi_dpcl;	/*!< Data path control register (rw) MRV_BASE + 0x00000018 */
	uint32_t _notused_2[(0x00000200 - 0x0000001c) / 4];	/* gap in address space */
	uint32_t img_eff_ctrl;	/*!< Global control register (rw) MRV_IMGEFF_BASE + 0x00000000 */
	uint32_t img_eff_color_sel;	/*!< Color selection register (for color selection effect) (rw) MRV_IMGEFF_BASE + 0x00000004 */
	uint32_t img_eff_mat_1;	/*!< 3x3 matrix coefficients for emboss effect (1) (rw) MRV_IMGEFF_BASE + 0x00000008 */
	uint32_t img_eff_mat_2;	/*!< 3x3 matrix coefficients for emboss effect (2) (rw) MRV_IMGEFF_BASE + 0x0000000c */
	uint32_t img_eff_mat_3;	/*!< 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (rw) MRV_IMGEFF_BASE + 0x00000010 */
	uint32_t img_eff_mat_4;	/*!< 3x3 matrix coefficients for sketch/sharpen effect (2) (rw) MRV_IMGEFF_BASE + 0x00000014 */
	uint32_t img_eff_mat_5;	/*!< 3x3 matrix coefficients for sketch/sharpen effect (3) (rw) MRV_IMGEFF_BASE + 0x00000018 */
	uint32_t img_eff_tint;	/*!< Chrominance increment values of a tint (used for sepia effect) (rw) MRV_IMGEFF_BASE + 0x0000001c */
	uint32_t img_eff_ctrl_shd;	/*!< Shadow register for control register (r) MRV_IMGEFF_BASE + 0x00000020 */
	uint32_t img_eff_sharpen;	/*!< Factor and threshold for sharpen effect (rw) MRV_IMGEFF_BASE + 0x00000024 */
	uint32_t _notused_3[(0x00000300 - 0x00000228) / 4];	/* gap in address space */
	uint32_t super_imp_ctrl;	/*!< Global control register (rw) MRV_SI_BASE + 0x00000000 */
	uint32_t super_imp_offset_x;	/*!< Offset x register (rw) MRV_SI_BASE + 0x00000004 */
	uint32_t super_imp_offset_y;	/*!< Offset y register (rw) MRV_SI_BASE + 0x00000008 */
	uint32_t super_imp_color_y;	/*!< Y component of transparent key color (rw) MRV_SI_BASE + 0x0000000c */
	uint32_t super_imp_color_cb;	/*!< Cb component of transparent key color (rw) MRV_SI_BASE + 0x00000010 */
	uint32_t super_imp_color_cr;	/*!< Cr component of transparent key color (rw) MRV_SI_BASE + 0x00000014 */
	uint32_t _notused_4[(0x00000400 - 0x00000318) / 4];	/* gap in address space */
	uint32_t isp_ctrl;	/*!< global control register (rw) MRV_ISP_BASE + 0x00000000 */
	uint32_t isp_acq_prop;	/*!< ISP acquisition properties (rw) MRV_ISP_BASE + 0x00000004 */
	uint32_t isp_acq_h_offs;	/*!< horizontal input offset (rw) MRV_ISP_BASE + 0x00000008 */
	uint32_t isp_acq_v_offs;	/*!< vertical input offset (rw) MRV_ISP_BASE + 0x0000000c */
	uint32_t isp_acq_h_size;	/*!< horizontal input size (rw) MRV_ISP_BASE + 0x00000010 */
	uint32_t isp_acq_v_size;	/*!< vertical input size (rw) MRV_ISP_BASE + 0x00000014 */
	uint32_t isp_acq_nr_frames;	/*!< Number of frames to be captured (rw) MRV_ISP_BASE + 0x00000018 */
	uint32_t isp_gamma_dx_lo;	/*!< De-Gamma Curve definition lower x increments (sampling points) (rw) MRV_ISP_BASE + 0x0000001c */
	uint32_t isp_gamma_dx_hi;	/*!< De-Gamma Curve definition higher x increments (sampling points) (rw) MRV_ISP_BASE + 0x00000020 */
	degamma_r_y_block_t degamma_r_y_block_arr[DEGAMMA_R_Y_BLOCK_ARR_SIZE];	/*!< degamma_r_y_block MRV_ISP_BASE + 36 + (n*0x4) (n=0..16) */
	degamma_g_y_block_t degamma_g_y_block_arr[DEGAMMA_G_Y_BLOCK_ARR_SIZE];	/*!< degamma_g_y_block MRV_ISP_BASE + 104 + (n*0x4) (n=0..16) */
	degamma_b_y_block_t degamma_b_y_block_arr[DEGAMMA_B_Y_BLOCK_ARR_SIZE];	/*!< degamma_b_y_block MRV_ISP_BASE + 172 + (n*0x4) (n=0..16) */
	uint32_t isp_dgain_rb;	/*!<  (rw) MRV_ISP_BASE + 0x000000f0 */
	uint32_t isp_dgain_g;	/*!< (rw) MRV_ISP_BASE + 0x000000f4 */
	uint32_t _notused_5[(0x00000510 - 0x000004f8) / 4];	/* gap in address space */
	uint32_t isp_awb_prop;	/*!< Auto white balance properties (rw) MRV_ISP_BASE + 0x00000110 */
	uint32_t isp_awb_h_offs;	/*!< Auto white balance horizontal offset of measure window (rw) MRV_ISP_BASE + 0x00000114 */
	uint32_t isp_awb_v_offs;	/*!< Auto white balance vertical offset of measure window (rw) MRV_ISP_BASE + 0x00000118 */
	uint32_t isp_awb_h_size;	/*!< Auto white balance horizontal window size (rw) MRV_ISP_BASE + 0x0000011c */
	uint32_t isp_awb_v_size;	/*!< Auto white balance vertical window size (rw) MRV_ISP_BASE + 0x00000120 */
	uint32_t isp_awb_frames;	/*!< Auto white balance mean value over multiple frames (rw) MRV_ISP_BASE + 0x00000124 */
	uint32_t isp_awb_ref;	/*!< Auto white balance reference Cb/Cr values (rw) MRV_ISP_BASE + 0x00000128 */
	uint32_t isp_awb_thresh;	/*!< Auto white balance threshold values (rw) MRV_ISP_BASE + 0x0000012c */
	uint32_t _notused_6[(0x00000538 - 0x00000530) / 4];	/* gap in address space */
	uint32_t isp_awb_gain_g;	/*!< Auto white balance gain green (rw) MRV_ISP_BASE + 0x00000138 */
	uint32_t isp_awb_gain_rb;	/*!< Auto white balance gain red and blue (rw) MRV_ISP_BASE + 0x0000013c */
	uint32_t isp_awb_white_cnt;	/*!< Auto white balance white pixel count (r) MRV_ISP_BASE + 0x00000140 */
	uint32_t isp_awb_mean;	/*!< Auto white balance measured mean value (r) MRV_ISP_BASE + 0x00000144 */
	uint32_t _notused_7[(0x00000570 - 0x00000548) / 4];	/* gap in address space */
	uint32_t isp_cc_coeff_0;	/*!< Color conversion coefficient 0 (rw) MRV_ISP_BASE + 0x00000170 */
	uint32_t isp_cc_coeff_1;	/*!< Color conversion coefficient 1 (rw) MRV_ISP_BASE + 0x00000174 */
	uint32_t isp_cc_coeff_2;	/*!< Color conversion coefficient 2 (rw) MRV_ISP_BASE + 0x00000178 */
	uint32_t isp_cc_coeff_3;	/*!< Color conversion coefficient 3 (rw) MRV_ISP_BASE + 0x0000017c */
	uint32_t isp_cc_coeff_4;	/*!< Color conversion coefficient 4 (rw) MRV_ISP_BASE + 0x00000180 */
	uint32_t isp_cc_coeff_5;	/*!< Color conversion coefficient 5 (rw) MRV_ISP_BASE + 0x00000184 */
	uint32_t isp_cc_coeff_6;	/*!< Color conversion coefficient 6 (rw) MRV_ISP_BASE + 0x00000188 */
	uint32_t isp_cc_coeff_7;	/*!< Color conversion coefficient 7 (rw) MRV_ISP_BASE + 0x0000018c */
	uint32_t isp_cc_coeff_8;	/*!< Color conversion coefficient 8 (rw) MRV_ISP_BASE + 0x00000190 */
	uint32_t isp_out_h_offs;	/*!< Horizontal offset of output window (rw) MRV_ISP_BASE + 0x00000194 */
	uint32_t isp_out_v_offs;	/*!< Vertical offset of output window (rw) MRV_ISP_BASE + 0x00000198 */
	uint32_t isp_out_h_size;	/*!< Output horizontal picture size (rw) MRV_ISP_BASE + 0x0000019c */
	uint32_t isp_out_v_size;	/*!< Output vertical picture size (rw) MRV_ISP_BASE + 0x000001a0 */
	uint32_t isp_demosaic;	/*!< Demosaic parameters (rw) MRV_ISP_BASE + 0x000001a4 */
	uint32_t isp_flags_shd;	/*!< Flags (current status) of certain signals and Shadow regs for enable signals (r) MRV_ISP_BASE + 0x000001a8 */
	uint32_t isp_out_h_offs_shd;	/*!< current horizontal offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001ac */
	uint32_t isp_out_v_offs_shd;	/*!< current vertical offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001b0 */
	uint32_t isp_out_h_size_shd;	/*!< current output horizontal picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b4 */
	uint32_t isp_out_v_size_shd;	/*!< current output vertical picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b8 */
	uint32_t isp_imsc;	/*!< Interrupt mask (rw) MRV_ISP_BASE + 0x000001bc */
	uint32_t isp_ris;	/*!< Raw interrupt status (r) MRV_ISP_BASE + 0x000001c0 */
	uint32_t isp_mis;	/*!< Masked interrupt status (r) MRV_ISP_BASE + 0x000001c4 */
	uint32_t isp_icr;	/*!< Interrupt clear register (w) MRV_ISP_BASE + 0x000001c8 */
	uint32_t isp_isr;	/*!< Interrupt set register (w) MRV_ISP_BASE + 0x000001cc */
	cross_talk_coef_block_t cross_talk_coef_block_arr[CROSS_TALK_COEF_BLOCK_ARR_SIZE];	/*!< cross_talk_coef_block MRV_ISP_BASE + 464 + (n*0x4) (n=0..8) */
	uint32_t isp_gamma_out_mode;	/*!< gamma segmentation mode register for output gamma (rw) MRV_ISP_BASE + 0x000001f4 */
	gamma_out_y_block_t gamma_out_y_block_arr[GAMMA_OUT_Y_BLOCK_ARR_SIZE];	/*!< gamma_out_y_block MRV_ISP_BASE + 504 + (n*0x4) (n=0..16) */
	uint32_t isp_err;	/*!< ISP error register (r) MRV_ISP_BASE + 0x0000023c */
	uint32_t isp_err_clr;	/*!< ISP error clear register (w) MRV_ISP_BASE + 0x00000240 */
	uint32_t isp_frame_count;	/*!< Frame counter (r) MRV_ISP_BASE + 0x00000244 */
	uint32_t isp_ct_offset_r;	/*!< cross-talk offset red (rw) MRV_ISP_BASE + 0x00000248 */
	uint32_t isp_ct_offset_g;	/*!< cross-talk offset green (rw) MRV_ISP_BASE + 0x0000024c */
	uint32_t isp_ct_offset_b;	/*!< cross-talk offset blue (rw) MRV_ISP_BASE + 0x00000250 */
	uint32_t isp_cnr_linesize;	/*!< chroma noise reduction line size (rw) MRV_ISP_BASE + 0x00000254 */
	uint32_t isp_cnr_threshold_c1;	/*!< chroma noise reduction C1 Threshold (rw) MRV_ISP_BASE + 0x00000258 */
	uint32_t isp_cnr_threshold_c2;	/*!< chroma noise reduction C2 Threshold (rw) MRV_ISP_BASE + 0x0000025c */
	uint32_t isp_flash_cmd;	/*!< Flash command (w) MRV_FLASH_BASE + 0x00000000 */
	uint32_t isp_flash_config;	/*!< Flash config (rw) MRV_FLASH_BASE + 0x00000004 */
	uint32_t isp_flash_prediv;	/*!< Flash Counter Pre-Divider (rw) MRV_FLASH_BASE + 0x00000008 */
	uint32_t isp_flash_delay;	/*!< Flash Delay (rw) MRV_FLASH_BASE + 0x0000000c */
	uint32_t isp_flash_time;	/*!< Flash time (rw) MRV_FLASH_BASE + 0x00000010 */
	uint32_t isp_flash_maxp;	/*!< Maximum value for flash or preflash (rw) MRV_FLASH_BASE + 0x00000014 */
	uint32_t _notused_8[(0x00000680 - 0x00000678) / 4];	/* gap in address space */
	uint32_t isp_sh_ctrl;	/*!< mechanical shutter control (rw) MRV_SHUT_BASE + 0x00000000 */
	uint32_t isp_sh_prediv;	/*!< Mech. Shutter Counter Pre-Divider (rw) MRV_SHUT_BASE + 0x00000004 */
	uint32_t isp_sh_delay;	/*!< Delay register (rw) MRV_SHUT_BASE + 0x00000008 */
	uint32_t isp_sh_time;	/*!< Time register (rw) MRV_SHUT_BASE + 0x0000000c */

	/* TPG */
	uint32_t _notused_pre_tpg[(0x00000700 - 0x00000690) / 4];	/* gap in address space */

	uint32_t isp_tpg_ctrl;	/*!<(rw), 0x00000700 */
	uint32_t isp_tpg_total_in;	/*!<(rw), 0x00000704 */
	uint32_t isp_tpg_act_in;	/*!<(rw), 0x00000708 */
	uint32_t isp_tpg_fp_in;	/*!<(rw), 0x0000070C */
	uint32_t isp_tpg_bp_in;	/*!<(rw), 0x00000710 */
	uint32_t isp_tpg_w_in;	/*!<(rw), 0x00000714 */
	uint32_t isp_tpg_gap_in;	/*!<(rw), 0x00000718 */
	uint32_t isp_tpg_gap_std_in;	/*!<(rw), 0x0000071C */
	uint32_t isp_tpg_random_seed;	/*!<(rw), 0x00000720 */
	uint32_t _notused_mid_tpg1[(0x00000730 - 0x00000724) / 4];	/* gap in address space */
	uint32_t isp_vsync_delay;	/*!<(rw), 0x00000730 */
	uint32_t _notused_mid_tpg2[(0x00000750 - 0x00000734) / 4];	/* gap in address space */
	uint32_t green_equilibrate_ctrl;	/*!<(rw), 0x00000750 */
	uint32_t green_equilibrate_hcnt_dummy;	/*!<(rw), 0x00000754 */
	uint32_t green_equilibrate_ctrl_shd;	/*!<(rw), 0x00000758 */

	uint32_t _notused_after_tpg[(0x00000800 - 0x0000075c) / 4];	/* gap in address space */
	/* uint32_t _notused_9[(0x00000800-0x00000690)/4];  gap in address space */

	uint32_t cproc_ctrl;	/*!< Global control register (rw) MRV_CPROC_BASE + 0x00000000 */
	uint32_t cproc_contrast;	/*!< Color Processing contrast register (rw) MRV_CPROC_BASE + 0x00000004 */
	uint32_t cproc_brightness;	/*!< Color Processing brightness register (rw) MRV_CPROC_BASE + 0x00000008 */
	uint32_t cproc_saturation;	/*!< Color Processing saturation register (rw) MRV_CPROC_BASE + 0x0000000c */
	uint32_t cproc_hue;	/*!< Color Processing hue register (rw) MRV_CPROC_BASE + 0x00000010 */
#ifdef ISP_RGBGC
	uint32_t _notused_10_0[(0x00000900 - 0x00000814) / 4];	/* gap in address space */
	uint32_t isp_gcrgb_r_px_0;	/*!<Gamma Correction for rgb register 0x00000900 */
	uint32_t isp_gcrgb_r_px_1;	/*!<Gamma Correction for rgb register 0x00000904 */
	uint32_t isp_gcrgb_r_px_2;	/*!<Gamma Correction for rgb register 0x00000908 */
	uint32_t isp_gcrgb_r_px_3;	/*!<Gamma Correction for rgb register 0x0000090C */
	uint32_t isp_gcrgb_r_px_4;	/*!<Gamma Correction for rgb register 0x00000910 */
	uint32_t isp_gcrgb_r_px_5;	/*!<Gamma Correction for rgb register 0x00000914 */
	uint32_t isp_gcrgb_r_px_6;	/*!<Gamma Correction for rgb register 0x00000918 */
	uint32_t isp_gcrgb_r_px_7;	/*!<Gamma Correction for rgb register 0x0000091C */
	uint32_t isp_gcrgb_r_px_8;	/*!<Gamma Correction for rgb register 0x00000920 */
	uint32_t isp_gcrgb_r_px_9;	/*!<Gamma Correction for rgb register 0x00000924 */
	uint32_t isp_gcrgb_r_px_10;	/*!<Gamma Correction for rgb register 0x00000928 */
	uint32_t isp_gcrgb_r_y_addr;	/*!<Gamma Correction for rgb register 0x0000092C */
	uint32_t isp_gcrgb_r_y_write_data;	/*!<Gamma Correction for rgb register 0x00000930 */
	uint32_t isp_gcrgb_r_x_addr;	/*!<Gamma Correction for rgb register 0x00000934 */
	uint32_t isp_gcrgb_r_x_write_data;	/*!<Gamma Correction for rgb register 0x00000938 */
	uint32_t _notused_10_1;	/* gap in address space */
	uint32_t isp_gcrgb_g_px_0;	/*!<Gamma Correction for rgb register 0x00000940 */
	uint32_t isp_gcrgb_g_px_1;	/*!<Gamma Correction for rgb register 0x00000944 */
	uint32_t isp_gcrgb_g_px_2;	/*!<Gamma Correction for rgb register 0x00000948 */
	uint32_t isp_gcrgb_g_px_3;	/*!<Gamma Correction for rgb register 0x0000094C */
	uint32_t isp_gcrgb_g_px_4;	/*!<Gamma Correction for rgb register 0x00000950 */
	uint32_t isp_gcrgb_g_px_5;	/*!<Gamma Correction for rgb register 0x00000954 */
	uint32_t isp_gcrgb_g_px_6;	/*!<Gamma Correction for rgb register 0x00000958 */
	uint32_t isp_gcrgb_g_px_7;	/*!<Gamma Correction for rgb register 0x0000095C */
	uint32_t isp_gcrgb_g_px_8;	/*!<Gamma Correction for rgb register 0x00000960 */
	uint32_t isp_gcrgb_g_px_9;	/*!<Gamma Correction for rgb register 0x00000964 */
	uint32_t isp_gcrgb_g_px_10;	/*!<Gamma Correction for rgb register 0x00000968 */
	uint32_t isp_gcrgb_g_y_addr;	/*!<Gamma Correction for rgb register 0x0000096C */
	uint32_t isp_gcrgb_g_y_write_data;	/*!<Gamma Correction for rgb register 0x00000970 */
	uint32_t isp_gcrgb_g_x_addr;	/*!<Gamma Correction for rgb register 0x00000974 */
	uint32_t isp_gcrgb_g_x_write_data;	/*!<Gamma Correction for rgb register 0x00000978 */
	uint32_t _notused_10_2;	/* gap in address space */
	uint32_t isp_gcrgb_b_px_0;	/*!<Gamma Correction for rgb register 0x00000980 */
	uint32_t isp_gcrgb_b_px_1;	/*!<Gamma Correction for rgb register 0x00000984 */
	uint32_t isp_gcrgb_b_px_2;	/*!<Gamma Correction for rgb register 0x00000988 */
	uint32_t isp_gcrgb_b_px_3;	/*!<Gamma Correction for rgb register 0x0000098C */
	uint32_t isp_gcrgb_b_px_4;	/*!<Gamma Correction for rgb register 0x00000990 */
	uint32_t isp_gcrgb_b_px_5;	/*!<Gamma Correction for rgb register 0x00000994 */
	uint32_t isp_gcrgb_b_px_6;	/*!<Gamma Correction for rgb register 0x00000998 */
	uint32_t isp_gcrgb_b_px_7;	/*!<Gamma Correction for rgb register 0x0000099C */
	uint32_t isp_gcrgb_b_px_8;	/*!<Gamma Correction for rgb register 0x000009A0 */
	uint32_t isp_gcrgb_b_px_9;	/*!<Gamma Correction for rgb register 0x000009A4 */
	uint32_t isp_gcrgb_b_px_10;	/*!<Gamma Correction for rgb register 0x000009A8 */
	uint32_t isp_gcrgb_b_y_addr;	/*!<Gamma Correction for rgb register 0x000009AC */
	uint32_t isp_gcrgb_b_y_write_data;	/*!<Gamma Correction for rgb register 0x000009B0 */
	uint32_t isp_gcrgb_b_x_addr;	/*!<Gamma Correction for rgb register 0x000009B4 */
	uint32_t isp_gcrgb_b_x_write_data;	/*!<Gamma Correction for rgb register 0x000009B8 */

	uint32_t _notused_10[(0x00000c00 - 0x000009bc) / 4];	/* gap in address space */

#else
	uint32_t _notused_10[(0x00000c00 - 0x00000814) / 4];	/* gap in address space */
#endif
	uint32_t mrsz_ctrl;	/*!< global control register (rw) MRV_MRSZ_BASE + 0x00000000 */
	uint32_t mrsz_scale_hy;	/*!< horizontal luminance scale factor register (rw) MRV_MRSZ_BASE + 0x00000004 */
	uint32_t mrsz_scale_hcb;	/*!< horizontal Cb scale factor register (rw) MRV_MRSZ_BASE + 0x00000008 */
	uint32_t mrsz_scale_hcr;	/*!< horizontal Cr scale factor register (rw) MRV_MRSZ_BASE + 0x0000000c */
	uint32_t mrsz_scale_vy;	/*!< vertical luminance scale factor register (rw) MRV_MRSZ_BASE + 0x00000010 */
	uint32_t mrsz_scale_vc;	/*!< vertical chrominance scale factor register (rw) MRV_MRSZ_BASE + 0x00000014 */
	uint32_t mrsz_phase_hy;	/*!< horizontal luminance phase register (rw) MRV_MRSZ_BASE + 0x00000018 */
	uint32_t mrsz_phase_hc;	/*!< horizontal chrominance phase register (rw) MRV_MRSZ_BASE + 0x0000001c */
	uint32_t mrsz_phase_vy;	/*!< vertical luminance phase register (rw) MRV_MRSZ_BASE + 0x00000020 */
	uint32_t mrsz_phase_vc;	/*!< vertical chrominance phase register (rw) MRV_MRSZ_BASE + 0x00000024 */
	uint32_t mrsz_scale_lut_addr;	/*!< Address pointer of up-scaling look up table (rw) MRV_MRSZ_BASE + 0x00000028 */
	uint32_t mrsz_scale_lut;	/*!< Entry of up-scaling look up table (rw) MRV_MRSZ_BASE + 0x0000002c */
	uint32_t mrsz_ctrl_shd;	/*!< global control shadow register (r) MRV_MRSZ_BASE + 0x00000030 */
	uint32_t mrsz_scale_hy_shd;	/*!< horizontal luminance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000034 */
	uint32_t mrsz_scale_hcb_shd;	/*!< horizontal Cb scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000038 */
	uint32_t mrsz_scale_hcr_shd;	/*!< horizontal Cr scale factor shadow register (r) MRV_MRSZ_BASE + 0x0000003c */
	uint32_t mrsz_scale_vy_shd;	/*!< vertical luminance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000040 */
	uint32_t mrsz_scale_vc_shd;	/*!< vertical chrominance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000044 */
	uint32_t mrsz_phase_hy_shd;	/*!< horizontal luminance phase shadow register (r) MRV_MRSZ_BASE + 0x00000048 */
	uint32_t mrsz_phase_hc_shd;	/*!< horizontal chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000004c */
	uint32_t mrsz_phase_vy_shd;	/*!< vertical luminance phase shadow register (r) MRV_MRSZ_BASE + 0x00000050 */
	uint32_t mrsz_phase_vc_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000054 */
	uint32_t mrsz_phase_crop_x;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
	uint32_t mrsz_phase_crop_y;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
	uint32_t mrsz_phase_crop_x_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
	uint32_t mrsz_phase_crop_y_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
	uint32_t mrsz_phase_frame_rate;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
	uint32_t mrsz_format_conv_ctrl;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */
	uint32_t _notused_11_0[(0x00001000 - 0x00000c70) / 4];	/* gap in address space */
	uint32_t srsz_ctrl;	/*!< global control register (rw) MRV_SRSZ_BASE + 0x00000000 */
	uint32_t srsz_scale_hy;	/*!< horizontal luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000004 */
	uint32_t srsz_scale_hcb;	/*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000008 */
	uint32_t srsz_scale_hcr;	/*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x0000000c */
	uint32_t srsz_scale_vy;	/*!< vertical luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000010 */
	uint32_t srsz_scale_vc;	/*!< vertical chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000014 */
	uint32_t srsz_phase_hy;	/*!< horizontal luminance phase register (rw) MRV_SRSZ_BASE + 0x00000018 */
	uint32_t srsz_phase_hc;	/*!< horizontal chrominance phase register (rw) MRV_SRSZ_BASE + 0x0000001c */
	uint32_t srsz_phase_vy;	/*!< vertical luminance phase register (rw) MRV_SRSZ_BASE + 0x00000020 */
	uint32_t srsz_phase_vc;	/*!< vertical chrominance phase register (rw) MRV_SRSZ_BASE + 0x00000024 */
	uint32_t srsz_scale_lut_addr;	/*!< Address pointer of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x00000028 */
	uint32_t srsz_scale_lut;	/*!< Entry of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x0000002c */
	uint32_t srsz_ctrl_shd;	/*!< global control shadow register (r) MRV_SRSZ_BASE + 0x00000030 */
	uint32_t srsz_scale_hy_shd;	/*!< horizontal luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000034 */
	uint32_t srsz_scale_hcb_shd;	/*!< horizontal Cb scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000038 */
	uint32_t srsz_scale_hcr_shd;	/*!< horizontal Cr scale factor shadow register (r) MRV_SRSZ_BASE + 0x0000003c */
	uint32_t srsz_scale_vy_shd;	/*!< vertical luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000040 */
	uint32_t srsz_scale_vc_shd;	/*!< vertical chrominance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000044 */
	uint32_t srsz_phase_hy_shd;	/*!< horizontal luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000048 */
	uint32_t srsz_phase_hc_shd;	/*!< horizontal chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x0000004c */
	uint32_t srsz_phase_vy_shd;	/*!< vertical luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000050 */
	uint32_t srsz_phase_vc_shd;	/*!< vertical chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x00000054 */
	uint32_t srsz_phase_crop_x;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
	uint32_t srsz_phase_crop_y;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
	uint32_t srsz_phase_crop_x_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
	uint32_t srsz_phase_crop_y_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
	uint32_t srsz_phase_frame_rate;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
	uint32_t srsz_phase_format_conv_ctr;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */
	uint32_t _notused_11_1[(0x00001100 - 0x00001070) / 4];	/* gap in address space */
	uint32_t srsz2_ctrl;	/*!< global control register (rw) MRV_SRSZ_BASE + 0x00000000 */
	uint32_t srsz2_scale_hy;	/*!< horizontal luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000004 */
	uint32_t srsz2_scale_hcb;	/*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000008 */
	uint32_t srsz2_scale_hcr;	/*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x0000000c */
	uint32_t srsz2_scale_vy;	/*!< vertical luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000010 */
	uint32_t srsz2_scale_vc;	/*!< vertical chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000014 */
	uint32_t srsz2_phase_hy;	/*!< horizontal luminance phase register (rw) MRV_SRSZ_BASE + 0x00000018 */
	uint32_t srsz2_phase_hc;	/*!< horizontal chrominance phase register (rw) MRV_SRSZ_BASE + 0x0000001c */
	uint32_t srsz2_phase_vy;	/*!< vertical luminance phase register (rw) MRV_SRSZ_BASE + 0x00000020 */
	uint32_t srsz2_phase_vc;	/*!< vertical chrominance phase register (rw) MRV_SRSZ_BASE + 0x00000024 */
	uint32_t srsz2_scale_lut_addr;	/*!< Address pointer of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x00000028 */
	uint32_t srsz2_scale_lut;	/*!< Entry of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x0000002c */
	uint32_t srsz2_ctrl_shd;	/*!< global control shadow register (r) MRV_SRSZ_BASE + 0x00000030 */
	uint32_t srsz2_scale_hy_shd;	/*!< horizontal luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000034 */
	uint32_t srsz2_scale_hcb_shd;	/*!< horizontal Cb scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000038 */
	uint32_t srsz2_scale_hcr_shd;	/*!< horizontal Cr scale factor shadow register (r) MRV_SRSZ_BASE + 0x0000003c */
	uint32_t srsz2_scale_vy_shd;	/*!< vertical luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000040 */
	uint32_t srsz2_scale_vc_shd;	/*!< vertical chrominance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000044 */
	uint32_t srsz2_phase_hy_shd;	/*!< horizontal luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000048 */
	uint32_t srsz2_phase_hc_shd;	/*!< horizontal chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x0000004c */
	uint32_t srsz2_phase_vy_shd;	/*!< vertical luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000050 */
	uint32_t srsz2_phase_vc_shd;	/*!< vertical chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x00000054 */
	uint32_t srsz2_phase_crop_x;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
	uint32_t srsz2_phase_crop_y;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
	uint32_t srsz2_phase_crop_x_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
	uint32_t srsz2_phase_crop_y_shd;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
	uint32_t srsz2_phase_frame_rate;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
	uint32_t srsz2_phase_format_conv_ctr;	/*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */

	uint32_t _notused_11_2[(0x00001200 - 0x00001170) / 4];	/* gap in address space */
	uint32_t mcm_ctrl;	/*!<(rw), (0x00001200) */
	uint32_t mcm_size0;	/*!<(rw), (0x00001204) */
	uint32_t mcm_size1;	/*!<(rw), (0x00001208) */
	uint32_t mcm_g2_size0;	/*!<(rw), (0x0000120c) */
	uint32_t mcm_g2_size1;	/*!<(rw), (0x00001210) */
	uint32_t _notused_11_3[(0x00001280 - 0x00001214) / 4];	/* gap in address space */
	uint32_t mcm_rd_cfg;	/*!<(rw), (0x00001280) */
	uint32_t mcm_retiming0;	/*!<(rw), (0x00001284) */
	uint32_t mcm_retiming1;	/*!<(rw), (0x00001288) */
	uint32_t mcm_hsync_preample_ext;	/*!<(rw), (0x0000128c) */
	uint32_t mcm_wr_retiming0;	/*!<(rw), (0x00001290) */
	uint32_t mcm_wr_retiming1;	/*!<(rw), (0x00001294) */

#ifdef ISP_MIV1
	uint32_t _notused_12[(0x00001400 - 0x00001298) / 4];	/* gap in address space */
	uint32_t mi_ctrl;	/*!< Global control register (rw) MRV_MI_BASE + 0x00000000 */
	uint32_t mi_init;	/*!< Control register for address init and skip function (w) MRV_MI_BASE + 0x00000004 */
	uint32_t mi_mp_y_base_ad_init;	/*!< Base address for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x00000008 */
	uint32_t mi_mp_y_size_init;	/*!< Size of main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x0000000c */
	uint32_t mi_mp_y_offs_cnt_init;	/*!< Offset counter init value for main picture Y, JPEG or raw data (rw) MRV_MI_BASE + 0x00000010 */
	uint32_t mi_mp_y_offs_cnt_start;	/*!< Offset counter start value for main picture Y, JPEG or raw data (r) MRV_MI_BASE + 0x00000014 */
	uint32_t mi_mp_y_irq_offs_init;	/*!< Fill level interrupt offset value for main picture Y, JPEG or raw data (rw) MRV_MI_BASE + 0x00000018 */
	uint32_t mi_mp_cb_base_ad_init;	/*!< Base address for main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x0000001c */
	uint32_t mi_mp_cb_size_init;	/*!< Size of main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000020 */
	uint32_t mi_mp_cb_offs_cnt_init;	/*!< Offset counter init value for main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000024 */
	uint32_t mi_mp_cb_offs_cnt_start;	/*!< Offset counter start value for main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000028 */
	uint32_t mi_mp_cr_base_ad_init;	/*!< Base address for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x0000002c */
	uint32_t mi_mp_cr_size_init;	/*!< Size of main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000030 */
	uint32_t mi_mp_cr_offs_cnt_init;	/*!< Offset counter init value for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000034 */
	uint32_t mi_mp_cr_offs_cnt_start;	/*!< Offset counter start value for main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000038 */
	uint32_t mi_sp_y_base_ad_init;	/*!< Base address for self picture Y component ring buffer (rw) MRV_MI_BASE + 0x0000003c */
	uint32_t mi_sp_y_size_init;	/*!< Size of self picture Y component ring buffer (rw) MRV_MI_BASE + 0x00000040 */
	uint32_t mi_sp_y_offs_cnt_init;	/*!< Offset counter init value for self picture Y component ring buffer (rw) MRV_MI_BASE + 0x00000044 */
	uint32_t mi_sp_y_offs_cnt_start;	/*!< Offset counter start value for self picture Y component ring buffer (r) MRV_MI_BASE + 0x00000048 */
	uint32_t mi_sp_y_llength;	/*!< Line length of self picture Y component (rw) MRV_MI_BASE + 0x0000004c */
	uint32_t mi_sp_cb_base_ad_init;	/*!< Base address for self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000050 */
	uint32_t mi_sp_cb_size_init;	/*!< Size of self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000054 */
	uint32_t mi_sp_cb_offs_cnt_init;	/*!< Offset counter init value for self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000058 */
	uint32_t mi_sp_cb_offs_cnt_start;	/*!< Offset counter start value for self picture Cb component ring buffer (r) MRV_MI_BASE + 0x0000005c */
	uint32_t mi_sp_cr_base_ad_init;	/*!< Base address for self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000060 */
	uint32_t mi_sp_cr_size_init;	/*!< Size of self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000064 */
	uint32_t mi_sp_cr_offs_cnt_init;	/*!< Offset counter init value for self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000068 */
	uint32_t mi_sp_cr_offs_cnt_start;	/*!< Offset counter start value for self picture Cr component ring buffer (r) MRV_MI_BASE + 0x0000006c */
	uint32_t mi_byte_cnt;	/*!< Counter value of JPEG or RAW data bytes (r) MRV_MI_BASE + 0x00000070 */
	uint32_t mi_ctrl_shd;	/*!< global control internal shadow register (r) MRV_MI_BASE + 0x00000074 */
	uint32_t mi_mp_y_base_ad_shd;	/*!< Base address shadow register for main picture Y component, JPEG or raw data ring buffer (r) MRV_MI_BASE + 0x00000078 */
	uint32_t mi_mp_y_size_shd;	/*!< Size shadow register of main picture Y component, JPEG or raw data (r) MRV_MI_BASE + 0x0000007c */
	uint32_t mi_mp_y_offs_cnt_shd;	/*!< Current offset counter of main picture Y component, JPEG or raw data ring buffer (r) MRV_MI_BASE + 0x00000080 */
	uint32_t mi_mp_y_irq_offs_shd;	/*!< Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (r) MRV_MI_BASE + 0x00000084 */
	uint32_t mi_mp_cb_base_ad_shd;	/*!< Base address shadow register for main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000088 */
	uint32_t mi_mp_cb_size_shd;	/*!< Size shadow register of main picture Cb component ring buffer (r) MRV_MI_BASE + 0x0000008c */
	uint32_t mi_mp_cb_offs_cnt_shd;	/*!< Current offset counter of main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000090 */
	uint32_t mi_mp_cr_base_ad_shd;	/*!< Base address shadow register for main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000094 */
	uint32_t mi_mp_cr_size_shd;	/*!< Size shadow register of main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000098 */
	uint32_t mi_mp_cr_offs_cnt_shd;	/*!< Current offset counter of main picture Cr component ring buffer (r) MRV_MI_BASE + 0x0000009c */
	uint32_t mi_sp_y_base_ad_shd;	/*!< Base address shadow register for self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a0 */
	uint32_t mi_sp_y_size_shd;	/*!< Size shadow register of self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a4 */
	uint32_t mi_sp_y_offs_cnt_shd;	/*!< Current offset counter of self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a8 */
	uint32_t _notused_13[(0x000014b0 - 0x000014ac) / 4];	/* gap in address space */
	uint32_t mi_sp_cb_base_ad_shd;	/*!< Base address shadow register for self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b0 */
	uint32_t mi_sp_cb_size_shd;	/*!< Size shadow register of self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b4 */
	uint32_t mi_sp_cb_offs_cnt_shd;	/*!< Current offset counter of self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b8 */
	uint32_t mi_sp_cr_base_ad_shd;	/*!< Base address shadow register for self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000bc */
	uint32_t mi_sp_cr_size_shd;	/*!< Size shadow register of self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000c0 */
	uint32_t mi_sp_cr_offs_cnt_shd;	/*!< Current offset counter of self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000c4 */
	uint32_t mi_dma_y_pic_start_ad;	/*!< Y component image start address (rw) MRV_MI_BASE + 0x000000c8 */
	uint32_t mi_dma_y_pic_width;	/*!< Y component image width (rw) MRV_MI_BASE + 0x000000cc */
	uint32_t mi_dma_y_llength;	/*!< Y component original line length (rw) MRV_MI_BASE + 0x000000d0 */
	uint32_t mi_dma_y_pic_size;	/*!< Y component image size (rw) MRV_MI_BASE + 0x000000d4 */
	uint32_t mi_dma_cb_pic_start_ad;	/*!< Cb component image start address (rw) MRV_MI_BASE + 0x000000d8 */
	uint32_t _notused_14[(0x000014e8 - 0x000014dc) / 4];	/* gap in address space */
	uint32_t mi_dma_cr_pic_start_ad;	/*!< Cr component image start address (rw) MRV_MI_BASE + 0x000000e8 */
	uint32_t _notused_15[(0x000014f8 - 0x000014ec) / 4];	/* gap in address space */
	uint32_t mi_imsc;	/*!< Interrupt Mask (1: interrupt active, 0: interrupt masked) (rw) MRV_MI_BASE + 0x000000f8 */
	uint32_t mi_ris;	/*!< Raw Interrupt Status (r) MRV_MI_BASE + 0x000000fc */
	uint32_t mi_mis;	/*!< Masked Interrupt Status (r) MRV_MI_BASE + 0x00000100 */
	uint32_t mi_icr;	/*!< Interrupt Clear Register (w) MRV_MI_BASE + 0x00000104 */
	uint32_t mi_isr;	/*!< Interrupt Set Register (w) MRV_MI_BASE + 0x00000108 */
	uint32_t mi_status;	/*!< MI Status Register (r) MRV_MI_BASE + 0x0000010c */
	uint32_t mi_status_clr;	/*!< MI Status Clear Register (w) MRV_MI_BASE + 0x00000110 */
	uint32_t mi_sp_y_pic_width;	/*!< Y component image width (rw) MRV_MI_BASE + 0x00000114 */
	uint32_t mi_sp_y_pic_height;	/*!< Y component image height (rw) MRV_MI_BASE + 0x00000118 */
	uint32_t mi_sp_y_pic_size;	/*!< Y component image size (rw) MRV_MI_BASE + 0x0000011c */
	uint32_t mi_dma_ctrl;	/*!< DMA control register (rw) MRV_MI_BASE + 0x00000120 */
	uint32_t mi_dma_start;	/*!< DMA start register (w) MRV_MI_BASE + 0x00000124 */
	uint32_t mi_dma_status;	/*!< DMA status register (r) MRV_MI_BASE + 0x00000128 */
	uint32_t mi_pixel_cnt;	/*!< Counter value for defect pixel list (r) MRV_MI_BASE + 0x0000012c */
	uint32_t mi_mp_y_base_ad_init2;	/*!< Base address 2 (ping pong) for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x00000130 */
	uint32_t mi_mp_cb_base_ad_init2;	/*!< Base address 2 (pingpong) for main picture Cb component (rw) MRV_MI_BASE + 0x00000134 */
	uint32_t mi_mp_cr_base_ad_init2;	/*!< Base address 2 (pingpong) for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000138 */
	uint32_t mi_sp_y_base_ad_init2;	/*!< Base address 2 (ping pong) for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x0000013c */
	uint32_t mi_sp_cb_base_ad_init2;	/*!< Base address 2 (pingpong) for main picture Cb component (rw) MRV_MI_BASE + 0x00000140 */
	uint32_t mi_sp_cr_base_ad_init2;	/*!< Base address 2 (pingpong) for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000144 */
	uint32_t mi_reserved_1;	/*!< MI_RESERVED_1 (rw) MRV_MI_BASE + 0x00000148 */
#ifdef ISP_MI_HANDSHAKE_NANO
	uint32_t mi_mp_handshake;	/*!< MI mp handshake control for Nano handshake, (rw) MRV_MI_BASE + 0x0000014C */
#else
	uint32_t mi_reserved_1_1;	/*!< MI_RESERVED_1 (rw) MRV_MI_BASE + 0x0000014c */
#endif
	uint32_t mi_mp_y_llength;	/*!< MI mp y llength for Nano handshake, (rw) MRV_MI_BASE + 0x00000150 */
	uint32_t mi_mp_y_slice_offset;	/*!< MI mp y slice offset for Nano handshake, (rw) MRV_MI_BASE + 0x00000154 */
	uint32_t mi_mp_c_slice_offset;	/*!< MI mp c slice offset for Nano handshare, (rw) MRV_MI_BASE + 0x00000158 */
	uint32_t mi_output_align_format;	/*!< MI output byte swap and LSB alignment control for Nano, (rw) MRV_MI_BASE + 0x0000015C */
	uint32_t mi_mp_output_fifo_size;	/*!< MI mp output fifo control for Nano, (rw) MRV_MI_BASE + 0x00000160 */
	uint32_t mi_mp_y_pic_width;	/*!< MI mp y width pix for Nano handshake, (rw) MRV_MI_BASE + 0x00000164 */
	uint32_t mi_mp_y_pic_height;	/*!< MI mp y height pix for Nano handshake, (rw) MRV_MI_BASE + 0x00000168 */
	uint32_t mi_mp_y_pic_size;	/*!< MI mp y pix size for Nano handshare, (rw) MRV_MI_BASE + 0x0000016C */

#ifdef ISP_MI_BP
	uint32_t _notused_16_0[(0x00001580 - 0x00001570) / 4];
	uint32_t mi_bp_ctrl;	/*!<(rw), (0x00001580) */
	uint32_t mi_bp_r_base_ad_shd;	/*!<(rw), (0x00001584) */
	uint32_t mi_bp_gr_base_ad_shd;	/*!<(rw), (0x00001588) */
	uint32_t mi_bp_gb_base_ad_shd;	/*!<(rw), (0x0000158C) */
	uint32_t mi_bp_b_base_ad_shd;	/*!<(rw), (0x00001590) */
	uint32_t mi_bp_r_offs_cnt_shd;	/*!<(rw), (0x00001594) */
	uint32_t mi_bp_gr_offs_cnt_shd;	/*!<(rw), (0x00001598) */
	uint32_t mi_bp_gb_offs_cnt_shd;	/*!<(rw), (0x0000159C) */
	uint32_t mi_bp_b_offs_cnt_shd;	/*!<(rw), (0x000015A0) */
	uint32_t mi_bp_wr_offs_cnt_init;	/*!<(rw), (0x000015A4) */
	uint32_t mi_bp_wr_irq_offs_shd;	/*!<(rw), (0x000015A8) */
	uint32_t mi_bp_wr_irq_offs_init;	/*!<(rw), (0x000015AC) */
	uint32_t mi_bp_wr_size_shd;	/*!<(rw), (0x000015B0) */
	uint32_t mi_bp_wr_size_init;	/*!<(rw), (0x000015B4) */
	uint32_t mi_bp_wr_llength;	/*!<(rw), (0x000015B8) */
	uint32_t mi_bp_pic_width;	/*!<(rw), (0x000015BC) */
	uint32_t mi_bp_pic_height;	/*!<(rw), (0x000015C0) */
	uint32_t mi_bp_pic_size;	/*!<(rw), (0x000015C4) */
	uint32_t mi_bp_r_offs_cnt_start;	/*!<(rw), (0x000015C8) */
	uint32_t mi_bp_gr_offs_cnt_start;	/*!<(rw), (0x000015CC) */
	uint32_t mi_bp_gb_offs_cnt_start;	/*!<(rw), (0x000015D0) */
	uint32_t mi_bp_b_offs_cnt_start;	/*!<(rw), (0x000015D4) */
	uint32_t mi_bp_r_base_ad_init;	/*!<(rw), (0x000015D8) */
	uint32_t mi_bp_gr_base_ad_init;	/*!<(rw), (0x000015DC) */
	uint32_t mi_bp_gb_base_ad_init;	/*!<(rw), (0x000015E0) */
	uint32_t mi_bp_b_base_ad_init;	/*!<(rw), (0x000015E4) */
#else
	uint32_t _notused_16[(0x000015e8 - 0x00001570) / 4];	/* gap in address space */
#endif
	uint32_t mi_dma_y_raw_fmt;	/*!<(rw), (0x000015E8) */
	uint32_t mi_dma_y_raw_lval;	/*!<(rw), (0x000015EC) */
	uint32_t _notused_16_1[(0x00001800 - 0x000015f0) / 4];	/* gap in address space */

#elif defined (ISP_MIV2)

	uint32_t _notused_12[(0x00001300 - 0x00001298) / 4];	/* gap in address space */
	uint32_t miv2_ctrl;	/*!<(rw), (0x00001300) */
	uint32_t miv2_ctrl_shd;	/*!<(rw), (0x00001304) */
	uint32_t _notused_13[(0x00001310 - 0x00001308) / 4];	/* gap in address space */
	uint32_t miv2_mp_ctrl;	/*!<(rw), (0x00001310) */
	uint32_t miv2_mp_fmt;	/*!<(rw), (0x00001314) */
	uint32_t miv2_mp_bus_cfg;	/*!<(rw), (0x00001318) */
	uint32_t miv2_mp_bus_id;	/*!<(rw), (0x0000131c) */
	uint32_t miv2_mp_bus_timeo;	/*!<(rw), (0x00001320) */
	uint32_t miv2_mp_y_base_ad_init;	/*!<(rw), (0x00001324) */
	uint32_t miv2_mp_y_size_init;	/*!<(rw), (0x00001328) */
	uint32_t miv2_mp_y_offs_cnt_init;	/*!<(rw), (0x0000132c) */
	uint32_t miv2_mp_y_llength;	/*!<(rw), (0x00001330) */
	uint32_t miv2_mp_y_pic_width;	/*!<(rw), (0x00001334) */
	uint32_t miv2_mp_y_pic_height;	/*!<(rw), (0x00001338) */
	uint32_t miv2_mp_y_pic_size;	/*!<(rw), (0x0000133c) */
	uint32_t miv2_mp_cb_base_ad_init;	/*!<(rw), (0x00001340) */
	uint32_t miv2_mp_cb_size_init;	/*!<(rw), (0x00001344) */
	uint32_t miv2_mp_cb_offs_cnt_init;	/*!<(rw), (0x00001348) */
	uint32_t miv2_mp_cr_base_ad_init;	/*!<(rw), (0x0000134c) */
	uint32_t miv2_mp_cr_size_init;	/*!<(rw), (0x00001350) */
	uint32_t miv2_mp_cr_offs_cnt_init;	/*!<(rw), (0x00001354) */
	uint32_t miv2_mp_y_base_ad_init2;	/*!<(rw), (0x00001358) */
	uint32_t miv2_mp_cb_base_ad_init2;	/*!<(rw), (0x0000135c) */
	uint32_t miv2_mp_cr_base_ad_init2;	/*!<(rw), (0x00001360) */
	uint32_t miv2_mp_y_offs_cnt_start;	/*!<(ro), (0x00001364) */
	uint32_t miv2_mp_cb_offs_cnt_start;	/*!<(ro), (0x00001368) */
	uint32_t miv2_mp_cr_offs_cnt_start;	/*!<(ro), (0x0000136c) */
	uint32_t miv2_mp_y_base_ad_shd;	/*!<(ro), (0x00001370) */
	uint32_t miv2_mp_y_size_shd;	/*!<(ro), (0x00001374) */
	uint32_t miv2_mp_y_offs_cnt_shd;	/*!<(ro), (0x00001378) */
	uint32_t miv2_mp_cb_base_ad_shd;	/*!<(ro), (0x0000137c) */
	uint32_t miv2_mp_cb_size_shd;	/*!<(ro), (0x00001380) */
	uint32_t miv2_mp_cb_offs_cnt_shd;	/*!<(ro), (0x00001384) */
	uint32_t miv2_mp_cr_base_ad_shd;	/*!<(ro), (0x00001388) */
	uint32_t miv2_mp_cr_size_shd;	/*!<(ro), (0x0000138c) */
	uint32_t miv2_mp_cr_offs_cnt_shd;	/*!<(ro), (0x00001390) */
	uint32_t miv2_mp_raw_base_ad_init;	/*!<(rw), (0x00001394) */
	uint32_t miv2_mp_raw_size_init;	/*!<(rw), (0x00001398) */
	uint32_t miv2_mp_raw_offs_cnt_init;	/*!<(rw), (0x0000139c) */
	uint32_t miv2_mp_raw_llength;	/*!<(rw), (0x000013a0) */
	uint32_t miv2_mp_raw_pic_width;	/*!<(rw), (0x000013a4) */
	uint32_t miv2_mp_raw_pic_height;	/*!<(rw), (0x000013a8) */
	uint32_t miv2_mp_raw_pic_size;	/*!<(rw), (0x000013ac) */
	uint32_t miv2_mp_raw_offs_cnt_start;	/*!<(ro), (0x000013b0) */
	uint32_t miv2_mp_raw_base_ad_shd;	/*!<(ro), (0x000013b4) */
	uint32_t miv2_mp_raw_size_shd;	/*!<(ro), (0x000013b8) */
	uint32_t miv2_mp_raw_offs_cnt_shd;	/*!<(ro), (0x000013bc) */
	uint32_t miv2_mp_jdp_base_ad_init;	/*!<(rw), (0x000013c0) */
	uint32_t miv2_mp_jdp_size_init;	/*!<(rw), (0x000013c4) */
	uint32_t miv2_mp_jdp_offs_cnt_init;	/*!<(rw), (0x000013c8) */
	uint32_t miv2_mp_jdp_llength;	/*!<(rw), (0x000013cc) */
	uint32_t miv2_mp_jdp_pic_width;	/*!<(rw), (0x000013d0) */
	uint32_t miv2_mp_jdp_pic_height;	/*!<(rw), (0x000013d4) */
	uint32_t miv2_mp_jdp_pic_size;	/*!<(rw), (0x000013d8) */
	uint32_t miv2_mp_jdp_offs_cnt_start;	/*!<(ro), (0x000013dc) */
	uint32_t miv2_mp_jdp_base_ad_shd;	/*!<(ro), (0x000013e0) */
	uint32_t miv2_mp_jdp_size_shd;	/*!<(ro), (0x000013e4) */
	uint32_t miv2_mp_jdp_offs_cnt_shd;	/*!<(ro), (0x000013e8) */
	uint32_t miv2_mp_status_clr;	/*!<(rw), (0x000013ec) */
	uint32_t miv2_mp_ctrl_status;	/*!<(ro), (0x000013f0) */
	uint32_t miv2_mp_axi_status;	/*!<(ro), (0x000013f4) */
	uint32_t miv2_mp_raw_byte_cnt_status;	/*!<(rw), (0x000013f8) */
	uint32_t miv2_mp_jdp_byte_cnt_status;	/*!<(rw), (0x000013fc) */
	uint32_t miv2_mp_dp_byte_cnt_status;	/*!<(rw), (0x00001400) */
	uint32_t _notused_14[(0x0000142c - 0x00001404) / 4];	/* gap in address space */
	uint32_t miv2_sp1_ctrl;	/*!<(rw), (0x0000142c) */
	uint32_t miv2_sp1_fmt;	/*!<(rw), (0x00001430) */
	uint32_t miv2_sp1_bus_cfg;	/*!<(rw), (0x00001434) */
	uint32_t miv2_sp1_bus_id;	/*!<(rw), (0x00001438) */
	uint32_t miv2_sp1_bus_timeo;	/*!<(rw), (0x0000143c) */
	uint32_t miv2_sp1_y_base_ad_init;	/*!<(rw), (0x00001440) */
	uint32_t miv2_sp1_y_size_init;	/*!<(rw), (0x00001444) */
	uint32_t miv2_sp1_y_offs_cnt_init;	/*!<(rw), (0x00001448) */
	uint32_t miv2_sp1_y_llength;	/*!<(rw), (0x0000144c) */
	uint32_t miv2_sp1_y_pic_width;	/*!<(rw), (0x00001450) */
	uint32_t miv2_sp1_y_pic_height;	/*!<(rw), (0x00001454) */
	uint32_t miv2_sp1_y_pic_size;	/*!<(rw), (0x00001458) */
	uint32_t miv2_sp1_cb_base_ad_init;	/*!<(rw), (0x0000145c) */
	uint32_t miv2_sp1_cb_size_init;	/*!<(rw), (0x00001460) */
	uint32_t miv2_sp1_cb_offs_cnt_init;	/*!<(rw), (0x00001464) */
	uint32_t miv2_sp1_cr_base_ad_init;	/*!<(rw), (0x00001468) */
	uint32_t miv2_sp1_cr_size_init;	/*!<(rw), (0x0000146c) */
	uint32_t miv2_sp1_cr_offs_cnt_init;	/*!<(rw), (0x00001470) */
	uint32_t miv2_sp1_y_base_ad_init2;	/*!<(rw), (0x00001474) */
	uint32_t miv2_sp1_cb_base_ad_init2;	/*!<(rw), (0x00001478) */
	uint32_t miv2_sp1_cr_base_ad_init2;	/*!<(rw), (0x0000147c) */
	uint32_t miv2_sp1_y_offs_cnt_start;	/*!<(ro), (0x00001480) */
	uint32_t miv2_sp1_cb_offs_cnt_start;	/*!<(ro), (0x00001484) */
	uint32_t miv2_sp1_cr_offs_cnt_start;	/*!<(ro), (0x00001488) */
	uint32_t miv2_sp1_y_base_ad_shd;	/*!<(ro), (0x0000148c) */
	uint32_t miv2_sp1_y_size_shd;	/*!<(ro), (0x00001490) */
	uint32_t miv2_sp1_y_offs_cnt_shd;	/*!<(ro), (0x00001494) */
	uint32_t miv2_sp1_cb_base_ad_shd;	/*!<(ro), (0x00001498) */
	uint32_t miv2_sp1_cb_size_shd;	/*!<(ro), (0x0000149c) */
	uint32_t miv2_sp1_cb_offs_cnt_shd;	/*!<(ro), (0x000014a0) */
	uint32_t miv2_sp1_cr_base_ad_shd;	/*!<(ro), (0x000014a4) */
	uint32_t miv2_sp1_cr_size_shd;	/*!<(ro), (0x000014a8) */
	uint32_t miv2_sp1_cr_offs_cnt_shd;	/*!<(ro), (0x000014ac) */
	uint32_t miv2_sp1_status_clr;	/*!<(rw), (0x000014b0) */
	uint32_t miv2_sp1_ctrl_status;	/*!<(ro), (0x000014b4) */
	uint32_t miv2_sp1_axi_status;	/*!<(ro), (0x000014b8) */
	uint32_t _notused_15[(0x000014e4 - 0x000014bc) / 4];	/* gap in address space */
	uint32_t miv2_sp2_ctrl;	/*!<(rw), (0x000014e4) */
	uint32_t miv2_sp2_fmt;	/*!<(rw), (0x000014e8) */
	uint32_t miv2_sp2_bus_cfg;	/*!<(rw), (0x000014ec) */
	uint32_t miv2_sp2_bus_id;	/*!<(rw), (0x000014f0) */
	uint32_t miv2_sp2_bus_timeo;	/*!<(rw), (0x000014f4) */
	uint32_t miv2_sp2_y_base_ad_init;	/*!<(rw), (0x000014f8) */
	uint32_t miv2_sp2_y_size_init;	/*!<(rw), (0x000014fc) */
	uint32_t miv2_sp2_y_offs_cnt_init;	/*!<(rw), (0x00001500) */
	uint32_t miv2_sp2_y_llength;	/*!<(rw), (0x00001504) */
	uint32_t miv2_sp2_y_pic_width;	/*!<(rw), (0x00001508) */
	uint32_t miv2_sp2_y_pic_height;	/*!<(rw), (0x0000150c) */
	uint32_t miv2_sp2_y_pic_size;	/*!<(rw), (0x00001510) */
	uint32_t miv2_sp2_cb_base_ad_init;	/*!<(rw), (0x00001514) */
	uint32_t miv2_sp2_cb_size_init;	/*!<(rw), (0x00001518) */
	uint32_t miv2_sp2_cb_offs_cnt_init;	/*!<(rw), (0x0000151c) */
	uint32_t miv2_sp2_cr_base_ad_init;	/*!<(rw), (0x00001520) */
	uint32_t miv2_sp2_cr_size_init;	/*!<(rw), (0x00001524) */
	uint32_t miv2_sp2_cr_offs_cnt_init;	/*!<(rw), (0x00001528) */
	uint32_t miv2_sp2_y_base_ad_init2;	/*!<(rw), (0x0000152c) */
	uint32_t miv2_sp2_cb_base_ad_init2;	/*!<(rw), (0x00001530) */
	uint32_t miv2_sp2_cr_base_ad_init2;	/*!<(rw), (0x00001534) */
	uint32_t miv2_sp2_y_offs_cnt_start;	/*!<(ro), (0x00001538) */
	uint32_t miv2_sp2_cb_offs_cnt_start;	/*!<(ro), (0x0000153c) */
	uint32_t miv2_sp2_cr_offs_cnt_start;	/*!<(ro), (0x00001540) */
	uint32_t miv2_sp2_y_base_ad_shd;	/*!<(ro), (0x00001544) */
	uint32_t miv2_sp2_y_size_shd;	/*!<(ro), (0x00001548) */
	uint32_t miv2_sp2_y_offs_cnt_shd;	/*!<(ro), (0x0000154c) */
	uint32_t miv2_sp2_cb_base_ad_shd;	/*!<(ro), (0x00001550) */
	uint32_t miv2_sp2_cb_size_shd;	/*!<(ro), (0x00001554) */
	uint32_t miv2_sp2_cb_offs_cnt_shd;	/*!<(ro), (0x00001558) */
	uint32_t miv2_sp2_cr_base_ad_shd;	/*!<(ro), (0x0000155c) */
	uint32_t miv2_sp2_cr_size_shd;	/*!<(ro), (0x00001560) */
	uint32_t miv2_sp2_cr_offs_cnt_shd;	/*!<(ro), (0x00001564) */
	uint32_t miv2_sp2_raw_base_ad_init;	/*!<(rw), (0x00001568) */
	uint32_t miv2_sp2_raw_size_init;	/*!<(rw), (0x0000156c) */
	uint32_t miv2_sp2_raw_offs_cnt_init;	/*!<(rw), (0x00001570) */
	uint32_t miv2_sp2_raw_llength;	/*!<(rw), (0x00001574) */
	uint32_t miv2_sp2_raw_pic_width;	/*!<(rw), (0x00001578) */
	uint32_t miv2_sp2_raw_pic_height;	/*!<(rw), (0x0000157c) */
	uint32_t miv2_sp2_raw_pic_size;	/*!<(rw), (0x00001580) */
	uint32_t miv2_sp2_raw_offs_cnt_start;	/*!<(ro), (0x00001584) */
	uint32_t _notused_16_0[(0x0000158c - 0x00001588) / 4];	/* gap in address space */
	uint32_t miv2_sp2_raw_base_ad_shd;	/*!<(ro), (0x0000158c) */
	uint32_t miv2_sp2_raw_size_shd;	/*!<(ro), (0x00001590) */
	uint32_t miv2_sp2_raw_offs_cnt_shd;	/*!<(ro), (0x00001594) */
	uint32_t miv2_sp2_dma_y_pic_start_ad;	/*!<(rw), (0x00001598) */
	uint32_t miv2_sp2_dma_y_pic_width;	/*!<(rw), (0x0000159c) */
	uint32_t miv2_sp2_dma_y_pic_llength;	/*!<(rw), (0x000015a0) */
	uint32_t miv2_sp2_dma_y_pic_size;	/*!<(rw), (0x000015a4) */
	uint32_t miv2_sp2_dma_cb_pic_start_ad;	/*!<(rw), (0x000015a8) */
	uint32_t miv2_sp2_dma_cr_pic_start_ad;	/*!<(rw), (0x000015ac) */
	uint32_t miv2_sp2_dma_y_pic_start_ad_shd;	/*!<(ro), (0x000015b0) */
	uint32_t miv2_sp2_dma_cb_pic_start_ad_shd;	/*!<(ro), (0x000015b4) */
	uint32_t miv2_sp2_dma_cr_pic_start_ad_shd;	/*!<(ro), (0x000015b8) */
	uint32_t miv2_sp2_dma_raw_pic_start_ad;	/*!<(rw), (0x000015bc) */
	uint32_t miv2_sp2_dma_raw_pic_width;	/*!<(rw), (0x000015c0) */
	uint32_t miv2_sp2_dma_raw_pic_llength;	/*!<(rw), (0x000015c4) */
	uint32_t miv2_sp2_dma_raw_pic_size;	/*!<(rw), (0x000015c8) */
	uint32_t miv2_sp2_dma_raw_pic_start_ad_shd;	/*!<(ro), (0x000015cc) */
	uint32_t miv2_sp2_status_clr;	/*!<(rw), (0x000015d0) */
	uint32_t miv2_sp2_ctrl_status;	/*!<(ro), (0x000015d4) */
	uint32_t miv2_sp2_axi_status;	/*!<(ro), (0x000015d8) */
	uint32_t miv2_sp2_dma_yuv_status;	/*!<(ro), (0x000015dc) */
	uint32_t miv2_sp2_dma_raw_status;	/*!<(ro), (0x000015e0) */
	uint32_t miv2_sp2_dma_y_pic_lval;	/*!<(rw), (0x000015e4) */
	uint32_t _notused_16_1[(0x000015ec - 0x000015e8) / 4];	/* gap in address space */
	uint32_t miv2_sp2_dma_raw_pic_lval;	/*!<(rw), (0x000015ec) */
	uint32_t _notused_16_2[(0x00001600 - 0x000015f0) / 4];	/* gap in address space */
	uint32_t miv2_mcm_ctrl;	/*!<(rw), (0x00001600) */
	uint32_t miv2_mcm_fmt;	/*!<(rw), (0x00001604) */
	uint32_t miv2_mcm_bus_cfg;	/*!<(rw), (0x00001608) */
	uint32_t miv2_mcm_bus_id;	/*!<(rw), (0x0000160c) */
	uint32_t miv2_mcm_bus_timeo;	/*!<(rw), (0x00001610) */
	uint32_t miv2_mcm_raw0_base_ad_init;	/*!<(rw), (0x00001614) */
	uint32_t miv2_mcm_raw0_size_init;	/*!<(rw), (0x00001618) */
	uint32_t miv2_mcm_raw0_offs_cnt_init;	/*!<(rw), (0x0000161c) */
	uint32_t miv2_mcm_raw0_llength;	/*!<(rw), (0x00001620) */
	uint32_t miv2_mcm_raw0_pic_width;	/*!<(rw), (0x00001624) */
	uint32_t miv2_mcm_raw0_pic_height;	/*!<(rw), (0x00001628) */
	uint32_t miv2_mcm_raw0_pic_size;	/*!<(rw), (0x0000162c) */
	uint32_t miv2_mcm_raw0_offs_cnt_start;	/*!<(ro), (0x00001630) */
	uint32_t miv2_mcm_raw0_base_ad_shd;	/*!<(ro), (0x00001634) */
	uint32_t miv2_mcm_raw0_size_shd;	/*!<(ro), (0x00001638) */
	uint32_t miv2_mcm_raw0_offs_cnt_shd;	/*!<(ro), (0x0000163c) */
	uint32_t miv2_mcm_raw1_base_ad_init;	/*!<(rw), (0x00001640) */
	uint32_t miv2_mcm_raw1_size_init;	/*!<(rw), (0x00001644) */
	uint32_t miv2_mcm_raw1_offs_cnt_init;	/*!<(rw), (0x00001648) */
	uint32_t miv2_mcm_raw1_llength;	/*!<(rw), (0x0000164c) */
	uint32_t miv2_mcm_raw1_pic_width;	/*!<(rw), (0x00001650) */
	uint32_t miv2_mcm_raw1_pic_height;	/*!<(rw), (0x00001654) */
	uint32_t miv2_mcm_raw1_pic_size;	/*!<(rw), (0x00001658) */
	uint32_t miv2_mcm_raw1_offs_cnt_start;	/*!<(ro), (0x0000165c) */
	uint32_t miv2_mcm_raw1_base_ad_shd;	/*!<(ro), (0x00001660) */
	uint32_t miv2_mcm_raw1_size_shd;	/*!<(ro), (0x00001664) */
	uint32_t miv2_mcm_raw1_offs_cnt_shd;	/*!<(ro), (0x00001668) */
	uint32_t miv2_mcm_dma_raw_pic_start_ad;	/*!<(rw), (0x0000166c) */
	uint32_t miv2_mcm_dma_raw_pic_width;	/*!<(rw), (0x00001670) */
	uint32_t miv2_mcm_dma_raw_pic_llength;	/*!<(rw), (0x00001674) */
	uint32_t miv2_mcm_dma_raw_pic_size;	/*!<(rw), (0x00001678) */
	uint32_t miv2_mcm_dma_raw_pic_start_ad_shd;	/*!<(ro), (0x0000167c) */
	uint32_t miv2_mcm_status_clr;	/*!<(rw), (0x00001680) */
	uint32_t miv2_mcm_ctrl_status;	/*!<(ro), (0x00001684) */
	uint32_t miv2_mcm_axi_status;	/*!<(ro), (0x00001688) */
	uint32_t miv2_mcm_dma_status;	/*!<(ro), (0x0000168c) */
	uint32_t miv2_mcm_dma_raw_pic_lval;	/*!<(ro), (0x00001690) */
	uint32_t miv2_mcm_raw0_lval_bytes;	/*!<(ro), (0x00001694) */
	uint32_t _notused_16_3[(0x000016c0 - 0x00001698) / 4];	/* gap in address space */
	uint32_t miv2_imsc;	/*!<(rw), (0x000016c0) */
	uint32_t miv2_imsc1;	/*!<(rw), (0x000016c4) */
	uint32_t miv2_isr;	/*!<(rw), (0x000016c8) */
	uint32_t miv2_isr1;	/*!<(rw), (0x000016cc) */
	uint32_t miv2_mis;	/*!<(rw), (0x000016d0) */
	uint32_t miv2_mis1;	/*!<(rw), (0x000016d4) */
	uint32_t miv2_icr;	/*!<(rw), (0x000016d8) */
	uint32_t miv2_icr1;	/*!<(rw), (0x000016dc) */
	uint32_t miv2_ris;	/*!<(rw), (0x000016e0) */
	uint32_t miv2_ris1;	/*!<(rw), (0x000016e4) */
	uint32_t miv2_imsc2; /*!<(rw), (0x000016e8) */
	uint32_t miv2_isr2; /*!<(rw), (0x000016ec) */
	uint32_t miv2_mis2; /*!<(rw), (0x000016f0) */
	uint32_t miv2_icr2; /*!<(rw), (0x000016f4) */
	uint32_t miv2_ris2; /*!<(rw), (0x000016f8) */
	 uint32_t _notused_16_4;
	uint32_t miv2_mp_y_irq_offs_init;	/*!<(rw), (0x00001700) */
	uint32_t miv2_mp_jdp_irq_offs_init;	/*!<(rw), (0x00001704) */
	uint32_t miv2_mp_raw_irq_offs_init;	/*!<(rw), (0x00001708) */
	uint32_t miv2_sp1_y_irq_offs_init;	/*!<(rw), (0x0000170c) */
	uint32_t miv2_sp2_y_irq_offs_init;	/*!<(rw), (0x00001710) */
	uint32_t miv2_sp2_raw_irq_offs_init;	/*!<(rw), (0x00001714) */
	uint32_t miv2_mcm_raw0_irq_offs_init;	/*!<(rw), (0x00001718) */
	uint32_t miv2_mcm_raw1_irq_offs_init;	/*!<(rw), (0x0000171c) */
	uint32_t miv2_mp_y_irq_offs_shd;	/*!<(ro), (0x00001720) */
	uint32_t miv2_mp_jdp_irq_offs_shd;	/*!<(ro), (0x00001724) */
	uint32_t miv2_mp_raw_irq_offs_shd;	/*!<(ro), (0x00001728) */
	uint32_t miv2_sp1_y_irq_offs_shd;	/*!<(ro), (0x0000172c) */
	uint32_t miv2_sp2_y_irq_offs_shd;	/*!<(ro), (0x00001730) */
	uint32_t miv2_sp2_raw_irq_offs_shd;	/*!<(ro), (0x00001734) */
	uint32_t miv2_mcm_raw0_irq_offs_shd;	/*!<(ro), (0x00001738) */
	uint32_t miv2_mcm_raw1_irq_offs_shd;	/*!<(ro), (0x0000173c) */

	uint32_t _notused_16[(0x00001800 - 0x00001740) / 4];	/* gap in address space */
#endif
	uint32_t jpe_gen_header;	/*!< command to start stream header generation (w) MRV_JPE_BASE + 0x00000000 */
	uint32_t jpe_encode;	/*!< Start command to start JFIF stream encoding (w) MRV_JPE_BASE + 0x00000004 */
	uint32_t jpe_init;	/*!< Automatic configuration update (INIT) (w) MRV_JPE_BASE + 0x00000008 */
	uint32_t jpe_y_scale_en;	/*!< Y value scaling control register (rw) MRV_JPE_BASE + 0x0000000c */
	uint32_t jpe_cbcr_scale_en;	/*!< Cb/Cr value scaling control register (rw) MRV_JPE_BASE + 0x00000010 */
	uint32_t jpe_table_flush;	/*!< header generation debug register (rw) MRV_JPE_BASE + 0x00000014 */
	uint32_t jpe_enc_hsize;	/*!< JPEG codec horizontal image size for encoding (rw) MRV_JPE_BASE + 0x00000018 */
	uint32_t jpe_enc_vsize;	/*!< JPEG codec vertical image size for encoding (rw) MRV_JPE_BASE + 0x0000001c */
	uint32_t jpe_pic_format;	/*!< JPEG picture encoding format (rw) MRV_JPE_BASE + 0x00000020 */
	uint32_t jpe_restart_interval;	/*!< restart marker insertion register (rw) MRV_JPE_BASE + 0x00000024 */
	uint32_t jpe_tq_y_select;	/*!< Q- table selector 0, quant. table for Y component (rw) MRV_JPE_BASE + 0x00000028 */
	uint32_t jpe_tq_u_select;	/*!< Q- table selector 1, quant. table for U component (rw) MRV_JPE_BASE + 0x0000002c */
	uint32_t jpe_tq_v_select;	/*!< Q- table selector 2, quant. table for V component (rw) MRV_JPE_BASE + 0x00000030 */
	uint32_t jpe_dc_table_select;	/*!< Huffman table selector for DC values (r) MRV_JPE_BASE + 0x00000034 */
	uint32_t jpe_ac_table_select;	/*!< Huffman table selector for AC values (r) MRV_JPE_BASE + 0x00000038 */
	uint32_t jpe_table_data;	/*!< table programming register (w) MRV_JPE_BASE + 0x0000003c */
	uint32_t jpe_table_id;	/*!< table programming select register (rw) MRV_JPE_BASE + 0x00000040 */
	uint32_t jpe_tac0_len;	/*!< Huffman AC table 0 length (rw) MRV_JPE_BASE + 0x00000044 */
	uint32_t jpe_tdc0_len;	/*!< Huffman DC table 0 length (rw) MRV_JPE_BASE + 0x00000048 */
	uint32_t jpe_tac1_len;	/*!< Huffman AC table 1 length (rw) MRV_JPE_BASE + 0x0000004c */
	uint32_t jpe_tdc1_len;	/*!< Huffman DC table 1 length (rw) MRV_JPE_BASE + 0x00000050 */
	uint32_t _notused_17[(0x00001858 - 0x00001854) / 4];	/* gap in address space */
	uint32_t jpe_encoder_busy;	/*!< encoder status flag (r) MRV_JPE_BASE + 0x00000058 */
	uint32_t jpe_header_mode;	/*!< header mode definition (rw) MRV_JPE_BASE + 0x0000005c */
	uint32_t jpe_encode_mode;	/*!< encode mode (r) MRV_JPE_BASE + 0x00000060 */
	uint32_t jpe_debug;	/*!< debug information register (r) MRV_JPE_BASE + 0x00000064 */
	uint32_t jpe_error_imr;	/*!< JPEG error interrupt mask register (rw) MRV_JPE_BASE + 0x00000068 */
	uint32_t jpe_error_ris;	/*!< JPEG error raw  interrupt status register (r) MRV_JPE_BASE + 0x0000006c */
	uint32_t jpe_error_mis;	/*!< JPEG error masked interrupt status register (r) MRV_JPE_BASE + 0x00000070 */
	uint32_t jpe_error_icr;	/*!< JPEG error interrupt set register (w) MRV_JPE_BASE + 0x00000074 */
	uint32_t jpe_error_isr;	/*!< JPEG error interrupt clear register (w) MRV_JPE_BASE + 0x00000078 */
	uint32_t jpe_status_imr;	/*!< JPEG status interrupt mask register (rw) MRV_JPE_BASE + 0x0000007c */
	uint32_t jpe_status_ris;	/*!< JPEG status raw interrupt status register (r) MRV_JPE_BASE + 0x00000080 */
	uint32_t jpe_status_mis;	/*!< JPEG status masked interrupt status register (r) MRV_JPE_BASE + 0x00000084 */
	uint32_t jpe_status_icr;	/*!< JPEG status interrupt clear register (w) MRV_JPE_BASE + 0x00000088 */
	uint32_t jpe_status_isr;	/*!< JPEG status interrupt set register (w) MRV_JPE_BASE + 0x0000008c */
	uint32_t jpe_config;	/*!< JPEG configuration register (rw) MRV_JPE_BASE + 0x00000090 */
	uint32_t _notused_18[(0x00001a00 - 0x00001894) / 4];	/* gap in address space */
	uint32_t smia_ctrl;	/*!< global control register (rw) MRV_SMIA_BASE + 0x00000000 */
	uint32_t smia_status;	/*!< global status register (r) MRV_SMIA_BASE + 0x00000004 */
	uint32_t smia_imsc;	/*!< Interrupt mask (rw) MRV_SMIA_BASE + 0x00000008 */
	uint32_t smia_ris;	/*!< Raw interrupt status (r) MRV_SMIA_BASE + 0x0000000c */
	uint32_t smia_mis;	/*!< Masked interrupt status (r) MRV_SMIA_BASE + 0x00000010 */
	uint32_t smia_icr;	/*!< Interrupt clear register (w) MRV_SMIA_BASE + 0x00000014 */
	uint32_t smia_isr;	/*!< Interrupt set register (w) MRV_SMIA_BASE + 0x00000018 */
	uint32_t smia_data_format_sel;	/*!< data format selector register (rw) MRV_SMIA_BASE + 0x0000001c */
	uint32_t smia_sof_emb_data_lines;	/*!< start of frame embedded data lines register (rw) MRV_SMIA_BASE + 0x00000020 */
	uint32_t smia_emb_hstart;	/*!< embedded data hstart register (rw) MRV_SMIA_BASE + 0x00000024 */
	uint32_t smia_emb_hsize;	/*!< embedded data hsize register (rw) MRV_SMIA_BASE + 0x00000028 */
	uint32_t smia_emb_vstart;	/*!< embedded data vstart register (rw) MRV_SMIA_BASE + 0x0000002c */
	uint32_t smia_num_lines;	/*!< image data lines register (rw) MRV_SMIA_BASE + 0x00000030 */
	uint32_t smia_emb_data_fifo;	/*!< Embedded Data Fifo (r) MRV_SMIA_BASE + 0x00000034 */
	uint32_t smia_fifo_fill_level;	/*!< Embedded Data FIFO Fill Level (rw) MRV_SMIA_BASE + 0x00000038 */
	uint32_t _notused_19[(0x00001c00 - 0x00001a3c) / 4];	/* gap in address space */
	uint32_t mipi_ctrl;	/*!< global control register (rw) MRV_MIPI_BASE + 0x00000000 */
	uint32_t mipi_status;	/*!< global status register (r) MRV_MIPI_BASE + 0x00000004 */
	uint32_t mipi_imsc;	/*!< Interrupt mask (rw) MRV_MIPI_BASE + 0x00000008 */
	uint32_t mipi_ris;	/*!< Raw interrupt status (r) MRV_MIPI_BASE + 0x0000000c */
	uint32_t mipi_mis;	/*!< Masked interrupt status (r) MRV_MIPI_BASE + 0x00000010 */
	uint32_t mipi_icr;	/*!< Interrupt clear register (w) MRV_MIPI_BASE + 0x00000014 */
	uint32_t mipi_isr;	/*!< Interrupt set register (w) MRV_MIPI_BASE + 0x00000018 */
	uint32_t mipi_cur_data_id;	/*!< Current Data Identifier (r) MRV_MIPI_BASE + 0x0000001c */
	uint32_t mipi_img_data_sel;	/*!< Image Data Selector (rw) MRV_MIPI_BASE + 0x00000020 */
	uint32_t mipi_add_data_sel_1;	/*!< Additional Data Selector 1 (rw) MRV_MIPI_BASE + 0x00000024 */
	uint32_t mipi_add_data_sel_2;	/*!< Additional Data Selector 2 (rw) MRV_MIPI_BASE + 0x00000028 */
	uint32_t mipi_add_data_sel_3;	/*!< Additional Data Selector 3 (rw) MRV_MIPI_BASE + 0x0000002c */
	uint32_t mipi_add_data_sel_4;	/*!< Additional Data Selector 4 (rw) MRV_MIPI_BASE + 0x00000030 */
	uint32_t mipi_add_data_fifo;	/*!< Additional Data Fifo (r) MRV_MIPI_BASE + 0x00000034 */
	uint32_t mipi_add_data_fill_level;	/*!< Additional Data FIFO Fill Level (rw) MRV_MIPI_BASE + 0x00000038 */
	uint32_t mipi_compressed_mode;	/*!< controls processing of compressed raw data types (rw) MRV_MIPI_BASE + 0x0000003c */
	uint32_t mipi_frame;	/*!< frame number from frame start and frame end short packets (r) MRV_MIPI_BASE + 0x00000040 */
	uint32_t mipi_gen_short_dt;	/*!< data type flags for received generic short packets (r) MRV_MIPI_BASE + 0x00000044 */
	uint32_t mipi_gen_short_8_9;	/*!< data field for generic short packets of data type 0x8 and 0x9 (r) MRV_MIPI_BASE + 0x00000048 */
	uint32_t mipi_gen_short_a_b;	/*!< data field for generic short packets of data type 0xA and 0xB (r) MRV_MIPI_BASE + 0x0000004c */
	uint32_t mipi_gen_short_c_d;	/*!< data field for generic short packets of data type 0xC and 0xD (r) MRV_MIPI_BASE + 0x00000050 */
	uint32_t mipi_gen_short_e_f;	/*!< data field for generic short packets of data type 0xE and 0xF (r) MRV_MIPI_BASE + 0x00000054 */
	uint32_t _notused_21[(0x00002000 - 0x00001c58) / 4];	/* gap in address space */
	uint32_t isp_afm_ctrl;	/*!< This is the control register for AF measurement unit (rw) MRV_AFM_BASE + 0x00000000 */
	uint32_t isp_afm_lt_a;	/*!< Top Left corner of measure window A (rw) MRV_AFM_BASE + 0x00000004 */
	uint32_t isp_afm_rb_a;	/*!< Bottom right corner of measure window A (rw) MRV_AFM_BASE + 0x00000008 */
	uint32_t isp_afm_lt_b;	/*!< Top left corner of measure window B (rw) MRV_AFM_BASE + 0x0000000c */
	uint32_t isp_afm_rb_b;	/*!< Bottom right corner of measure window B (rw) MRV_AFM_BASE + 0x00000010 */
	uint32_t isp_afm_lt_c;	/*!< Top left corner of measure window C (rw) MRV_AFM_BASE + 0x00000014 */
	uint32_t isp_afm_rb_c;	/*!< Bottom right corner of measure window C (rw) MRV_AFM_BASE + 0x00000018 */
	uint32_t isp_afm_thres;	/*!< Threshold register (rw) MRV_AFM_BASE + 0x0000001c */
	uint32_t isp_afm_var_shift;	/*!< Variable shift register (rw) MRV_AFM_BASE + 0x00000020 */
	uint32_t isp_afm_sum_a;	/*!< Sharpness Value Status Register of Window A (r) MRV_AFM_BASE + 0x00000024 */
	uint32_t isp_afm_sum_b;	/*!< Sharpness Value Status Register of Window B (r) MRV_AFM_BASE + 0x00000028 */
	uint32_t isp_afm_sum_c;	/*!< Sharpness Value Status Register of Window C (r) MRV_AFM_BASE + 0x0000002c */
	uint32_t isp_afm_lum_a;	/*!< Luminance Value Status Register of Window A (r) MRV_AFM_BASE + 0x00000030 */
	uint32_t isp_afm_lum_b;	/*!< Luminance Value Status Register of Window B (r) MRV_AFM_BASE + 0x00000034 */
	uint32_t isp_afm_lum_c;	/*!< Luminance Value Status Register of Window C (r) MRV_AFM_BASE + 0x00000038 */
#ifdef ISP_HIST256
	uint32_t _notused_22_0[(0x00002100 - 0x0000203c) / 4];	/* gap in address space */
	uint32_t isp_hist256_prop;	/*!< Register of  hist 256, address 0x00002100 */
	uint32_t isp_hist256_h_offs;	/*!< Register of  hist 256, address 0x00002104 */
	uint32_t isp_hist256_v_offs;	/*!< Register of  hist 256, address 0x00002108 */
	uint32_t isp_hist256_h_size;	/*!< Register of  hist 256, address 0x0000210c */
	uint32_t isp_hist256_v_size;	/*!< Register of  hist 256, address 0x00002110 */
	uint32_t isp_hist256_bin_n;	/*!< Register of  hist 256, address 0x00002114 */
	uint32_t _notused_22_1[(0x00002154 - 0x00002118) / 4];	/* gap in address space */
	uint32_t isp_hist256_weight_00to30;	/*!< Register of  hist 256, address 0x00002154 */
	uint32_t isp_hist256_weight_40to21;	/*!< Register of  hist 256, address 0x00002158 */
	uint32_t isp_hist256_weight_31to12;	/*!< Register of  hist 256, address 0x0000215C */
	uint32_t isp_hist256_weight_22to03;	/*!< Register of  hist 256, address 0x00002160 */
	uint32_t isp_hist256_weight_13to43;	/*!< Register of  hist 256, address 0x00002164 */
	uint32_t isp_hist256_weight_04to34;	/*!< Register of  hist 256, address 0x00002168; */
	uint32_t isp_hist256_weight_44;	/*!< Register of  hist 256, address 0x0000216C */
	uint32_t _notused_22[(0x00002200 - 0x00002170) / 4];	/* gap in address space */
#else
	uint32_t _notused_22[(0x00002200 - 0x0000203c) / 4];	/* gap in address space */
#endif
	uint32_t isp_lsc_ctrl;	/*!< Lens shade control (rw) MRV_LSC_BASE + 0x00000000 */
	uint32_t isp_lsc_r_table_addr;	/*!< Table RAM Address for red component (rwhh) MRV_LSC_BASE + 0x00000004 */
	uint32_t isp_lsc_gr_table_addr;	/*!< Table RAM Address for green (red) component (rwhh) MRV_LSC_BASE + 0x00000008 */
	uint32_t isp_lsc_b_table_addr;	/*!< Table RAM Address for blue component (rwhh) MRV_LSC_BASE + 0x0000000c */
	uint32_t isp_lsc_gb_table_addr;	/*!< Table RAM Address for green (blue) component (rwhh) MRV_LSC_BASE + 0x00000010 */
	uint32_t isp_lsc_r_table_data;	/*!< Sample table red (rw) MRV_LSC_BASE + 0x00000014 */
	uint32_t isp_lsc_gr_table_data;	/*!< Sample table green (red) (rw) MRV_LSC_BASE + 0x00000018 */
	uint32_t isp_lsc_b_table_data;	/*!< Sample table blue (rw) MRV_LSC_BASE + 0x0000001c */
	uint32_t isp_lsc_gb_table_data;	/*!< Sample table green (blue) (rw) MRV_LSC_BASE + 0x00000020 */
	uint32_t isp_lsc_xgrad_01;	/*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000024 */
	uint32_t isp_lsc_xgrad_23;	/*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000028 */
	uint32_t isp_lsc_xgrad_45;	/*!< Gradient table x (rw) MRV_LSC_BASE + 0x0000002c */
	uint32_t isp_lsc_xgrad_67;	/*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000030 */
	uint32_t isp_lsc_ygrad_01;	/*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000034 */
	uint32_t isp_lsc_ygrad_23;	/*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000038 */
	uint32_t isp_lsc_ygrad_45;	/*!< Gradient table y (rw) MRV_LSC_BASE + 0x0000003c */
	uint32_t isp_lsc_ygrad_67;	/*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000040 */
	uint32_t isp_lsc_xsize_01;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000044 */
	uint32_t isp_lsc_xsize_23;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000048 */
	uint32_t isp_lsc_xsize_45;	/*!< Size table (rw) MRV_LSC_BASE + 0x0000004c */
	uint32_t isp_lsc_xsize_67;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000050 */
	uint32_t isp_lsc_ysize_01;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000054 */
	uint32_t isp_lsc_ysize_23;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000058 */
	uint32_t isp_lsc_ysize_45;	/*!< Size table (rw) MRV_LSC_BASE + 0x0000005c */
	uint32_t isp_lsc_ysize_67;	/*!< Size table (rw) MRV_LSC_BASE + 0x00000060 */
	uint32_t isp_lsc_table_sel;	/*!< Lens shade table set selection (rw) MRV_LSC_BASE + 0x00000064 */
	uint32_t isp_lsc_status;	/*!< Lens shade status (r) MRV_LSC_BASE + 0x00000068 */
	uint32_t _notused_23[(0x00002300 - 0x0000226c) / 4];	/* gap in address space */
	uint32_t isp_is_ctrl;	/*!< Image Stabilization Control Register (rw) MRV_IS_BASE + 0x00000000 */
	uint32_t isp_is_recenter;	/*!< Recenter register (rw) MRV_IS_BASE + 0x00000004 */
	uint32_t isp_is_h_offs;	/*!< Horizontal offset of output window (rw) MRV_IS_BASE + 0x00000008 */
	uint32_t isp_is_v_offs;	/*!< Vertical offset of output window (rw) MRV_IS_BASE + 0x0000000c */
	uint32_t isp_is_h_size;	/*!< Output horizontal picture size (rw) MRV_IS_BASE + 0x00000010 */
	uint32_t isp_is_v_size;	/*!< Output vertical picture size (rw) MRV_IS_BASE + 0x00000014 */
	uint32_t isp_is_max_dx;	/*!< Maximum Horizontal Displacement (rw) MRV_IS_BASE + 0x00000018 */
	uint32_t isp_is_max_dy;	/*!< Maximum Vertical Displacement (rw) MRV_IS_BASE + 0x0000001c */
	uint32_t isp_is_displace;	/*!< Camera displacement (rw) MRV_IS_BASE + 0x00000020 */
	uint32_t isp_is_h_offs_shd;	/*!< current horizontal offset of output window (shadow register) (r) MRV_IS_BASE + 0x00000024 */
	uint32_t isp_is_v_offs_shd;	/*!< current vertical offset of output window (shadow register) (r) MRV_IS_BASE + 0x00000028 */
	uint32_t isp_is_h_size_shd;	/*!< current output horizontal picture size (shadow register) (r) MRV_IS_BASE + 0x0000002c */
	uint32_t isp_is_v_size_shd;	/*!< current output vertical picture size (shadow register) (r) MRV_IS_BASE + 0x00000030 */
#ifdef ISP_RAWIS
	uint32_t _notused_23_1[(0x00002340 - 0x00002334) / 4];	/* gap in address space */
	uint32_t isp_raw_is_ctrl;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002340 */
	uint32_t isp_raw_is_recenter;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002344 */
	uint32_t isp_raw_is_h_offs;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002348 */
	uint32_t isp_raw_is_v_offs;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000234c */
	uint32_t isp_raw_is_h_size;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002350 */
	uint32_t isp_raw_is_v_size;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002354 */
	uint32_t isp_raw_is_max_dx;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002358 */
	uint32_t isp_raw_is_max_dy;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000235c */
	uint32_t isp_raw_is_displace;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002360 */
	uint32_t isp_raw_is_h_offs_shd;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002364 */
	uint32_t isp_raw_is_v_offs_shd;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002368 */
	uint32_t isp_raw_is_h_size_shd;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000236c */
	uint32_t isp_raw_is_v_size_shd;	/*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002370 */
	uint32_t _notused_24[(0x00002400 - 0x00002374) / 4];	/* gap in address space */
#else
	uint32_t _notused_24[(0x00002400 - 0x00002334) / 4];	/* gap in address space */
#endif
	uint32_t isp_hist_prop;	/*!< Histogram properties (rw) MRV_HIST_BASE + 0x00000000 */
	uint32_t isp_hist_h_offs;	/*!< Histogram window horizontal offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000004 */
	uint32_t isp_hist_v_offs;	/*!< Histogram window vertical offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000008 */
	uint32_t isp_hist_h_size;	/*!< Horizontal (sub-)window size (rw) MRV_HIST_BASE + 0x0000000c */
	uint32_t isp_hist_v_size;	/*!< Vertical (sub-)window size (rw) MRV_HIST_BASE + 0x00000010 */
	histogram_measurement_result_t histogram_measurement_result_arr[HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE];	/*!< histogram_measurement_result MRV_HIST_BASE + 20 + (n*0x4) (n=0..15) */
	uint32_t isp_hist_weight_00to30;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000054 */
	uint32_t isp_hist_weight_40to21;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000058 */
	uint32_t isp_hist_weight_31to12;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x0000005c */
	uint32_t isp_hist_weight_22to03;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000060 */
	uint32_t isp_hist_weight_13to43;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000064 */
	uint32_t isp_hist_weight_04to34;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000068 */
	uint32_t isp_hist_weight_44;	/*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x0000006c */
	uint32_t _notused_25[(0x00002500 - 0x00002470) / 4];	/* gap in address space */
	uint32_t isp_filt_mode;	/*!< mode control register for the filter block (rw) MRV_FILT_BASE + 0x00000000 */
	uint32_t _notused_26[(0x00002528 - 0x00002504) / 4];	/* gap in address space */
	uint32_t isp_filt_thresh_bl0;	/*!< Blurring threshold 0 (rw) MRV_FILT_BASE + 0x00000028 */
	uint32_t isp_filt_thresh_bl1;	/*!< Blurring threshold 1 (rw) MRV_FILT_BASE + 0x0000002c */
	uint32_t isp_filt_thresh_sh0;	/*!< Sharpening threshold 0 (rw) MRV_FILT_BASE + 0x00000030 */
	uint32_t isp_filt_thresh_sh1;	/*!< Sharpening threshold 1 (rw) MRV_FILT_BASE + 0x00000034 */
	uint32_t isp_filt_lum_weight;	/*!< Parameters for luminance weight function (rw) MRV_FILT_BASE + 0x00000038 */
	uint32_t isp_filt_fac_sh1;	/*!< filter factor sharp1 (rw) MRV_FILT_BASE + 0x0000003c */
	uint32_t isp_filt_fac_sh0;	/*!< filter factor sharp0 (rw) MRV_FILT_BASE + 0x00000040 */
	uint32_t isp_filt_fac_mid;	/*!< filter factor middle (rw) MRV_FILT_BASE + 0x00000044 */
	uint32_t isp_filt_fac_bl0;	/*!< Parameter for blur 0 filter (rw) MRV_FILT_BASE + 0x00000048 */
	uint32_t isp_filt_fac_bl1;	/*!< Parameter for blur 1 filter (rw) MRV_FILT_BASE + 0x0000004c */
	uint32_t _notused_27[(0x00002580 - 0x00002550) / 4];	/* gap in address space */
	uint32_t isp_cac_ctrl;	/*!< Control register for chromatic aberration correction (rw) MRV_CAC_BASE + 0x00000000 */
	uint32_t isp_cac_count_start;	/*!< Preload values for CAC pixel and line counter (rw) MRV_CAC_BASE + 0x00000004 */
	uint32_t isp_cac_a;	/*!< Linear Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x00000008 */
	uint32_t isp_cac_b;	/*!< Square Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x0000000c */
	uint32_t isp_cac_c;	/*!< Cubical Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x00000010 */
	uint32_t isp_cac_x_norm;	/*!< Normalization parameters for calculation of image coordinate x_d relative to optical center (rw) MRV_CAC_BASE + 0x00000014 */
	uint32_t isp_cac_y_norm;	/*!< Normalization parameters for calculation of image coordinate y_d relative to optical center (rw) MRV_CAC_BASE + 0x00000018 */
	uint32_t _notused_28[(0x00002600 - 0x0000259c) / 4];	/* gap in address space */
	uint32_t isp_exp_ctrl;	/*!< Exposure control (rw) MRV_AE_BASE + 0x00000000 */
	uint32_t isp_exp_h_offset;	/*!< Horizontal offset for first block (rw) MRV_AE_BASE + 0x00000004 */
	uint32_t isp_exp_v_offset;	/*!< Vertical offset for first block (rw) MRV_AE_BASE + 0x00000008 */
	uint32_t isp_exp_h_size;	/*!< Horizontal size of one block (rw) MRV_AE_BASE + 0x0000000c */
	uint32_t isp_exp_v_size;	/*!< Vertical size of one block (rw) MRV_AE_BASE + 0x00000010 */
	uint32_t isp_exp_mean_00;	/*!< Mean luminance value of block 00 (r) MRV_AE_BASE + 0x00000014 */
	uint32_t isp_exp_mean_10;	/*!< Mean luminance value of block 10 (r) MRV_AE_BASE + 0x00000018 */
	uint32_t isp_exp_mean_20;	/*!< Mean luminance value of block 20 (r) MRV_AE_BASE + 0x0000001c */
	uint32_t isp_exp_mean_30;	/*!< Mean luminance value of block 30 (r) MRV_AE_BASE + 0x00000020 */
	uint32_t isp_exp_mean_40;	/*!< Mean luminance value of block 40 (r) MRV_AE_BASE + 0x00000024 */
	uint32_t isp_exp_mean_01;	/*!< Mean luminance value of block 01 (r) MRV_AE_BASE + 0x00000028 */
	uint32_t isp_exp_mean_11;	/*!< Mean luminance value of block 11 (r) MRV_AE_BASE + 0x0000002c */
	uint32_t isp_exp_mean_21;	/*!< Mean luminance value of block 21 (r) MRV_AE_BASE + 0x00000030 */
	uint32_t isp_exp_mean_31;	/*!< Mean luminance value of block 31 (r) MRV_AE_BASE + 0x00000034 */
	uint32_t isp_exp_mean_41;	/*!< Mean luminance value of block 41 (r) MRV_AE_BASE + 0x00000038 */
	uint32_t isp_exp_mean_02;	/*!< Mean luminance value of block 02 (r) MRV_AE_BASE + 0x0000003c */
	uint32_t isp_exp_mean_12;	/*!< Mean luminance value of block 12 (r) MRV_AE_BASE + 0x00000040 */
	uint32_t isp_exp_mean_22;	/*!< Mean luminance value of block 22 (r) MRV_AE_BASE + 0x00000044 */
	uint32_t isp_exp_mean_32;	/*!< Mean luminance value of block 32 (r) MRV_AE_BASE + 0x00000048 */
	uint32_t isp_exp_mean_42;	/*!< Mean luminance value of block 42 (r) MRV_AE_BASE + 0x0000004c */
	uint32_t isp_exp_mean_03;	/*!< Mean luminance value of block 03 (r) MRV_AE_BASE + 0x00000050 */
	uint32_t isp_exp_mean_13;	/*!< Mean luminance value of block 13 (r) MRV_AE_BASE + 0x00000054 */
	uint32_t isp_exp_mean_23;	/*!< Mean luminance value of block 23 (r) MRV_AE_BASE + 0x00000058 */
	uint32_t isp_exp_mean_33;	/*!< Mean luminance value of block 33 (r) MRV_AE_BASE + 0x0000005c */
	uint32_t isp_exp_mean_43;	/*!< Mean luminance value of block 43 (r) MRV_AE_BASE + 0x00000060 */
	uint32_t isp_exp_mean_04;	/*!< Mean luminance value of block 04 (r) MRV_AE_BASE + 0x00000064 */
	uint32_t isp_exp_mean_14;	/*!< Mean luminance value of block 14 (r) MRV_AE_BASE + 0x00000068 */
	uint32_t isp_exp_mean_24;	/*!< Mean luminance value of block 24 (r) MRV_AE_BASE + 0x0000006c */
	uint32_t isp_exp_mean_34;	/*!< Mean luminance value of block 34 (r) MRV_AE_BASE + 0x00000070 */
	uint32_t isp_exp_mean_44;	/*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000074 */
#ifdef ISP_AE_SHADOW
	uint32_t isp_exp_h_offset_shd;	/*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000078 */
	uint32_t isp_exp_v_offset_shd;	/*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x0000007C */
	uint32_t isp_exp_h_size_shd;	/*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000080 */
	uint32_t isp_exp_v_size_shd;	/*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000084 */
	uint32_t _notused_isp_exp[(0x000026A0 - 0x00002688) / 4];
	uint32_t isp_expv2_ctrl;	/* 0x000026A0; */
	uint32_t isp_expv2_offset;	/* 0x000026A4; */
	uint32_t isp_expv2_size;	/* 0x000026A8; */
	uint32_t isp_expv2_size_invert;	/* 0x000026AC; */
	uint32_t isp_expv2_pixel_weight;	/* 0x000026B0; */
	uint32_t isp_expv2_offset_shd;	/* 0x000026B4; */
	uint32_t isp_expv2_size_shd;	/* 0x000026B8; */
	uint32_t isp_expv2_size_invert_shd;	/* 0x000026BC; */
	uint32_t _notused_29[(0x00002700 - 0x000026C0) / 4];	/* gap in address space */
#else
	uint32_t _notused_isp_exp[(0x00002680 - 0x00002678) / 4];
	uint32_t isp_expv2_ctrl;	/* 0x00002680; */
	uint32_t isp_expv2_offset;	/* 0x00002684; */
	uint32_t isp_expv2_size;	/* 0x00002688; */
	uint32_t isp_expv2_size_invert;	/* 0x0000268c; */
	uint32_t isp_expv2_pixel_weight;	/* 0x00002690; */
	uint32_t _notused_29[(0x00002700 - 0x00002694) / 4];	/* gap in address space */
#endif
	uint32_t isp_bls_ctrl;	/*!< global control register (rw) MRV_BLS_BASE + 0x00000000 */
	uint32_t isp_bls_samples;	/*!< samples register (rw) MRV_BLS_BASE + 0x00000004 */
	uint32_t isp_bls_h1_start;	/*!< window 1 horizontal start (rw) MRV_BLS_BASE + 0x00000008 */
	uint32_t isp_bls_h1_stop;	/*!< window 1 horizontal stop (rw) MRV_BLS_BASE + 0x0000000c */
	uint32_t isp_bls_v1_start;	/*!< window 1 vertical start (rw) MRV_BLS_BASE + 0x00000010 */
	uint32_t isp_bls_v1_stop;	/*!< window 1 vertical stop (rw) MRV_BLS_BASE + 0x00000014 */
	uint32_t isp_bls_h2_start;	/*!< window 2 horizontal start (rw) MRV_BLS_BASE + 0x00000018 */
	uint32_t isp_bls_h2_stop;	/*!< window 2 horizontal stop (rw) MRV_BLS_BASE + 0x0000001c */
	uint32_t isp_bls_v2_start;	/*!< window 2 vertical start (rw) MRV_BLS_BASE + 0x00000020 */
	uint32_t isp_bls_v2_stop;	/*!< window 2 vertical stop (rw) MRV_BLS_BASE + 0x00000024 */
	uint32_t isp_bls_a_fixed;	/*!< fixed black level A (rw) MRV_BLS_BASE + 0x00000028 */
	uint32_t isp_bls_b_fixed;	/*!< fixed black level B (rw) MRV_BLS_BASE + 0x0000002c */
	uint32_t isp_bls_c_fixed;	/*!< fixed black level C (rw) MRV_BLS_BASE + 0x00000030 */
	uint32_t isp_bls_d_fixed;	/*!< fixed black level D (rw) MRV_BLS_BASE + 0x00000034 */
	uint32_t isp_bls_a_measured;	/*!< measured black level A (r) MRV_BLS_BASE + 0x00000038 */
	uint32_t isp_bls_b_measured;	/*!< measured black level B (r) MRV_BLS_BASE + 0x0000003c */
	uint32_t isp_bls_c_measured;	/*!< measured black level C (r) MRV_BLS_BASE + 0x00000040 */
	uint32_t isp_bls_d_measured;	/*!< measured black level D (r) MRV_BLS_BASE + 0x00000044 */
	uint32_t _notused_30[(0x00002800 - 0x00002748) / 4];	/* gap in address space */
	uint32_t isp_dpf_mode;	/*!< Mode control for Denoising Pre-Filter block (rw) MRV_DPF_BASE + 0x00000000 */
	uint32_t isp_dpf_strength_r;	/*!< filter strength of the RED filter (rw) MRV_DPF_BASE + 0x00000004 */
	uint32_t isp_dpf_strength_g;	/*!< filter strength of the GREEN filter (rw) MRV_DPF_BASE + 0x00000008 */
	uint32_t isp_dpf_strength_b;	/*!< filter strength of the BLUE filter (rw) MRV_DPF_BASE + 0x0000000c */
	uint32_t isp_dpf_s_weight_g_1_4;	/*!< Spatial Weights green channel 1 2 3 4 (rw) MRV_DPF_BASE + 0x00000010 */
	uint32_t isp_dpf_s_weight_g_5_6;	/*!< Spatial Weights green channel 5 6 (rw) MRV_DPF_BASE + 0x00000014 */
	uint32_t isp_dpf_s_weight_rb_1_4;	/*!< Spatial Weights red/blue channels 1 2 3 4 (rw) MRV_DPF_BASE + 0x00000018 */
	uint32_t isp_dpf_s_weight_rb_5_6;	/*!< Spatial Weights red/blue channels 5 6 (rw) MRV_DPF_BASE + 0x0000001c */
	nlf_lookup_table_block_t nlf_lookup_table_block_arr[NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE];	/*!< nlf_lookup_table_block MRV_DPF_BASE + 32 + (n*0x4) (n=0..16) */
	uint32_t isp_dpf_nf_gain_r;	/*!< noise function gain for red pixels (rw) MRV_DPF_BASE + 0x00000064 */
	uint32_t isp_dpf_nf_gain_gr;	/*!< noise function gain for green in red pixels (rw) MRV_DPF_BASE + 0x00000068 */
	uint32_t isp_dpf_nf_gain_gb;	/*!< noise function gain for green in blue pixels (rw) MRV_DPF_BASE + 0x0000006c */
	uint32_t isp_dpf_nf_gain_b;	/*!< noise function gain for blue pixels (rw) MRV_DPF_BASE + 0x00000070 */
	uint32_t _notused_31[(0x00002900 - 0x00002874) / 4];	/* gap in address space */
	uint32_t isp_dpcc_mode;	/*!< Mode control for DPCC detection unit (rw) MRV_DPCC_BASE + 0x00000000 */
	uint32_t isp_dpcc_output_mode;	/*!< Interpolation mode for correction unit (rw) MRV_DPCC_BASE + 0x00000004 */
	uint32_t isp_dpcc_set_use;	/*!< DPCC methods set usage for detection (rw) MRV_DPCC_BASE + 0x00000008 */
	uint32_t isp_dpcc_methods_set_1;	/*!< Methods enable bits for SET_1 (rw) MRV_DPCC_BASE + 0x0000000c */
	uint32_t isp_dpcc_methods_set_2;	/*!< Methods enable bits for SET_2 (rw) MRV_DPCC_BASE + 0x00000010 */
	uint32_t isp_dpcc_methods_set_3;	/*!< Methods enable bits for SET_3 (rw) MRV_DPCC_BASE + 0x00000014 */
	uint32_t isp_dpcc_line_thresh_1;	/*!< Line threshold SET_1 (rw) MRV_DPCC_BASE + 0x00000018 */
	uint32_t isp_dpcc_line_mad_fac_1;	/*!< Mean Absolute Difference (MAD) factor for Line check set 1 (rw) MRV_DPCC_BASE + 0x0000001c */
	uint32_t isp_dpcc_pg_fac_1;	/*!< Peak gradient factor for set 1 (rw) MRV_DPCC_BASE + 0x00000020 */
	uint32_t isp_dpcc_rnd_thresh_1;	/*!< Rank Neighbor Difference threshold for set 1 (rw) MRV_DPCC_BASE + 0x00000024 */
	uint32_t isp_dpcc_rg_fac_1;	/*!< Rank gradient factor for set 1 (rw) MRV_DPCC_BASE + 0x00000028 */
	uint32_t isp_dpcc_line_thresh_2;	/*!< Line threshold set 2 (rw) MRV_DPCC_BASE + 0x0000002c */
	uint32_t isp_dpcc_line_mad_fac_2;	/*!< Mean Absolute Difference (MAD) factor for Line check set 2 (rw) MRV_DPCC_BASE + 0x00000030 */
	uint32_t isp_dpcc_pg_fac_2;	/*!< Peak gradient factor for set 2 (rw) MRV_DPCC_BASE + 0x00000034 */
	uint32_t isp_dpcc_rnd_thresh_2;	/*!< Rank Neighbor Difference threshold for set 2 (rw) MRV_DPCC_BASE + 0x00000038 */
	uint32_t isp_dpcc_rg_fac_2;	/*!< Rank gradient factor for set 2 (rw) MRV_DPCC_BASE + 0x0000003c */
	uint32_t isp_dpcc_line_thresh_3;	/*!< Line threshold set 3 (rw) MRV_DPCC_BASE + 0x00000040 */
	uint32_t isp_dpcc_line_mad_fac_3;	/*!< Mean Absolute Difference (MAD) factor for Line check set 3 (rw) MRV_DPCC_BASE + 0x00000044 */
	uint32_t isp_dpcc_pg_fac_3;	/*!< Peak gradient factor for set 3 (rw) MRV_DPCC_BASE + 0x00000048 */
	uint32_t isp_dpcc_rnd_thresh_3;	/*!< Rank Neighbor Difference threshold for set 3 (rw) MRV_DPCC_BASE + 0x0000004c */
	uint32_t isp_dpcc_rg_fac_3;	/*!< Rank gradient factor for set 3 (rw) MRV_DPCC_BASE + 0x00000050 */
	uint32_t isp_dpcc_ro_limits;	/*!< Rank Order Limits (rw) MRV_DPCC_BASE + 0x00000054 */
	uint32_t isp_dpcc_rnd_offs;	/*!< Differential Rank Offsets for Rank Neighbor Difference (rw) MRV_DPCC_BASE + 0x00000058 */
	uint32_t isp_dpcc_bpt_ctrl;	/*!< bad pixel table settings (rw) MRV_DPCC_BASE + 0x0000005c */
	uint32_t isp_dpcc_bpt_number;	/*!< Number of entries for bad pixel table (table based correction) (rw) MRV_DPCC_BASE + 0x00000060 */
	uint32_t isp_dpcc_bpt_addr;	/*!< TABLE Start Address for table-based correction algorithm (rwhh) MRV_DPCC_BASE + 0x00000064 */
	uint32_t isp_dpcc_bpt_data;	/*!< TABLE DATA register for read and write access of table RAM (rwhh) MRV_DPCC_BASE + 0x00000068 */
	uint32_t _notused_32[(0x00002a00 - 0x0000296c) / 4];	/* gap in address space */
	uint32_t isp_wdr_ctrl;	/*!< Control Bits for Wide Dynamic Range Unit (rw) MRV_WDR_BASE + 0x00000000 */
	uint32_t isp_wdr_tonecurve_1;	/*!< Tone Curve sample points dYn definition (part 1) (rw) MRV_WDR_BASE + 0x00000004 */
	uint32_t isp_wdr_tonecurve_2;	/*!< Tone Curve sample points dYn definition (part 2) (rw) MRV_WDR_BASE + 0x00000008 */
	uint32_t isp_wdr_tonecurve_3;	/*!< Tone Curve sample points dYn definition (part 3) (rw) MRV_WDR_BASE + 0x0000000c */
	uint32_t isp_wdr_tonecurve_4;	/*!< Tone Curve sample points dYn definition (part 4) (rw) MRV_WDR_BASE + 0x00000010 */
	wdr_tone_mapping_curve_y_block_t wdr_tone_mapping_curve_y_block_arr[WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE];	/*!< wdr_tone_mapping_curve_y_block MRV_WDR_BASE + 20 + (n*0x4) (n=0..32) */
	uint32_t isp_wdr_offset;	/*!< Offset values for RGB path (rw) MRV_WDR_BASE + 0x00000098 */
	uint32_t isp_wdr_deltamin;	/*!< DeltaMin Threshold and Strength factor (rw) MRV_WDR_BASE + 0x0000009c */
	uint32_t isp_wdr_tonecurve_1_shd;	/*!< Tone Curve sample points dYn definition shadow register (part 1) (r) MRV_WDR_BASE + 0x000000a0 */
	uint32_t isp_wdr_tonecurve_2_shd;	/*!< Tone Curve sample points dYn definition shadow register (part 2) (r) MRV_WDR_BASE + 0x000000a4 */
	uint32_t isp_wdr_tonecurve_3_shd;	/*!< Tone Curve sample points dYn definition shadow register (part 3) (r) MRV_WDR_BASE + 0x000000a8 */
	uint32_t isp_wdr_tonecurve_4_shd;	/*!< Tone Curve sample points dYn definition shadow register(part 4) (r) MRV_WDR_BASE + 0x000000ac */
	wdr_tone_mapping_curve_y_shd_block_t wdr_tone_mapping_curve_y_shd_block_arr[WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE];	/*!< wdr_tone_mapping_curve_y_shd_block MRV_WDR_BASE + 176 + (n*0x4) (n=0..32) */
	uint32_t _notused_33[(0x00002c00 - 0x00002b34) / 4];	/* gap in address space */
	uint32_t awb_meas_mode;	/*!< AWB Measure Mode (rw) ISP_AWB_BASE + 0x00000000 */
	uint32_t awb_meas_h_offs;	/*!< AWB window horizontal offset (rw) ISP_AWB_BASE + 0x00000004 */
	uint32_t awb_meas_v_offs;	/*!< AWB window vertical offset (rw) ISP_AWB_BASE + 0x00000008 */
	uint32_t awb_meas_h_size;	/*!< Horizontal window size (rw) ISP_AWB_BASE + 0x0000000c */
	uint32_t awb_meas_v_size;	/*!< Vertical window size (rw) ISP_AWB_BASE + 0x00000010 */
	uint32_t awb_meas_r_min_max;	/*!< Min Max Compare Red (rw) ISP_AWB_BASE + 0x00000014 */
	uint32_t awb_meas_g_min_max;	/*!< Min Max Compare Green (rw) ISP_AWB_BASE + 0x00000018 */
	uint32_t awb_meas_b_min_max;	/*!< Min Max Compare Blue (rw) ISP_AWB_BASE + 0x0000001c */
	uint32_t awb_meas_divider_min;	/*!< Min Compare Divider (rw) ISP_AWB_BASE + 0x00000020 */
	uint32_t awb_meas_csc_coeff[9];	/*!< Color conversion coefficient 0 (rw) ISP_AWB_BASE + 0x00000024 */
	elawb_ellipse_pt awb_meas_center[8];	/*!< Ellipse 1 Center X (rw) ISP_AWB_BASE + 0x00000048 */
	elawb_ellipse_axis awb_meas_axis[8];	/*!< Ellipse 1 coefficient a1 (rw) ISP_AWB_BASE + 0x00000088 */
	uint32_t awb_meas_rmax[8];	/*!< Ellipse 1 r_max (rw) ISP_AWB_BASE + 0x00000108 */
	uint32_t awb_meas_counter[8];	/*!< AWB Counter 1 (r) ISP_AWB_BASE + 0x00000128 */
	AWB_MEAS_ACCU_t AWB_MEAS_ACCU_arr[AWB_MEAS_ACCU_ARR_SIZE];	/*!< AWB_MEAS_ACCU ISP_AWB_BASE + 328 + (n*0x4) (n=0..23) */
	uint32_t _notused_34[(0x00002e00 - 0x00002da8) / 4];	/* gap in address space */
	uint32_t isp64_hist_ctrl;	/*!< Histogram control (rw) MRV_HIST_BASE + 0x00000000 */
	uint32_t isp64_hist_prop;	/*!< Histogram properties (sh_rw) MRV_HIST_BASE + 0x00000004 */
	uint32_t isp64_hist_subsampling;	/*!< Subsampling properties (sh_rw) MRV_HIST_BASE + 0x00000008 */
	uint32_t isp64_hist_coeff_r;	/*!< Color conversion coefficient for red (sh_rw) MRV_HIST_BASE + 0x0000000c */
	uint32_t isp64_hist_coeff_g;	/*!< Color conversion coefficient for green (sh_rw) MRV_HIST_BASE + 0x00000010 */
	uint32_t isp64_hist_coeff_b;	/*!< Color conversion coefficient for blue (sh_rw) MRV_HIST_BASE + 0x00000014 */
	uint32_t isp64_hist_h_offs;	/*!< Histogram window horizontal offset for first window of 25 sub-windows (sh_rw) MRV_HIST_BASE + 0x00000018 */
	uint32_t isp64_hist_v_offs;	/*!< Histogram window vertical offset for first window of 25 sub-windows (sh_rw) MRV_HIST_BASE + 0x0000001c */
	uint32_t isp64_hist_h_size;	/*!< Horizontal (sub-)window size (sh_rw) MRV_HIST_BASE + 0x00000020 */
	uint32_t isp64_hist_v_size;	/*!< Vertical (sub-)window size (sh_rw) MRV_HIST_BASE + 0x00000024 */
	uint32_t isp64_hist_sample_range;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000028 */
	uint32_t isp64_hist_weight_00to30;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x0000002c */
	uint32_t isp64_hist_weight_40to21;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000030 */
	uint32_t isp64_hist_weight_31to12;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000034 */
	uint32_t isp64_hist_weight_22to03;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000038 */
	uint32_t isp64_hist_weight_13to43;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x0000003c */
	uint32_t isp64_hist_weight_04to34;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000040 */
	uint32_t isp64_hist_weight_44;	/*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000044 */
	uint32_t isp64_hist_forced_upd_start_line;	/*!< Forced update start line limit (rw) MRV_HIST_BASE + 0x00000048 */
	uint32_t isp64_hist_forced_update;	/*!< Histogram forced update (w) MRV_HIST_BASE + 0x0000004c */
	uint32_t isp64_hist_vstart_status;	/*!< Forced update start line status (sh_r) MRV_HIST_BASE + 0x00000050 */
	isp64_histogram_measurement_result_t isp64_histogram_measurement_result_arr[ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE];	/*!< isp64_histogram_measurement_result MRV_HIST_BASE + 84 + (n*0x4) (n=0..31) */
	uint32_t _notused_35[(0x00002f00 - 0x00002ed4) / 4];	/* gap in address space */
	uint32_t isp_vsm_mode;	/*!< VS Measure Mode (rw) ISP_VSM_BASE + 0x00000000 */
	uint32_t isp_vsm_h_offs;	/*!< VSM window horizontal offset (rw) ISP_VSM_BASE + 0x00000004 */
	uint32_t isp_vsm_v_offs;	/*!< VSM window vertical offset (rw) ISP_VSM_BASE + 0x00000008 */
	uint32_t isp_vsm_h_size;	/*!< Horizontal measure window size (rw) ISP_VSM_BASE + 0x0000000c */
	uint32_t isp_vsm_v_size;	/*!< Vertical measure window size (rw) ISP_VSM_BASE + 0x00000010 */
	uint32_t isp_vsm_h_segments;	/*!< Iteration 1 horizontal segments (rw) ISP_VSM_BASE + 0x00000014 */
	uint32_t isp_vsm_v_segments;	/*!< Iteration 1 vertical segments (rw) ISP_VSM_BASE + 0x00000018 */
	uint32_t isp_vsm_delta_h;	/*!< estimated horizontal displacement (r) ISP_VSM_BASE + 0x0000001c */
	uint32_t isp_vsm_delta_v;	/*!< estimated vertical displacement (r) ISP_VSM_BASE + 0x00000020 */
	uint32_t _notused_36[(0x00003000 - 0x00002f24) / 4];	/* gap in address space */
#ifdef ISP_GCMONO
	uint32_t isp_gcmono_ctrl;	/*!< GCMONO CTRL for ISP Nano MRV_GCMONO_BASE + 0x00000000 */
	uint32_t isp_gcmono_para_base;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE + 0x00000004 */
	uint32_t _notused_37_0[(0x00003040 - 0x00003008) / 4];	/* gap in address space */
	uint32_t isp_gcmono_px_0;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003040 */
	uint32_t isp_gcmono_px_1;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003044 */
	uint32_t isp_gcmono_px_2;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003048 */
	uint32_t isp_gcmono_px_3;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000304C */
	uint32_t isp_gcmono_px_4;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003050 */
	uint32_t isp_gcmono_px_5;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003054 */
	uint32_t isp_gcmono_px_6;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003058 */
	uint32_t isp_gcmono_px_7;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000305C */
	uint32_t isp_gcmono_px_8;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003060 */
	uint32_t isp_gcmono_px_9;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003064 */
	uint32_t isp_gcmono_px_10;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003068 */
	uint32_t isp_gcmono_y_addr;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000306C */
	uint32_t isp_gcmono_y_write_data;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003070 */
	uint32_t isp_gcmono_x_addr;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003074 */
	uint32_t isp_gcmono_x_write_data;	/*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003078 */
	uint32_t _notused_37_1[(0x00003100 - 0x0000307c) / 4];	/* gap in address space */
#else
	uint32_t _notused_37[(0x00003100 - 0x00003000) / 4];	/* gap in address space */
#endif

	/* WDR2 */
	uint32_t isp_wdr2_ctrl;	/*!<(rw), 0x00003100 */
	uint32_t isp_wdr2_blk_siz;	/*!<(rw), 0x00003104 */
	uint32_t isp_wdr2_color_weight;	/*!<(rw), 0x00003108 */
	uint32_t isp_wdr2_blt_sigma;	/*!<(rw), 0x0000310C */
	uint32_t isp_wdr2_blt_kernel_0;	/*!<(rw), 0x00003110 */
	uint32_t isp_wdr2_blt_kernel_1;	/*!<(rw), 0x00003114 */
	uint32_t isp_wdr2_vol_shift_bit;	/*!<(rw), 0x00003118 */
	uint32_t isp_wdr2_bin_dist_0;	/*!<(rw), 0x0000311C */
	uint32_t isp_wdr2_bin_dist_1;	/*!<(rw), 0x00003120 */
	uint32_t isp_wdr2_bin_dist_2;	/*!<(rw), 0x00003124 */
	uint32_t isp_wdr2_bin_dist_3;	/*!<(rw), 0x00003128 */
	uint32_t isp_wdr2_hist_norm_fac;	/*!<(rw), 0x0000312C */

	uint32_t _notused_38[(0x00003138 - 0x00003130) / 4];	/* gap in address space */

	uint32_t isp_wdr2_pre_gamma_lut;	/*!<(rw), 0x00003138 */
	uint32_t isp_wdr2_pre_gamma_write_data;	/*!<(rw), 0x0000313C */
	uint32_t isp_wdr2_tone_curve_lut;	/*!<(rw), 0x00003140 */
	uint32_t isp_wdr2_tone_curve_write_data;	/*!<(rw), 0x00003144 */
	uint32_t isp_wdr2_merge_coeff_lut;	/*!<(rw), 0x00003148 */
	uint32_t isp_wdr2_merge_coeff_write_data;	/*!<(rw), 0x0000314C */
	uint32_t isp_wdr2_pre_gamma_cx_0;	/*!<(rw), 0x00003150 */
	uint32_t isp_wdr2_pre_gamma_cx_1;	/*!<(rw), 0x00003154 */
	uint32_t isp_wdr2_pre_gamma_cx_2;	/*!<(rw), 0x00003158 */
	uint32_t isp_wdr2_pre_gamma_cx_3;	/*!<(rw), 0x0000315C */
	uint32_t isp_wdr2_pre_gamma_cx_4;	/*!<(rw), 0x00003160 */
	uint32_t isp_wdr2_pre_gamma_cx_5;	/*!<(rw), 0x00003164 */
	uint32_t isp_wdr2_pre_gamma_cx_6;	/*!<(rw), 0x00003168 */
	uint32_t isp_wdr2_pre_gamma_cx_7;	/*!<(rw), 0x0000316C */
	uint32_t isp_wdr2_pre_gamma_cx_8;	/*!<(rw), 0x00003170 */
	uint32_t isp_wdr2_pre_gamma_cx_9;	/*!<(rw), 0x00003174 */
	uint32_t isp_wdr2_pre_gamma_cx_10;	/*!<(rw), 0x00003178 */
	uint32_t isp_wdr2_tone_curve_cx_0;	/*!<(rw), 0x0000317C */
	uint32_t isp_wdr2_tone_curve_cx_1;	/*!<(rw), 0x00003180 */
	uint32_t isp_wdr2_tone_curve_cx_2;	/*!<(rw), 0x00003184 */
	uint32_t isp_wdr2_tone_curve_cx_3;	/*!<(rw), 0x00003188 */
	uint32_t isp_wdr2_merge_coeff_cx_0;	/*!<(rw), 0x0000318C */
	uint32_t isp_wdr2_merge_coeff_cx_1;	/*!<(rw), 0x00003190 */

	uint32_t _notused_39[(0x000031A8 - 0x00003194) / 4];	/* gap in address space */

	uint32_t isp_wdr2_max_gain_cx;	/*!<(rw), 0x000031A8 */
	uint32_t isp_wdr2_max_gain_slope_0;	/*!<(rw), 0x000031AC */
	uint32_t isp_wdr2_max_gain_slope_1;	/*!<(rw), 0x000031B0 */
	uint32_t isp_wdr2_max_gain_slope_2;	/*!<(rw), 0x000031B4 */
	uint32_t isp_wdr2_max_gain_cy_0;	/*!<(rw), 0x000031B8 */
	uint32_t isp_wdr2_max_gain_cy_1;	/*!<(rw), 0x000031BC */
	uint32_t isp_wdr2_max_gain_cy_2;	/*!<(rw), 0x000031C0 */
	uint32_t isp_wdr2_norm_factor_mul_0;	/*!<(rw), 0x000031C4 */
	uint32_t isp_wdr2_norm_factor_mul_1;	/*!<(rw), 0x000031C8 */
	uint32_t isp_wdr2_norm_factor_shift_bit_0;	/*!<(rw), 0x000031CC */
	uint32_t isp_wdr2_norm_factor_shift_bit_1;	/*!<(rw), 0x000031D0 */
	uint32_t isp_wdr2_bin_range_0;	/*!<(rw), 0x000031D4 */
	uint32_t isp_wdr2_bin_range_1;	/*!<(rw), 0x000031D8 */
	uint32_t isp_wdr2_bin_range_2;	/*!<(rw), 0x000031DC */
	uint32_t isp_wdr2_bin_range_3;	/*!<(rw), 0x000031E0 */
	uint32_t isp_wdr2_hist_data_0;	/*!<(ro), 0x000031E4 */
	uint32_t isp_wdr2_hist_data_1;	/*!<(ro), 0x000031E8 */

	uint32_t _notused_40[(0x00003200 - 0x000031EC) / 4];	/* gap in address space */

	/* Compand */
	uint32_t isp_compand_ctrl;	/*!<(rw), 0x00003200 */
	uint32_t isp_compand_bls_a_fixed;	/*!<(rw), 0x00003204 */
	uint32_t isp_compand_bls_b_fixed;	/*!<(rw), 0x00003208 */
	uint32_t isp_compand_bls_c_fixed;	/*!<(rw), 0x0000320C */
	uint32_t isp_compand_bls_d_fixed;	/*!<(rw), 0x00003210 */
	uint32_t isp_compand_expand_px_0;	/*!<(rw), 0x00003214 */
	uint32_t isp_compand_expand_px_1;	/*!<(rw), 0x00003218 */
	uint32_t isp_compand_expand_px_2;	/*!<(rw), 0x0000321C */
	uint32_t isp_compand_expand_px_3;	/*!<(rw), 0x00003220 */
	uint32_t isp_compand_expand_px_4;	/*!<(rw), 0x00003224 */
	uint32_t isp_compand_expand_px_5;	/*!<(rw), 0x00003228 */
	uint32_t isp_compand_expand_px_6;	/*!<(rw), 0x0000322C */
	uint32_t isp_compand_expand_px_7;	/*!<(rw), 0x00003230 */
	uint32_t isp_compand_expand_px_8;	/*!<(rw), 0x00003234 */
	uint32_t isp_compand_expand_px_9;	/*!<(rw), 0x00003238 */
	uint32_t isp_compand_expand_px_10;	/*!<(rw), 0x0000323C */
	uint32_t isp_compand_compress_px_0;	/*!<(rw), 0x00003240 */
	uint32_t isp_compand_compress_px_1;	/*!<(rw), 0x00003244 */
	uint32_t isp_compand_compress_px_2;	/*!<(rw), 0x00003248 */
	uint32_t isp_compand_compress_px_3;	/*!<(rw), 0x0000324C */
	uint32_t isp_compand_compress_px_4;	/*!<(rw), 0x00003250 */
	uint32_t isp_compand_compress_px_5;	/*!<(rw), 0x00003254 */
	uint32_t isp_compand_compress_px_6;	/*!<(rw), 0x00003258 */
	uint32_t isp_compand_compress_px_7;	/*!<(rw), 0x0000325C */
	uint32_t isp_compand_compress_px_8;	/*!<(rw), 0x00003260 */
	uint32_t isp_compand_compress_px_9;	/*!<(rw), 0x00003264 */
	uint32_t isp_compand_compress_px_10;	/*!<(rw), 0x00003268 */
	uint32_t isp_compand_expand_y_addr;	/*!<(rw), 0x0000326C */
	uint32_t isp_compand_expand_y_write_data;	/*!<(rw), 0x00003270 */
	uint32_t isp_compand_compress_y_addr;	/*!<(rw), 0x00003274 */
	uint32_t isp_compand_compress_y_write_data;	/*!<(rw), 0x00003278 */
	uint32_t isp_compand_expand_x_addr;	/*!<(rw), 0x0000327C */
	uint32_t isp_compand_expand_x_write_data;	/*!<(rw), 0x00003280 */
	uint32_t isp_compand_compress_x_addr;	/*!<(rw), 0x00003284 */
	uint32_t isp_compand_compress_x_write_data;	/*!<(rw), 0x00003288 */

	uint32_t _notused_41[(0x00003300 - 0x0000328C) / 4];	/* gap in address space */

	uint32_t isp_stitching_ctrl;	/*!<(rw), 0x00003300 */
	uint32_t isp_stitching_frame_width;	/*!<(rw), 0x00003304 */
	uint32_t isp_stitching_frame_height;	/*!<(rw), 0x00003308 */
	uint32_t isp_stitching_exposure_bit;	/*!<(rw), 0x0000330C */
	uint32_t isp_stitching_color_weight;	/*!<(rw), 0x00003310 */
	uint32_t isp_stitching_bls_exp_0_a;	/*!<(rw), 0x00003314 */
	uint32_t isp_stitching_bls_exp_0_b;	/*!<(rw), 0x00003318 */
	uint32_t isp_stitching_bls_exp_0_c;	/*!<(rw), 0x0000331C */
	uint32_t isp_stitching_bls_exp_0_d;	/*!<(rw), 0x00003320 */
	uint32_t isp_stitching_bls_exp_1_a;	/*!<(rw), 0x00003324 */
	uint32_t isp_stitching_bls_exp_1_b;	/*!<(rw), 0x00003328 */
	uint32_t isp_stitching_bls_exp_1_c;	/*!<(rw), 0x0000332C */
	uint32_t isp_stitching_bls_exp_1_d;	/*!<(rw), 0x00003330 */
	uint32_t isp_stitching_bls_exp_2_a;	/*!<(rw), 0x00003334 */
	uint32_t isp_stitching_bls_exp_2_b;	/*!<(rw), 0x00003338 */
	uint32_t isp_stitching_bls_exp_2_c;	/*!<(rw), 0x0000333C */
	uint32_t isp_stitching_bls_exp_2_d;	/*!<(rw), 0x00003340 */
	uint32_t isp_stitching_ratio_ls;	/*!<(rw), 0x00003344 */
	uint32_t isp_stitching_ratio_vs;	/*!<(rw), 0x00003348 */
	uint32_t isp_stitching_ratio_ls_shd;	/*!<(ro), 0x0000334C */
	uint32_t isp_stitching_ratio_vs_shd;	/*!<(ro), 0x00003350 */
	uint32_t isp_stitching_trans_range_linear;	/*!<(rw), 0x00003354 */
	uint32_t isp_stitching_trans_range_nonlinear;	/*!<(rw), 0x00003358 */
	uint32_t isp_stitching_sat_level;	/*!<(rw), 0x0000335C */
	uint32_t isp_stitching_long_exposure;	/*!<(rw), 0x00003360 */
	uint32_t isp_stitching_short_exposure;	/*!<(rw), 0x00003364 */
	uint32_t isp_stitching_very_short_exposure;	/*!<(rw), 0x00003368 */
	uint32_t isp_stitching_hdr_mode;	/*!<(rw), 0x0000336C */
	uint32_t isp_stitching_out_hblank;	/*!<(rw), 0x00003370 */
	uint32_t isp_stitching_out_vblank;	/*!<(rw), 0x00003374 */
	uint32_t isp_stitching_interrupt_status;	/*!<(rw), 0x00003378 */
	uint32_t isp_stitching_compress_x0;	/*!<(rw), 0x0000337c */
	uint32_t isp_stitching_compress_x0_shd;	/*!<(rw), 0x00003380 */
	uint32_t isp_stitching_exposure_mean_0;	/*!<(rw), 0x00003384 */
	uint32_t isp_stitching_exposure_mean_1;	/*!<(rw), 0x00003388 */

	uint32_t _notused_42[(0x000033A0 - 0x0000338C) / 4];	/* gap in address space */

	uint32_t isp_stitching_compress_lut_0;	/*!<(rw), 0x000033A0 */
	uint32_t isp_stitching_compress_lut_1;	/*!<(rw), 0x000033A4 */
	uint32_t isp_stitching_compress_lut_2;	/*!<(rw), 0x000033A8 */
	uint32_t isp_stitching_compress_lut_3;	/*!<(rw), 0x000033AC */
	uint32_t isp_stitching_compress_lut_4;	/*!<(rw), 0x000033B0 */
	/* uint32_t isp_stitching_compress_lut_shd_0;      //!<(ro), 0x000033B4 */
	/* uint32_t isp_stitching_compress_lut_shd_1;      //!<(ro), 0x000033B8 */
	/* uint32_t isp_stitching_compress_lut_shd_2;      //!<(ro), 0x000033BC */
	/* uint32_t isp_stitching_compress_lut_shd_3;      //!<(ro), 0x000033C0 */
	/* uint32_t isp_stitching_compress_lut_shd_4;      //!<(ro), 0x000033C4 */

	uint32_t _notused_43[(0x000033C8 - 0x000033B4) / 4];	/* gap in address space */

	uint32_t isp_stitching_exp0_awb_gain_g;	/*!<(ro), 0x000033C8 */
	uint32_t isp_stitching_exp0_awb_gain_rb;	/*!<(ro), 0x000033CC */
	uint32_t isp_stitching_exp1_awb_gain_g;	/*!<(ro), 0x000033D0 */
	uint32_t isp_stitching_exp1_awb_gain_rb;	/*!<(ro), 0x000033D4 */
	uint32_t isp_stitching_exp2_awb_gain_g;	/*!<(ro), 0x000033D8 */
	uint32_t isp_stitching_exp2_awb_gain_rb;	/*!<(ro), 0x000033DC */
	uint32_t isp_stitching_long_sat_params;	/*!<(ro), 0x000033E0 */
	uint32_t isp_stitching_imsc;	/*!<(rw), 0x000033e4 */
	uint32_t isp_stitching_ris;	/*!<(ro), 0x000033e8 */
	uint32_t isp_stitching_mis;	/*!<(ro), 0x000033ec */
	uint32_t isp_stitching_icr;	/*!<(wo), 0x000033f0 */
	uint32_t isp_stitching_isr;	/*!<(wo), 0x000033f4 */
	uint32_t isp_stitching_bls_exp_out_0;	/*!<(rw), 0x000033f8 */
	uint32_t isp_stitching_bls_exp_out_1;	/*!<(rw), 0x000033fc */
	uint32_t _notused_44[(0x00003500 - 0x00003400) / 4];	/* gap in address space */

	/* WDR3 */
	uint32_t isp_wdr3_ctrl;	/*!<(rw), 0x00003500 */
	uint32_t isp_wdr3_shift;	/*!<(rw), 0x00003504 */
	uint32_t isp_wdr3_block_size;	/*!<(rw), 0x00003508 */
	uint32_t isp_wdr3_block_area_factor;	/*!<(rw), 0x0000350C */
	uint32_t isp_wdr3_value_weight;	/*!<(rw), 0x00003510 */
	uint32_t isp_wdr3_strength;	/*!<(rw), 0x00003514 */
	uint32_t isp_wdr3_pixel_slope;	/*!<(rw), 0x00003518 */
	uint32_t isp_wdr3_entropy_slope;	/*!<(rw), 0x0000351C */
	uint32_t isp_wdr3_sigma_width;	/*!<(rw), 0x00003520 */
	uint32_t isp_wdr3_sigma_height;	/*!<(rw), 0x00003524 */
	uint32_t isp_wdr3_sigma_value;	/*!<(rw), 0x00003528 */
	uint32_t isp_wdr3_block_flag_width;	/*!<(rw), 0x0000352C */
	uint32_t isp_wdr3_block_flag_height;	/*!<(rw), 0x00003530 */
	uint32_t isp_wdr3_frame_average;	/*!<(ro), 0x00003534 */
	uint32_t isp_wdr3_frame_std;	/*!<(ro), 0x00003538 */
	uint32_t isp_wdr3_histogram[5];	/*!<(rw), 0x0000353C */
	uint32_t isp_wdr3_entropy[5];	/*!<(rw), 0x00003550 */
	uint32_t isp_wdr3_gamma_pre[5];	/*!<(rw), 0x00003564 */
	uint32_t isp_wdr3_gamma_up[5];	/*!<(rw), 0x00003578 */
	uint32_t isp_wdr3_gamma_down[5];	/*!<(rw), 0x0000358C */
	uint32_t isp_wdr3_distance_weight[5];	/*!<(rw), 0x000035A0 */
	uint32_t isp_wdr3_difference_weight[5];	/*!<(rw), 0x000035B4 */
	uint32_t isp_wdr3_invert_curve[7];	/*!<(rw), 0x000035C8 */
	uint32_t isp_wdr3_invert_linear[7];	/*!<(rw), 0x000035E4 */
	uint32_t isp_wdr3_shift_0;	/*!<(rw), 0x00003600 */
	uint32_t isp_wdr3_shift_1;	/*!<(rw), 0x00003604 */
	uint32_t isp_wdr3_strength_shd;	/*!<(ro), 0x00003608 */
	uint32_t isp_wdr3_pixel_slope_shd;	/*!<(ro), 0x0000360C */
	uint32_t isp_wdr3_entropy_slope_shd;	/*!<(ro), 0x00003610 */
	uint32_t _notused_44_3dnr[(0x00003700 - 0x00003614) / 4];	/* gap in address space */
	/* 3DNR */
	uint32_t isp_denoise3d_ctrl;	/* 0x00003700 */
	uint32_t isp_denoise3d_strength;	/* 0x00003704 */
	uint32_t isp_denoise3d_edge_h;	/* 0x00003708 */
	uint32_t isp_denoise3d_edge_v;	/* 0x0000370C */
	uint32_t isp_denoise3d_range_s;	/* 0x00003710 */
	uint32_t isp_denoise3d_range_t;	/* 0x00003714 */
	uint32_t isp_denoise3d_motion;	/* 0x00003718 */
	uint32_t isp_denoise3d_delta_inv;	/* 0x0000371C */
	uint32_t isp_denoise3d_curve_s[6];	/* 0x00003720 */
	uint32_t isp_denoise3d_curve_t[6];	/* 0x00003738 */
	uint32_t isp_denoise3d_average;	/* 0x00003750 */
	uint32_t isp_denoise3d_strength_shd;	/* 0x00003754 */
	uint32_t isp_denoise3d_edge_h_shd;	/* 0x00003758 */
	uint32_t isp_denoise3d_edge_v_shd;	/* 0x0000375C */
	uint32_t isp_denoise3d_range_s_shd;	/* 0x00003760 */
	uint32_t isp_denoise3d_range_t_shd;	/* 0x00003764 */
	uint32_t isp_denoise3d_motion_shd;	/* 0x00003768 */
	uint32_t isp_denoise3d_delta_inv_shd;	/* 0x0000376C */
	uint32_t isp_denoise3d_dummy_hblank;	/* 0x00003770 */
	uint32_t isp_denoise3d_ctrl_shd;	/* ro 0x00003774 */
	uint32_t isp_denoise3d_weight1;	/* rw 0x00003778 */
	uint32_t isp_denoise3d_weight2;	/* rw 0x0000377c */
	uint32_t isp_denoise3d_weight1_shd;	/* rw 0x00003780 */
	uint32_t isp_denoise3d_weight2_shd;	/* rw 0x00003784 */

	uint32_t _notused_45[(0x00003900 - 0x00003788) / 4];	/* gap in address space */

	uint32_t isp_ee_ctrl;	/*!<(rw), 0x00003900 */
	uint32_t isp_ee_y_gain;	/*!<(rw), 0x00003904 */
	uint32_t isp_ee_uv_gain;	/*!<(ro), 0x00003908 */
	uint32_t isp_ee_ctrl_shd;	/*!<(ro), 0x0000390C */
	uint32_t isp_ee_y_gain_shd;	/*!<(ro), 0x00003910 */
	uint32_t isp_ee_uv_gain_shd;	/*!<(ro), 0x00003914 */
	uint32_t isp_ee_dummy_hblank;	/*!<(rw), 0x00003918 */
	uint32_t isp_curve_ctrl;	/*!<(rw), 0x0000391c */
	uint32_t isp_curve_lut_x_addr;	/*!<(rw), 0x00003920 */
	uint32_t isp_curve_lut_x_write_data;	/*!<(rw), 0x00003924 */
	uint32_t isp_curve_lut_luma_addr;	/*!<(rw), 0x00003928 */
	uint32_t isp_curve_lut_luma_write_data;	/*!<(rw), 0x0000392c */
	uint32_t isp_curve_lut_chroma_addr;	/*!<(rw), 0x00003930 */
	uint32_t isp_curve_lut_chroma_write_data;	/*!<(rw), 0x00003934 */
	uint32_t isp_curve_lut_shift_addr;	/*!<(rw), 0x00003938 */
	uint32_t isp_curve_lut_shift_write_data;	/*!<(rw), 0x0000393c */
	uint32_t isp_curve_ctrl_shd;	/*!<(ro), 0x00003940 */
	uint32_t isp_curve_lut_luma_addr_shd;	/*!<(ro), 0x00003944 */
	uint32_t isp_curve_lut_luma_write_data_shd;	/*!<(ro), 0x00003948 */
	uint32_t isp_curve_lut_chroma_addr_shd;	/*!<(ro), 0x0000394c */
	uint32_t isp_curve_lut_chroma_write_data_shd;	/*!<(ro), 0x00003950 */
	uint32_t isp_curve_lut_shift_addr_shd;	/*!<(ro), 0x00003954 */
	uint32_t isp_curve_lut_shift_write_data_shd;	/*!<(ro), 0x00003958 */

	uint32_t _notused_46[(0x00003A00 - 0x0000395c) / 4];	/* gap in address space */
	uint32_t isp_denoise2d_control;	/*!<(rw), 0x00003A00 */
	uint32_t isp_denoise2d_strength;	/*!<(rw), 0x00003A04 */
	uint32_t isp_denoise2d_sigma_y[24];	/*!<(rw), 0x00003A08 */
	uint32_t isp_denoise2d_sigma_y_shd[24];	/*!<(ro), 0x00003A68 */
#if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) || defined(ISP_2DNR_V5)
	uint32_t isp_denoise2d_control_shd;	/*!<(ro), 0x00003AC8 */
	uint32_t isp_denoise2d_strength_shd;	/*!<(ro), 0x00003ACC */
	uint32_t isp_denoise2d_sigma_sqr;	/*!<(rw), 0x00003AD0 */
	uint32_t isp_denoise2d_weight_mul_factor;	/*!<(rw), 0x00003AD4 */
	uint32_t isp_denoise2d_sigma_sqr_shd;	/*!<(rw), 0x00003AD8 */
	uint32_t isp_denoise2d_weight_mul_factor_shd;	/*!<(rw), 0x00003ADC */
	uint32_t isp_denoise2d_dummy_hblank;	/*!<(rw), 0x00003AE0 */
	uint32_t isp_denoise2d_motionless_control_curve; /*!<(rw), 0x00003ae4 */
	uint32_t isp_denoise2d_motion_inv; /*!<(rw), 0x00003ae8 */
	uint32_t isp_denoise3d2_blending; /*!<(rw), 0x00003aec */
	uint32_t isp_denoise3d2_blending_shd; /*!<(ro), 0x00003af0 */
	uint32_t _notused_47[(0x00003B00 - 0x00003af4) / 4];	// gap in address space
#else
	uint32_t _notused_47[(0x00003B00 - 0x00003ac8) / 4];	// gap in address space
#endif

	uint32_t isp_hdr_hist_prop;	/*!< Histogram properties (rw) MRV_HIST_BASE + 0x00000000 */
	uint32_t isp_hdr_hist_h_offs;	/*!< Histogram window horizontal offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000004 */
	uint32_t isp_hdr_hist_v_offs;	/*!< Histogram window vertical offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000008 */
	uint32_t isp_hdr_hist_h_size;	/*!< Horizontal (sub-)window size (rw) MRV_HIST_BASE + 0x0000000c */
	uint32_t isp_hdr_hist_v_size;	/*!< Vertical (sub-)window size (rw) MRV_HIST_BASE + 0x00000010 */
	uint32_t isp_hdr_hist_statistics[48];  /*! 16 x 3 channels l/s/vs */
	uint32_t _notused_48 [(0x00003C00 - 0x00003BD4) / 4];  // gap in address space
	uint32_t isp_hdr_exp_conf;  //!<(rw), 0x00003C00
	uint32_t isp_hdr_exp_h_offset;  //!<(rw), 0x00003C04
	uint32_t isp_hdr_exp_v_offset;  //!<(rw), 0x00003C08
	uint32_t isp_hdr_exp_h_size;  //!<(rw), 0x00003C0C
	uint32_t isp_hdr_exp_v_size;  //!<(rw), 0x00003C10
	uint32_t isp_hdr_exp_statistics[75];	 /*! 25 x 3 channels l/s/vs */
	uint32_t isp_hdr_exp_h_offset_shd;  //!<(ro), 0x00003D40
	uint32_t isp_hdr_exp_v_offset_shd;  //!<(ro), 0x00003D44
	uint32_t isp_hdr_exp_h_size_shd;  //!<(ro), 0x00003D48
	uint32_t isp_hdr_exp_v_size_shd;  //!<(ro), 0x00003D4C
	uint32_t _notused_49[(0x00003E00 - 0x00003d50) / 4];
	uint32_t isp_dmsc_ctrl;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000000
	uint32_t isp_dmsc_intp_thr;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000004
	uint32_t isp_dmsc_dmoi_ctrl;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000008
	uint32_t isp_dmsc_dmoi_thr;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000000c
	uint32_t isp_dmsc_dmoi_patn_thr;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000010
	uint32_t isp_dmsc_shap_fact;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000014
	uint32_t isp_dmsc_shap_clip;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000018
	uint32_t isp_dmsc_shap_thr;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000001c
	uint32_t isp_dmsc_shap_ratio;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000020
	uint32_t isp_dmsc_shap_line_ctrl;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000024
	uint32_t isp_dmsc_shap_line_ratio;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000028
	uint32_t isp_dmsc_shap_filt1;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000002c
	uint32_t isp_dmsc_shap_filt2;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000030
	uint32_t isp_dmsc_dpul_ctrl;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000034
	uint32_t isp_dmsc_skin_thr_cb;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000038
	uint32_t isp_dmsc_skin_thr_cr;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000003c
	uint32_t isp_dmsc_skin_thr_y;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000040
	uint32_t isp_dmsc_cac_ctrl;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000044
	uint32_t isp_dmsc_cac_count_start;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000048
	uint32_t isp_dmsc_cac_a;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000004C
	uint32_t isp_dmsc_cac_b;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000050
	uint32_t isp_dmsc_cac_c;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000054
	uint32_t isp_dmsc_cac_x_norm;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000058
	uint32_t isp_dmsc_cac_y_norm;	//!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000005C
	uint32_t isp_dmsc_size_ctrl;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000060
	uint32_t isp_dmsc_ctrl_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000064
	uint32_t isp_dmsc_shap_fact_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000068
	uint32_t isp_dmsc_shap_clip_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000006c
	uint32_t isp_dmsc_dpul_ctrl_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000070
	uint32_t isp_dmsc_cac_ctrl_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000074
	uint32_t isp_dmsc_cac_count_start_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000078
	uint32_t isp_dmsc_cac_a_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000007c
	uint32_t isp_dmsc_cac_b_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000080
	uint32_t isp_dmsc_cac_c_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000084
	uint32_t isp_dmsc_cac_x_norm_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000088
	uint32_t isp_dmsc_cac_y_norm_shd;	//!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000008c

	uint32_t _notused_50[(0x00004000 - 0x00003e90) / 4];
    uint32_t isp_pre_filt_ctrl;     //!< isp_pre_file_base_addres + 0x0000
    uint32_t isp_pre_filt_bls_a;     //!< isp_pre_file_base_addres + 0x0004
    uint32_t isp_pre_filt_bls_b;     //!< isp_pre_file_base_addres + 0x0008
    uint32_t isp_pre_filt_bls_c;     //!< isp_pre_file_base_addres + 0x000c
    uint32_t isp_pre_filt_bls_d;     //!< isp_pre_file_base_addres + 0x0010
    uint32_t isp_pre_filt_gain_r;     //!< isp_pre_file_base_addres + 0x0014
    uint32_t isp_pre_filt_gain_g;     //!< isp_pre_file_base_addres + 0x0018
    uint32_t isp_pre_filt_gain_b;     //!< isp_pre_file_base_addres + 0x001c
    uint32_t isp_pre_filt_dpc_th_r;     //!< isp_pre_file_base_addres + 0x0020
    uint32_t isp_pre_filt_dpc_th_g;     //!< isp_pre_file_base_addres + 0x0024
    uint32_t isp_pre_filt_dpc_th_b;     //!< isp_pre_file_base_addres + 0x0028
    uint32_t isp_pre_filt_dpc_th_ir;     //!< isp_pre_file_base_addres + 0x002c
    uint32_t isp_pre_filt_cc_00_01;     //!< isp_pre_file_base_addres + 0x0030
    uint32_t isp_pre_filt_cc_02_03;     //!< isp_pre_file_base_addres + 0x0034
    uint32_t isp_pre_filt_cc_10_11;     //!< isp_pre_file_base_addres + 0x0038
    uint32_t isp_pre_filt_cc_12_13;     //!< isp_pre_file_base_addres + 0x003c
    uint32_t isp_pre_filt_cc_20_21;     //!< isp_pre_file_base_addres + 0x0040
    uint32_t isp_pre_filt_cc_22_23;     //!< isp_pre_file_base_addres + 0x0044
    uint32_t isp_pre_filt_cc_00_01_shd;     //!< isp_pre_file_base_addres + 0x0048
    uint32_t isp_pre_filt_cc_02_03_shd;     //!< isp_pre_file_base_addres + 0x004c
    uint32_t isp_pre_filt_cc_10_11_shd;     //!< isp_pre_file_base_addres + 0x0050
    uint32_t isp_pre_filt_cc_12_13_shd;     //!< isp_pre_file_base_addres + 0x0054
    uint32_t isp_pre_filt_cc_20_21_shd;     //!< isp_pre_file_base_addres + 0x0058
    uint32_t isp_pre_filt_cc_22_23_shd;     //!< isp_pre_file_base_addres + 0x05c
    uint32_t isp_pre_filt_ir_des_px1;     //!< isp_pre_file_base_addres + 0x0060
    uint32_t _notused_51[(0x00004080 - 0x00004064) / 4];
    uint32_t isp_pre_filt_ir_des_py1;     //!< isp_pre_file_base_addres + 0x0080
    uint32_t isp_pre_filt_ir_des_py2;     //!< isp_pre_file_base_addres + 0x0084
    uint32_t isp_pre_filt_ir_des_py3;     //!< isp_pre_file_base_addres + 0x0088
    uint32_t isp_pre_filt_ir_des_py4;     //!< isp_pre_file_base_addres + 0x008c
    uint32_t isp_pre_filt_ir_des_py5;     //!< isp_pre_file_base_addres + 0x0090
    uint32_t isp_pre_filt_ir_des_py6;     //!< isp_pre_file_base_addres + 0x0094
    uint32_t isp_pre_filt_ir_des_py7;     //!< isp_pre_file_base_addres + 0x0098
    uint32_t isp_pre_filt_ir_des_py8;     //!< isp_pre_file_base_addres + 0x009c
    uint32_t isp_pre_filt_ir_des_pd1;     //!< isp_pre_file_base_addres + 0x00a0
    uint32_t isp_pre_filt_ir_des_pd2;     //!< isp_pre_file_base_addres + 0x00a4
    uint32_t isp_pre_filt_ir_des_pd3;     //!< isp_pre_file_base_addres + 0x00a8
    uint32_t isp_pre_filt_ir_des_pd4;     //!< isp_pre_file_base_addres + 0x00ac
    uint32_t isp_pre_filt_l_des_px1;     //!< isp_pre_file_base_addres + 0x00b0
    uint32_t _notused_52[(0x000040d0 - 0x000040b4) / 4];
    uint32_t isp_pre_filt_l_des_py1;     //!< isp_pre_file_base_addres + 0x00d0
    uint32_t isp_pre_filt_l_des_py2;     //!< isp_pre_file_base_addres + 0x00d4
    uint32_t isp_pre_filt_l_des_py3;     //!< isp_pre_file_base_addres + 0x00d8
    uint32_t isp_pre_filt_l_des_py4;     //!< isp_pre_file_base_addres + 0x00dc
    uint32_t isp_pre_filt_l_des_py5;     //!< isp_pre_file_base_addres + 0x00e0
    uint32_t isp_pre_filt_l_des_py6;     //!< isp_pre_file_base_addres + 0x00e4
    uint32_t isp_pre_filt_l_des_py7;     //!< isp_pre_file_base_addres + 0x00e8
    uint32_t isp_pre_filt_l_des_py8;     //!< isp_pre_file_base_addres + 0x00ec
    uint32_t isp_pre_filt_l_des_pd1;     //!< isp_pre_file_base_addres + 0x00f0
    uint32_t isp_pre_filt_l_des_pd2;     //!< isp_pre_file_base_addres + 0x00f4
    uint32_t isp_pre_filt_l_des_pd3;     //!< isp_pre_file_base_addres + 0x00f8
    uint32_t isp_pre_filt_l_des_pd4;     //!< isp_pre_file_base_addres + 0x00fc
    uint32_t isp_pre_filt_thresh_bl0;     //!< isp_pre_file_base_addres + 0x0100
    uint32_t isp_pre_filt_thresh_bl1;     //!< isp_pre_file_base_addres + 0x0104
    uint32_t isp_pre_filt_thresh_sh0;     //!< isp_pre_file_base_addres + 0x0108
    uint32_t isp_pre_filt_thresh_sh1;     //!< isp_pre_file_base_addres + 0x010c
    uint32_t isp_pre_filt_lum_weight;     //!< isp_pre_file_base_addres + 0x0110
    uint32_t isp_pre_filt_fac_sh1;     //!< isp_pre_file_base_addres + 0x0114
    uint32_t isp_pre_filt_fac_sh0;     //!< isp_pre_file_base_addres + 0x0118
    uint32_t isp_pre_filt_fac_mid;     //!< isp_pre_file_base_addres + 0x011c
    uint32_t isp_pre_filt_fac_bl0;     //!< isp_pre_file_base_addres + 0x0120
    uint32_t isp_pre_filt_fac_bl1;     //!< isp_pre_file_base_addres + 0x0124
    uint32_t isp_pre_filt_ir_denoise_sw_03;     //!< isp_pre_file_base_addres + 0x0128
    uint32_t isp_pre_filt_ir_denoise_sw_45;     //!< isp_pre_file_base_addres + 0x012c
    uint32_t isp_pre_filt_h_size;     //!< isp_pre_file_base_addres + 0x0130
    uint32_t isp_pre_filt_v_size;     //!< isp_pre_file_base_addres + 0x0134
    uint32_t isp_pre_filt_dmy_hblank;     //!< isp_pre_file_base_addres + 0x0138
    uint32_t isp_pre_filt_ctrl_shd;     //!< isp_pre_file_base_addres + 0x013c

    uint32_t _notused_53[(0x00005100 - 0x00004140) / 4];
    uint32_t isp_wdr4_ctrl ;        //!<isp_wdr4_base_addr + 0x000,
    uint32_t isp_wdr4_shift ;        //!<isp_wdr4_base_addr + 0x004,
    uint32_t isp_wdr4_block_size ;        //!<isp_wdr4_base_addr + 0x008,
    uint32_t isp_wdr4_block_area_factor ;        //!<isp_wdr4_base_addr + 0x00c,
    uint32_t isp_wdr4_value_weight ;        //!<isp_wdr4_base_addr + 0x010,
    uint32_t isp_wdr4_strength_0 ;        //!<isp_wdr4_base_addr + 0x014,
    uint32_t isp_wdr4_strength_1 ;        //!<isp_wdr4_base_addr + 0x018,
    uint32_t isp_wdr4_contrast ;        //!<isp_wdr4_base_addr + 0x01c,
    uint32_t isp_wdr4_pixel_slope ;        //!<isp_wdr4_base_addr + 0x020,
    uint32_t isp_wdr4_entropy_slope ;        //!<isp_wdr4_base_addr + 0x024,
    uint32_t isp_wdr4_sigma_width ;        //!<isp_wdr4_base_addr + 0x028,
    uint32_t isp_wdr4_sigma_height ;        //!<isp_wdr4_base_addr + 0x02c,
    uint32_t isp_wdr4_sigma_value ;        //!<isp_wdr4_base_addr + 0x030,
    uint32_t isp_wdr4_block_flag_width ;        //!<isp_wdr4_base_addr + 0x034,
    uint32_t isp_wdr4_block_flag_height ;        //!<isp_wdr4_base_addr + 0x038,
    uint32_t isp_wdr4_frame_average ;        //!<isp_wdr4_base_addr + 0x03c,
    uint32_t isp_wdr4_frame_std ;        //!<isp_wdr4_base_addr + 0x040,
    uint32_t isp_wdr4_histogram_0 ;        //!<isp_wdr4_base_addr + 0x044,
    uint32_t isp_wdr4_histogram_1 ;        //!<isp_wdr4_base_addr + 0x048,
    uint32_t isp_wdr4_histogram_2 ;        //!<isp_wdr4_base_addr + 0x04c,
    uint32_t isp_wdr4_histogram_3 ;        //!<isp_wdr4_base_addr + 0x050,
    uint32_t isp_wdr4_histogram_4 ;        //!<isp_wdr4_base_addr + 0x054,
    uint32_t isp_wdr4_histogram_5 ;        //!<isp_wdr4_base_addr + 0x058,
    uint32_t isp_wdr4_histogram_6 ;        //!<isp_wdr4_base_addr + 0x05c,
    uint32_t isp_wdr4_histogram_7 ;        //!<isp_wdr4_base_addr + 0x060,
    uint32_t isp_wdr4_histogram_8 ;        //!<isp_wdr4_base_addr + 0x064,
    uint32_t isp_wdr4_histogram_9 ;        //!<isp_wdr4_base_addr + 0x068,
    uint32_t isp_wdr4_histogram_10 ;        //!<isp_wdr4_base_addr + 0x06c,
    uint32_t isp_wdr4_histogram_11 ;        //!<isp_wdr4_base_addr + 0x070,
    uint32_t isp_wdr4_histogram_12 ;        //!<isp_wdr4_base_addr + 0x074,
    uint32_t isp_wdr4_histogram_13 ;        //!<isp_wdr4_base_addr + 0x078,
    uint32_t isp_wdr4_entropy_0 ;        //!<isp_wdr4_base_addr + 0x07c,
    uint32_t isp_wdr4_entropy_1 ;        //!<isp_wdr4_base_addr + 0x080,
    uint32_t isp_wdr4_entropy_2 ;        //!<isp_wdr4_base_addr + 0x084,
    uint32_t isp_wdr4_entropy_3 ;        //!<isp_wdr4_base_addr + 0x088,
    uint32_t isp_wdr4_entropy_4 ;        //!<isp_wdr4_base_addr + 0x08c,
    uint32_t isp_wdr4_entropy_5 ;        //!<isp_wdr4_base_addr + 0x090,
    uint32_t isp_wdr4_entropy_6 ;        //!<isp_wdr4_base_addr + 0x094,
    uint32_t isp_wdr4_gamma_pre_0 ;        //!<isp_wdr4_base_addr + 0x098,
    uint32_t isp_wdr4_gamma_pre_1 ;        //!<isp_wdr4_base_addr + 0x09c,
    uint32_t isp_wdr4_gamma_pre_2 ;        //!<isp_wdr4_base_addr + 0x0a0,
    uint32_t isp_wdr4_gamma_pre_3 ;        //!<isp_wdr4_base_addr + 0x0a4,
    uint32_t isp_wdr4_gamma_pre_4 ;        //!<isp_wdr4_base_addr + 0x0a8,
    uint32_t isp_wdr4_gamma_pre_5 ;        //!<isp_wdr4_base_addr + 0x0ac,
    uint32_t isp_wdr4_gamma_pre_6 ;        //!<isp_wdr4_base_addr + 0x0b0,
    uint32_t isp_wdr4_gamma_pre_7 ;        //!<isp_wdr4_base_addr + 0x0b4,
    uint32_t isp_wdr4_gamma_pre_8 ;        //!<isp_wdr4_base_addr + 0x0b8,
    uint32_t isp_wdr4_gamma_pre_9 ;        //!<isp_wdr4_base_addr + 0x0bc,
    uint32_t isp_wdr4_gamma_pre_10 ;        //!<isp_wdr4_base_addr + 0x0c0,
    uint32_t isp_wdr4_gamma_pre_11 ;        //!<isp_wdr4_base_addr + 0x0c4,
    uint32_t isp_wdr4_gamma_pre_12 ;        //!<isp_wdr4_base_addr + 0x0c8,
    uint32_t isp_wdr4_gamma_pre_13 ;        //!<isp_wdr4_base_addr + 0x0cc,
    uint32_t isp_wdr4_gamma_up_0 ;        //!<isp_wdr4_base_addr + 0x0d0,
    uint32_t isp_wdr4_gamma_up_1 ;        //!<isp_wdr4_base_addr + 0x0d4,
    uint32_t isp_wdr4_gamma_up_2 ;        //!<isp_wdr4_base_addr + 0x0d8,
    uint32_t isp_wdr4_gamma_up_3 ;        //!<isp_wdr4_base_addr + 0x0dc,
    uint32_t isp_wdr4_gamma_up_4 ;        //!<isp_wdr4_base_addr + 0x0e0,
    uint32_t isp_wdr4_gamma_up_5 ;        //!<isp_wdr4_base_addr + 0x0e4,
    uint32_t isp_wdr4_gamma_up_6 ;        //!<isp_wdr4_base_addr + 0x0e8,
    uint32_t isp_wdr4_gamma_up_7 ;        //!<isp_wdr4_base_addr + 0x0ec,
    uint32_t isp_wdr4_gamma_up_8 ;        //!<isp_wdr4_base_addr + 0x0f0,
    uint32_t isp_wdr4_gamma_up_9 ;        //!<isp_wdr4_base_addr + 0x0f4,
    uint32_t isp_wdr4_gamma_up_10 ;        //!<isp_wdr4_base_addr + 0x0f8,
    uint32_t isp_wdr4_gamma_up_11 ;        //!<isp_wdr4_base_addr + 0x0fc,
    uint32_t isp_wdr4_gamma_up_12 ;        //!<isp_wdr4_base_addr + 0x100,
    uint32_t isp_wdr4_gamma_up_13 ;        //!<isp_wdr4_base_addr + 0x104,
    uint32_t isp_wdr4_gamma_down_0 ;        //!<isp_wdr4_base_addr + 0x108,
    uint32_t isp_wdr4_gamma_down_1 ;        //!<isp_wdr4_base_addr + 0x10c,
    uint32_t isp_wdr4_gamma_down_2 ;        //!<isp_wdr4_base_addr + 0x110,
    uint32_t isp_wdr4_gamma_down_3 ;        //!<isp_wdr4_base_addr + 0x114,
    uint32_t isp_wdr4_gamma_down_4 ;        //!<isp_wdr4_base_addr + 0x118,
    uint32_t isp_wdr4_gamma_down_5 ;        //!<isp_wdr4_base_addr + 0x11c,
    uint32_t isp_wdr4_gamma_down_6 ;        //!<isp_wdr4_base_addr + 0x120,
    uint32_t isp_wdr4_distance_weight_0 ;        //!<isp_wdr4_base_addr + 0x124,
    uint32_t isp_wdr4_distance_weight_1 ;        //!<isp_wdr4_base_addr + 0x128,
    uint32_t isp_wdr4_distance_weight_2 ;        //!<isp_wdr4_base_addr + 0x12c,
    uint32_t isp_wdr4_distance_weight_3 ;        //!<isp_wdr4_base_addr + 0x130,
    uint32_t isp_wdr4_distance_weight_4 ;        //!<isp_wdr4_base_addr + 0x134,
    uint32_t isp_wdr4_difference_weight_0 ;        //!<isp_wdr4_base_addr + 0x138,
    uint32_t isp_wdr4_difference_weight_1 ;        //!<isp_wdr4_base_addr + 0x13c,
    uint32_t isp_wdr4_difference_weight_2 ;        //!<isp_wdr4_base_addr + 0x140,
    uint32_t isp_wdr4_difference_weight_3 ;        //!<isp_wdr4_base_addr + 0x144,
    uint32_t isp_wdr4_difference_weight_4 ;        //!<isp_wdr4_base_addr + 0x148,
    uint32_t isp_wdr4_invert_curve_0 ;        //!<isp_wdr4_base_addr + 0x14c,
    uint32_t isp_wdr4_invert_curve_1 ;        //!<isp_wdr4_base_addr + 0x150,
    uint32_t isp_wdr4_invert_curve_2 ;        //!<isp_wdr4_base_addr + 0x154,
    uint32_t isp_wdr4_invert_curve_3 ;        //!<isp_wdr4_base_addr + 0x158,
    uint32_t isp_wdr4_invert_curve_4 ;        //!<isp_wdr4_base_addr + 0x15c,
    uint32_t isp_wdr4_invert_curve_5 ;        //!<isp_wdr4_base_addr + 0x160,
    uint32_t isp_wdr4_invert_curve_6 ;        //!<isp_wdr4_base_addr + 0x164,
    uint32_t isp_wdr4_invert_curve_7 ;        //!<isp_wdr4_base_addr + 0x168,
    uint32_t isp_wdr4_invert_curve_8 ;        //!<isp_wdr4_base_addr + 0x16c,
    uint32_t isp_wdr4_invert_curve_9 ;        //!<isp_wdr4_base_addr + 0x170,
    uint32_t isp_wdr4_invert_linear_0 ;        //!<isp_wdr4_base_addr + 0x174,
    uint32_t isp_wdr4_invert_linear_1 ;        //!<isp_wdr4_base_addr + 0x178,
    uint32_t isp_wdr4_invert_linear_2 ;        //!<isp_wdr4_base_addr + 0x17c,
    uint32_t isp_wdr4_invert_linear_3 ;        //!<isp_wdr4_base_addr + 0x180,
    uint32_t isp_wdr4_invert_linear_4 ;        //!<isp_wdr4_base_addr + 0x184,
    uint32_t isp_wdr4_invert_linear_5 ;        //!<isp_wdr4_base_addr + 0x188,
    uint32_t isp_wdr4_invert_linear_6 ;        //!<isp_wdr4_base_addr + 0x18c,
    uint32_t isp_wdr4_invert_linear_7 ;        //!<isp_wdr4_base_addr + 0x190,
    uint32_t isp_wdr4_invert_linear_8 ;        //!<isp_wdr4_base_addr + 0x194,
    uint32_t isp_wdr4_invert_linear_9 ;        //!<isp_wdr4_base_addr + 0x198,
    uint32_t isp_wdr4_invert_linear_10 ;        //!<isp_wdr4_base_addr + 0x19c,
    uint32_t isp_wdr4_invert_linear_11 ;        //!<isp_wdr4_base_addr + 0x1a0,
    uint32_t isp_wdr4_invert_linear_12 ;        //!<isp_wdr4_base_addr + 0x1a4,
    uint32_t isp_wdr4_invert_linear_13 ;        //!<isp_wdr4_base_addr + 0x1a8,
    uint32_t isp_wdr4_smooth_invert_0 ;        //!<isp_wdr4_base_addr + 0x1ac,
    uint32_t isp_wdr4_smooth_invert_1 ;        //!<isp_wdr4_base_addr + 0x1b0,
    uint32_t isp_wdr4_smooth_invert_2 ;        //!<isp_wdr4_base_addr + 0x1b4,
    uint32_t isp_wdr4_smooth_invert_3 ;        //!<isp_wdr4_base_addr + 0x1b8,
    uint32_t isp_wdr4_smooth_invert_4 ;        //!<isp_wdr4_base_addr + 0x1bc,
    uint32_t isp_wdr4_shift_0 ;        //!<isp_wdr4_base_addr + 0x1c0,
    uint32_t isp_wdr4_shift_1 ;        //!<isp_wdr4_base_addr + 0x1c4,
    uint32_t isp_wdr4_shift_2 ;        //!<isp_wdr4_base_addr + 0x1c8,
    uint32_t isp_wdr4_shift_3 ;        //!<isp_wdr4_base_addr + 0x1cc,
    uint32_t isp_wdr4_shift0_0 ;        //!<isp_wdr4_base_addr + 0x1d0,
    uint32_t isp_wdr4_shift0_1 ;        //!<isp_wdr4_base_addr + 0x1d4,
    uint32_t isp_wdr4_shift0_2 ;        //!<isp_wdr4_base_addr + 0x1d8,
    uint32_t isp_wdr4_strength_0_shd ;        //!<isp_wdr4_base_addr + 0x1dc,
    uint32_t isp_wdr4_strength_1_shd ;        //!<isp_wdr4_base_addr + 0x1e0,
    uint32_t isp_wdr4_contrast_shd ;        //!<isp_wdr4_base_addr + 0x1e4,
    uint32_t isp_wdr4_pixel_slope_shd ;        //!<isp_wdr4_base_addr + 0x1e8,
    uint32_t isp_wdr4_entropy_slope_shd ;        //!<isp_wdr4_base_addr + 0x1ec,

    uint32_t _notused_54[(0x00005300 - 0x000052f0) / 4];
    uint32_t isp_denoise3d2_ctrl;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0000,//0x00005300
    uint32_t isp_denoise3d2_strength;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0004,//0x00005304
    uint32_t isp_denoise3d2_noise;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0008,//0x00005308
    uint32_t isp_denoise3d2_motion;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x000c,//0x0000530c
    uint32_t isp_denoise3d2_range;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0010,//0x00005310
    uint32_t isp_denoise3d2_motion_inv;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0014,//0x00005314
    uint32_t isp_denoise3d2_update;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0018,//0x00005318
    uint32_t isp_denoise3d2_tnr;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x001c,//0x0000531c
    uint32_t isp_denoise3d2_shift;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0020,//0x00005320
    uint32_t isp_denoise3d2_luma;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0024,//0x00005324
    uint32_t isp_denoise3d2_ctrl_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0028,//0x00005328
    uint32_t isp_denoise3d2_strength_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x002c,//0x0000532c
    uint32_t isp_denoise3d2_noise_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0030,//0x00005330
    uint32_t isp_denoise3d2_motion_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0034,//0x00005334
    uint32_t isp_denoise3d2_range_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x00038,//0x00005338
    uint32_t isp_denoise3d2_motion_inv_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x003c,//0x0000533c
    uint32_t isp_denoise3d2_update_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0040,//0x00005340
    uint32_t isp_denoise3d2_tnr_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0044,//0x00005344
    uint32_t isp_denoise3d2_shift_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0048,//0x00005348
    uint32_t isp_denoise3d2_luma_shd;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x004c,//0x0000534c
    uint32_t isp_denoise3d2_bg_val_sum;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0050,//0x00005350
    uint32_t isp_denoise3d2_mo_val_sum;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0054,//0x00005354
    uint32_t isp_denoise3d2_bg_cnt;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0058,//0x00005358
    uint32_t isp_denoise3d2_mo_cnt;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x005c,//0x0000535c
    uint32_t isp_denoise3d2_frame_avg;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0060,//0x00005360
    uint32_t isp_denoise3d2_dummy_hblank;        //!< denoise3d V2  isp_denoise3d2_base_addr+0x0060,//0x00005364
    uint32_t _notused_54_1[(0x00005400 - 0x00005368) / 4];
    uint32_t isp_denoise3d2_pregamma_y_0;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0000,//0x00005400
    uint32_t isp_denoise3d2_pregamma_y_1;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0004,//0x00005404
    uint32_t isp_denoise3d2_pregamma_y_2;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0008,//0x00005408
    uint32_t isp_denoise3d2_pregamma_y_3;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x000c,//0x0000540c
    uint32_t isp_denoise3d2_pregamma_y_4;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0010,//0x00005410
    uint32_t isp_denoise3d2_pregamma_y_5;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0014,//0x00005414
    uint32_t isp_denoise3d2_pregamma_y_6;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0018,//0x00005418
    uint32_t isp_denoise3d2_pregamma_y_7;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x001c,//0x0000541c
    uint32_t isp_denoise3d2_pregamma_y_8;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0020,//0x00005420
    uint32_t isp_denoise3d2_pregamma_y_9;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0024,//0x00005424
    uint32_t isp_denoise3d2_pregamma_y_10;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0028,//0x00005428
    uint32_t isp_denoise3d2_pregamma_y_11;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x002c,//0x0000542c
    uint32_t isp_denoise3d2_pregamma_y_12;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0030,//0x00005430
    uint32_t isp_denoise3d2_pregamma_y_13;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0034,//0x00005434
    uint32_t isp_denoise3d2_pregamma_y_0_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0038,//0x00005438
    uint32_t isp_denoise3d2_pregamma_y_1_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x003c,//0x0000543c
    uint32_t isp_denoise3d2_pregamma_y_2_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0040,//0x00005440
    uint32_t isp_denoise3d2_pregamma_y_3_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0044,//0x00005444
    uint32_t isp_denoise3d2_pregamma_y_4_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0048,//0x00005448
    uint32_t isp_denoise3d2_pregamma_y_5_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x004c,//0x0000544c
    uint32_t isp_denoise3d2_pregamma_y_6_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0050,//0x00005450
    uint32_t isp_denoise3d2_pregamma_y_7_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0054,//0x00005454
    uint32_t isp_denoise3d2_pregamma_y_8_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0058,//0x00005458
    uint32_t isp_denoise3d2_pregamma_y_9_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x005c,//0x0000545c
    uint32_t isp_denoise3d2_pregamma_y_10_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0060,//0x00005460
    uint32_t isp_denoise3d2_pregamma_y_11_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0064,//0x00005464
    uint32_t isp_denoise3d2_pregamma_y_12_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0068,//0x00005468
    uint32_t isp_denoise3d2_pregamma_y_13_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x006c,//0x0000546c
    uint32_t isp_denoise3d2_invgamma_y_0;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0070,//0x00005470
    uint32_t isp_denoise3d2_invgamma_y_1;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0074,//0x00005474
    uint32_t isp_denoise3d2_invgamma_y_2;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0078,//0x00005478
    uint32_t isp_denoise3d2_invgamma_y_3;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x007c,//0x0000547c
    uint32_t isp_denoise3d2_invgamma_y_4;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0080,//0x00005480
    uint32_t isp_denoise3d2_invgamma_y_5;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0084,//0x00005484
    uint32_t isp_denoise3d2_invgamma_y_6;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0088,//0x00005488
    uint32_t isp_denoise3d2_invgamma_y_7;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x008c,//0x0000548c
    uint32_t isp_denoise3d2_invgamma_y_8;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0090,//0x00005490
    uint32_t isp_denoise3d2_invgamma_y_9;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0094,//0x00005494
    uint32_t isp_denoise3d2_invgamma_y_10;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x0098,//0x00005498
    uint32_t isp_denoise3d2_invgamma_y_11;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x009c,//0x0000549c
    uint32_t isp_denoise3d2_invgamma_y_12;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00a0,//0x000054a0
    uint32_t isp_denoise3d2_invgamma_y_13;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00a4,//0x000054a4
    uint32_t isp_denoise3d2_invgamma_y_0_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00a8,//0x000054a8
    uint32_t isp_denoise3d2_invgamma_y_1_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00ac,//0x000054ac
    uint32_t isp_denoise3d2_invgamma_y_2_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00b0,//0x000054b0
    uint32_t isp_denoise3d2_invgamma_y_3_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00b4,//0x000054b4
    uint32_t isp_denoise3d2_invgamma_y_4_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00b8,//0x000054b8
    uint32_t isp_denoise3d2_invgamma_y_5_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00bc,//0x000054bc
    uint32_t isp_denoise3d2_invgamma_y_6_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00c0,//0x000054c0
    uint32_t isp_denoise3d2_invgamma_y_7_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00c4,//0x000054c4
    uint32_t isp_denoise3d2_invgamma_y_8_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00c8,//0x000054c8
    uint32_t isp_denoise3d2_invgamma_y_9_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00cc,//0x000054cc
    uint32_t isp_denoise3d2_invgamma_y_10_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00d0,//0x000054d0
    uint32_t isp_denoise3d2_invgamma_y_11_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00d4,//0x000054d4
    uint32_t isp_denoise3d2_invgamma_y_12_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00d8,//0x000054d8
    uint32_t isp_denoise3d2_invgamma_y_13_shd;        //!< denoise3d V2  isp_denoise3d2_curve_base_addr+0x00dc,//0x000054dc

    uint32_t _notused_55[(0x00005500 - 0x000054e0) / 4];
    uint32_t isp_mi_pp_ctrl;        //!<0x00 isp_mi_pp_base
    uint32_t isp_mi_pp_fmt;        //!<0x04 isp_mi_pp_base
    uint32_t isp_mi_pp_data_swap;        //!<0x08 isp_mi_pp_base
	uint32_t _notused_55_1[(0x00005520 - 0x0000550c) / 4];
    uint32_t isp_mi_pp_y_base_ad_init;        //!<0x20 isp_mi_pp_base
    uint32_t isp_mi_pp_y_size_init;        //!<0x24 isp_mi_pp_base
    uint32_t isp_mi_pp_y_offs_cnt_init;        //!<0x28 isp_mi_pp_base
    uint32_t isp_mi_pp_y_llength;        //!<0x2c isp_mi_pp_base
    uint32_t isp_mi_pp_y_pic_width;        //!<0x30 isp_mi_pp_base
    uint32_t isp_mi_pp_y_pic_height;        //!<0x34 isp_mi_pp_base
    uint32_t isp_mi_pp_y_pic_size;        //!<0x38 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_base_ad_init;        //!<0x3c isp_mi_pp_base
    uint32_t isp_mi_pp_cb_size_init;        //!<0x40 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_offs_cnt_init;        //!<0x44 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_base_ad_init;        //!<0x48 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_size_init;        //!<0x4c isp_mi_pp_base
    uint32_t isp_mi_pp_cr_offs_cnt_init;        //!<0x50 isp_mi_pp_base
    uint32_t isp_mi_pp_y_base_ad_init2;        //!<0x54 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_base_ad_init2;        //!<0x58 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_base_ad_init2;        //!<0x5c isp_mi_pp_base
    uint32_t isp_mi_pp_y_offs_cnt_start;        //!<0x60 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_offs_cnt_start;        //!<0x64 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_offs_cnt_start;        //!<0x68 isp_mi_pp_base
    uint32_t isp_mi_pp_y_base_ad_shd;        //!<0x6c isp_mi_pp_base
    uint32_t isp_mi_pp_y_size_shd;        //!<0x70 isp_mi_pp_base
    uint32_t isp_mi_pp_y_offs_cnt_shd;        //!<0x74 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_base_ad_shd;        //!<0x78 isp_mi_pp_base
    uint32_t isp_mi_pp_cb_size_shd;        //!<0x7c isp_mi_pp_base
    uint32_t isp_mi_pp_cb_offs_cnt_shd;        //!<0x80 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_base_ad_shd;        //!<0x84 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_size_shd;        //!<0x88 isp_mi_pp_base
    uint32_t isp_mi_pp_cr_offs_cnt_shd;        //!<0x8c isp_mi_pp_base
	uint32_t _notused_55_2[(0x00005598 - 0x00005590) / 4];
    uint32_t isp_mi_pp_dma_y_pic_start_ad;        //!<0x98 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_y_pic_width;        //!<0x9c isp_mi_pp_base
    uint32_t isp_mi_pp_dma_y_pic_llength;        //!<0xa0 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_y_pic_size;        //!<0xa4 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_cb_pic_start_ad;        //!<0xa8 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_cr_pic_start_ad;        //!<0xac isp_mi_pp_base
    uint32_t isp_mi_pp_dma_y_pic_start_ad_shd;        //!<0xb0 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_cb_pic_start_ad_shd;        //!<0xb4 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_cr_pic_start_ad_shd;        //!<0xb8 isp_mi_pp_base
    uint32_t isp_mi_pp_dma_y_pic_lval;        //!<0xbc isp_mi_pp_base

	uint32_t mi_pp_dma_y_entry_line_num;
	uint32_t mi_pp_dma_y_buf_line_num;
	uint32_t mi_pp_dma_y_pic_height;
	uint32_t mi_pp_y_lval_bytes;
	uint32_t _notused_56[(0x00005600 - 0x000055d0) / 4];
    uint32_t isp_mi_sp2_raw2_ctrl;        //!<0x00 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_fmt;        //!<0x04 isp_mi_sp2_raw2_base
    uint32_t _notused_56_2[(0x00005620 - 0x00005608) / 4];
    uint32_t isp_mi_sp2_raw2_base_ad_init;        //!<0x20 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_size_init;        //!<0x24 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_offs_cnt_init;        //!<0x28 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_llength;        //!<0x2c isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_pic_width;        //!<0x30 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_pic_height;        //!<0x34 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_pic_size;        //!<0x38 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_offs_cnt_start;        //!<0x3c isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_base_ad_shd;        //!<0x40 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_size_shd;        //!<0x44 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_raw2_offs_cnt_shd;        //!<0x48 isp_mi_sp2_raw2_base
    uint32_t _notused_56_3[(0x00005660 - 0x0000564c) / 4];
    uint32_t isp_mi_sp2_dma_raw2_pic_start_ad;        //!<0x60 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_width;        //!<0x64 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_llength;        //!<0x68 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_size;        //!<0x6c isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_start_ad_shd;        //!<0x70 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_width_shd;        //!<0x74 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_llength_shd;        //!<0x78 isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_size_shd;        //!<0x7c isp_mi_sp2_raw2_base
    uint32_t isp_mi_sp2_dma_raw2_pic_lval;        //!<0x80 isp_mi_sp2_raw2_base

	uint32_t mi_sp2_dma_raw2_pic_lval_shd;
    uint32_t _notused_56_4[(0x00005690 - 0x00005688) / 4];
	uint32_t mi_mp_ycbcr_entry_line_num;
	uint32_t mi_mp_ycbcr_entry_pic_cnt;
	uint32_t mi_mp_ycbcr_entry_y_cnt;
	uint32_t mi_mp_ycbcr_entry_cb_cnt;
	uint32_t mi_mp_ycbcr_entry_cr_cnt;
	uint32_t mi_mp_raw_entry_line_num;
	uint32_t mi_mp_raw_entry_pic_cnt;
	uint32_t mi_sp1_ppw_ycbcr_entry_line_num;
	uint32_t mi_sp1_ppw_ycbcr_entry_pic_cnt;
	uint32_t mi_mcm_raw0_entry_line_num;
	uint32_t mi_mcm_raw0_entry_pic_cnt;
    uint32_t _notused_56_5[(0x000056d0 - 0x000056bc) / 4];
	uint32_t miv2_imsc3;
	uint32_t miv2_isr3;
	uint32_t miv2_mis3;
	uint32_t miv2_icr3;
	uint32_t miv2_ris3;

    uint32_t _notused_57[(0x00005700 - 0x000056e4) / 4];
    uint32_t isp_mi_hdr_ctrl;        //!<0x00 isp_mi_hdr_base
    uint32_t isp_mi_hdr_fmt;        //!<0x04 isp_mi_hdr_base
    uint32_t isp_mi_hdr_dma_start_by_lines;        //!<0x08 isp_mi_hdr_base
    uint32_t isp_mi_hdr_ret_bus_cfg;        //!<0x0c isp_mi_hdr_base
    uint32_t isp_mi_hdr_ret_bus_id;        //!<0x10 isp_mi_hdr_base
    uint32_t isp_mi_hdr_ret_bus_timeo;        //!<0x14 isp_mi_hdr_base
    uint32_t _notused_57_2[(0x00005720 - 0x00005718) / 4];
    uint32_t isp_mi_hdr_pic_width;        //!<0x20 isp_mi_hdr_base
    uint32_t isp_mi_hdr_pic_height;        //!<0x24 isp_mi_hdr_base
    uint32_t _notused_57_3[(0x00005740 - 0x00005728) / 4];
    uint32_t isp_mi_hdr_l_base_ad_init;        //!<0x40 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_size_init;        //!<0x44 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_offs_cnt_init;        //!<0x48 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_llength;        //!<0x4c isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_pic_lval;        //!<0x50 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_irq_offs_init;        //!<0x54 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_offs_cnt_start;        //!<0x58 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_base_ad_shd;        //!<0x5c isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_size_shd;        //!<0x60 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_offs_cnt_shd;        //!<0x64 isp_mi_hdr_base
    uint32_t isp_mi_hdr_l_irq_offs_shd;        //!<0x68 isp_mi_hdr_base
    uint32_t _notused_57_4[(0x00005780 - 0x0000576c) / 4];
    uint32_t isp_mi_hdr_s_base_ad_init;        //!<0x80 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_size_init;        //!<0x84 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_offs_cnt_init;        //!<0x88 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_llength;        //!<0x8c isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_pic_lval;        //!<0x90 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_irq_offs_init;        //!<0x94 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_offs_cnt_start;        //!<0x98 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_base_ad_shd;        //!<0x9c isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_size_shd;        //!<0xa0 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_offs_cnt_shd;        //!<0xa4 isp_mi_hdr_base
    uint32_t isp_mi_hdr_s_irq_offs_shd;        //!<0xa8 isp_mi_hdr_base
    uint32_t _notused_57_5[(0x000057c0 - 0x000057ac) / 4];
    uint32_t isp_mi_hdr_vs_base_ad_init;        //!<0xc0 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_size_init;        //!<0xc4 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_offs_cnt_init;        //!<0xc8 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_llength;        //!<0xcc isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_pic_lval;        //!<0xd0 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_irq_offs_init;        //!<0xd4 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_offs_cnt_start;        //!<0xd8 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_base_ad_shd;        //!<0xdc isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_size_shd;        //!<0xe0 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_offs_cnt_shd;        //!<0xe4 isp_mi_hdr_base
    uint32_t isp_mi_hdr_vs_irq_offs_shd;        //!<0xe8 isp_mi_hdr_base
    uint32_t _notused_58[(0x00005800 - 0x000057ec) / 4];
    uint32_t isp_mi_hdr_dma_pic_width;        //!<0x00 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_pic_height;        //!<0x04 isp_mi_hdr_dma_base
	uint32_t _notused_58_1[(0x00005820 - 0x00005808) / 4];
    uint32_t isp_mi_hdr_dma_l_base_ad_init;        //!<0x20 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_l_size_init;        //!<0x24 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_l_llength;        //!<0x28 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_l_lval;        //!<0x2c isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_l_base_ad_shd;        //!<0x30 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_l_size_shd;        //!<0x34 isp_mi_hdr_dma_base
	uint32_t _notused_58_2[(0x00005850 - 0x00005838) / 4];
    uint32_t isp_mi_hdr_dma_s_base_ad_init;        //!<0x50 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_s_size_init;        //!<0x54 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_s_llength;        //!<0x58 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_s_lval;        //!<0x5c isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_s_base_ad_shd;        //!<0x60 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_s_size_shd;        //!<0x64 isp_mi_hdr_dma_base
	uint32_t _notused_58_3[(0x00005880 - 0x00005868) / 4];
    uint32_t isp_mi_hdr_dma_vs_base_ad_init;        //!<0x80 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_vs_size_init;        //!<0x84 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_vs_llength;        //!<0x88 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_vs_lval;        //!<0x8c isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_vs_base_ad_shd;        //!<0x90 isp_mi_hdr_dma_base
    uint32_t isp_mi_hdr_dma_vs_size_shd;        //!<0x94 isp_mi_hdr_dma_base
	uint32_t _notused_58_4[(0x00005900 - 0x00005898) / 4];
    uint32_t isp_hdr_ret_ctrl;        //!<0x00 isp_hdr_ret_base
    uint32_t isp_hdr_interval;        //!<0x04 isp_hdr_ret_base
    uint32_t isp_hdr_ret_h_blank;        //!<0x08 isp_hdr_ret_h_blank
    uint32_t isp_hdr_ret_v_blank;        //!<0x0c isp_hdr_ret_v_blank
    uint32_t isp_hdr_ret_h_size;        //!<0x010 isp_hdr_ret_h_size
    uint32_t isp_hdr_ret_v_size;        //!<0x014 isp_hdr_ret_v_size
} MrvAllRegister_t;

/* - MASK AND SHIFT MARCOS ----------------------------------------------------------*/

/*! Register: vi_ccl: Clock control register (0x00000000)*/
/*! Slice: vi_ccl_dis:*/
/*! Clock Control Logic disable */
/* 0: processing/cfg-clocks for all marvin sub modules enabled */
/* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */
#define MRV_VI_CCL_DIS
#define MRV_VI_CCL_DIS_MASK 0x00000004U
#define MRV_VI_CCL_DIS_SHIFT 2U
/*! Slice: vi_ccl_dis_status:*/
/*! Status of vi_ccl[2] bit (copy of vi_ccl[2])*/
#define MRV_VI_CCL_DIS_STATUS
#define MRV_VI_CCL_DIS_STATUS_MASK 0x00000002U
#define MRV_VI_CCL_DIS_STATUS_SHIFT 1U

/*! Register: vi_id: Revision identification register (0x00000008)*/
/*! Slice: rev_id:*/
/*! MARVIN5 revision IDs:*/
/* M5_v1 id =  0x0015'3010  release 1.0 */
/* M5_v1 id =  0x1015'3010  release 1.1 */
/* M5_v2 id =  0x0025'3010 */
/* M5_v2 id =  0x0075'3010  release 2.0 (full feature set)*/
/* M5_v3 id =  0x0035'3010 */
/* M5_v3 id =  0x2035'3010  with bug fixes in MIPI, MI, LSC */
/* M5_v4 id =  0x0045'3010 */
/* M5_v4 id =  0x1045'3010  with bug fixes in MIPI, MI, LSC */
/* M5_v6 id =  0x0055'3010 */
/* M5_v7 id =  0x0065'3010 */
/* M12_v1 id (Rel. 1.0) = 0x0015'3017 */
/* M12_v1 id (Rel. 1.2) = 0x1015'3017 */
/* M12_v1 id (Rel. 2.0) = 0x2015'3017 */
/* M12_v1 id (Rel. 2.1) = 0x3015'3017 */
/* M12_v2 id = 0x0025'3017 */
/* M12_v3 id (Rel. 1.0) = 0x0065'3017 */
/* M12_v3 id (Rel. 1.1) = 0x1065'3017 */
/* M14_v1 id (Rel. 1.0) = 0x0075'3017 */
/* M14_v1 id (Rel. 1.1) = 0x1075'3017 */
/* M14_v2 id (Rel. 1.0) = 0x0085'3017 */
/* M18_v1 id = 0x0035'3017 (MarvinBase)*/
/* M20_v1 id (Rel. 1.0) = 0x0055'3017 */
/* M20_v1 id (Rel. 1.1) = 0x1055'3017 */
/* M20_v1 id (Rel. 1.2) = 0x2055'3017 */
/* M20_v2 id (Rel. 1.0) = 0x0095'3017 */
/* M64_v1 id = 0x0045'3017 */
#define MRV_REV_ID
#define MRV_REV_ID_MASK 0xFFFFFFFFU
#define MRV_REV_ID_SHIFT 0U

/*! Register: vi_iccl: Internal clock  control register (0x00000010)*/
/*! Slice: vi_mipi_clk_enable:*/
/*! MIPI interface clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_MIPI_CLK_ENABLE
#define MRV_VI_MIPI_CLK_ENABLE_MASK 0x00000800U
#define MRV_VI_MIPI_CLK_ENABLE_SHIFT 11U
/*! Slice: vi_smia_clk_enable:*/
/*! SMIA interface clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_SMIA_CLK_ENABLE
#define MRV_VI_SMIA_CLK_ENABLE_MASK 0x00000400U
#define MRV_VI_SMIA_CLK_ENABLE_SHIFT 10U
/*! Slice: vi_simp_clk_enable:*/
/*! Superimpose clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_SIMP_CLK_ENABLE
#define MRV_VI_SIMP_CLK_ENABLE_MASK 0x00000200U
#define MRV_VI_SIMP_CLK_ENABLE_SHIFT 9U
/*! Slice: vi_ie_clk_enable:*/
/*! Image effect clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_IE_CLK_ENABLE
#define MRV_VI_IE_CLK_ENABLE_MASK 0x00000100U
#define MRV_VI_IE_CLK_ENABLE_SHIFT 8U
/*! Slice: vi_mi_clk_enable:*/
/*! memory interface clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_MI_CLK_ENABLE
#define MRV_VI_MI_CLK_ENABLE_MASK 0x00000040U
#define MRV_VI_MI_CLK_ENABLE_SHIFT 6U
/*! Slice: vi_jpeg_clk_enable:*/
/*! JPEG encoder clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_JPEG_CLK_ENABLE
#define MRV_VI_JPEG_CLK_ENABLE_MASK 0x00000020U
#define MRV_VI_JPEG_CLK_ENABLE_SHIFT 5U
/*! Slice: vi_srsz_clk_enable:*/
/*! self picture resize clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_SRSZ_CLK_ENABLE
#define MRV_VI_SRSZ_CLK_ENABLE_MASK 0x00000010U
#define MRV_VI_SRSZ_CLK_ENABLE_SHIFT 4U
/*! Slice: vi_mrsz_clk_enable:*/
/*! main picture resize clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_MRSZ_CLK_ENABLE
#define MRV_VI_MRSZ_CLK_ENABLE_MASK 0x00000008U
#define MRV_VI_MRSZ_CLK_ENABLE_SHIFT 3U
/*! Slice: vi_cp_clk_enable:*/
/*! color processing clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_CP_CLK_ENABLE
#define MRV_VI_CP_CLK_ENABLE_MASK 0x00000002U
#define MRV_VI_CP_CLK_ENABLE_SHIFT 1U
/*! Slice: vi_isp_clk_enable:*/
/*! isp processing clock enable */
/* 1: processing mode */
/* 0: power safe */
#define MRV_VI_ISP_CLK_ENABLE
#define MRV_VI_ISP_CLK_ENABLE_MASK 0x00000001U
#define MRV_VI_ISP_CLK_ENABLE_SHIFT 0U

/*! Register: vi_ircl: Internal reset control register (0x00000014)*/
/*! Slice: vi_mipi_soft_rst:*/
/*! MIPI Interface software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_MIPI_SOFT_RST
#define MRV_VI_MIPI_SOFT_RST_MASK 0x00000800U
#define MRV_VI_MIPI_SOFT_RST_SHIFT 11U
/*! Slice: vi_smia_soft_rst:*/
/*! SMIA Interface software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_SMIA_SOFT_RST
#define MRV_VI_SMIA_SOFT_RST_MASK 0x00000400U
#define MRV_VI_SMIA_SOFT_RST_SHIFT 10U
/*! Slice: vi_simp_soft_rst:*/
/*! Superimpose software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_SIMP_SOFT_RST
#define MRV_VI_SIMP_SOFT_RST_MASK 0x00000200U
#define MRV_VI_SIMP_SOFT_RST_SHIFT 9U
/*! Slice: vi_ie_soft_rst:*/
/*! Image effect software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_IE_SOFT_RST
#define MRV_VI_IE_SOFT_RST_MASK 0x00000100U
#define MRV_VI_IE_SOFT_RST_SHIFT 8U
/*! Slice: vi_marvin_rst:*/
/*! hardware reset of entire marvin */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_MARVIN_RST
#define MRV_VI_MARVIN_RST_MASK 0x00000080U
#define MRV_VI_MARVIN_RST_SHIFT 7U
/*! Slice: vi_mi_soft_rst:*/
/*! memory interface software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_MI_SOFT_RST
#define MRV_VI_MI_SOFT_RST_MASK 0x00000040U
#define MRV_VI_MI_SOFT_RST_SHIFT 6U
/*! Slice: vi_jpeg_soft_rst:*/
/*! JPEG encoder software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_JPEG_SOFT_RST
#define MRV_VI_JPEG_SOFT_RST_MASK 0x00000020U
#define MRV_VI_JPEG_SOFT_RST_SHIFT 5U
/*! Slice: vi_srsz_soft_rst:*/
/*! Self-picture resize software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_SRSZ_SOFT_RST
#define MRV_VI_SRSZ_SOFT_RST_MASK 0x00000010U
#define MRV_VI_SRSZ_SOFT_RST_SHIFT 4U
/*! Slice: vi_mrsz_soft_rst:*/
/*! Main-picture resize software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_MRSZ_SOFT_RST
#define MRV_VI_MRSZ_SOFT_RST_MASK 0x00000008U
#define MRV_VI_MRSZ_SOFT_RST_SHIFT 3U
/*! Slice: vi_ycs_soft_rst:*/
/*! y/c splitter software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_YCS_SOFT_RST
#define MRV_VI_YCS_SOFT_RST_MASK 0x00000004U
#define MRV_VI_YCS_SOFT_RST_SHIFT 2U
/*! Slice: vi_cp_soft_rst:*/
/*! color processing software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_CP_SOFT_RST
#define MRV_VI_CP_SOFT_RST_MASK 0x00000002U
#define MRV_VI_CP_SOFT_RST_SHIFT 1U
/*! Slice: vi_isp_soft_rst:*/
/*! isp software reset */
/* 0: processing mode */
/* 1: reset state */
#define MRV_VI_ISP_SOFT_RST
#define MRV_VI_ISP_SOFT_RST_MASK 0x00000001U
#define MRV_VI_ISP_SOFT_RST_SHIFT 0U

/*! Register: vi_dpcl: Data path control register (0x00000018)*/
/*! Slice: vi_dma_spmux:*/
/*! 0: data from camera interface to self resize */
/* 1: data from DMA read port to self resize */
#define MRV_VI_DMA_SPMUX
#define MRV_VI_DMA_SPMUX_MASK 0x00000800U
#define MRV_VI_DMA_SPMUX_SHIFT 11U
/*! Slice: vi_dma_iemux:*/
/*! 0: data from camera interface to image effects */
/* 1: data from DMA read port to image effects */
#define MRV_VI_DMA_IEMUX
#define MRV_VI_DMA_IEMUX_MASK 0x00000400U
#define MRV_VI_DMA_IEMUX_SHIFT 10U
/*! Slice: if_select:*/
/*! selects input interface */
/* 0: parallel interface */
/* 1: SMIA-interface */
/* 2: MIPI-interface */
/* 3: HDR-interface */
#define MRV_IF_SELECT
#define MRV_IF_SELECT_MASK 0x00000300U
#define MRV_IF_SELECT_SHIFT 8U
/*! Slice: vi_dma_switch:*/
/*! DMA read data path selector */
/* 0: path to SPMUX */
/* 1: path to Superimpose */
/* 2: path to Image Effects */
/* 3: path to JPEG encoder */
/* 4: path to ISP Bayer RGB */
/* 5..7: reserved */
#define MRV_VI_DMA_SWITCH
#define MRV_VI_DMA_SWITCH_MASK 0x00000070U
#define MRV_VI_DMA_SWITCH_SHIFT 4U
/*! Slice: vi_chan_mode:*/
/*! Y/C splitter channel mode */
/* 0: disabled */
/* 1: main path and raw data mode */
/* 2: self path mode */
/* 3: main and self path mode */
#define MRV_VI_CHAN_MODE
#ifdef ISPVI_EXPAND_CHAN
#define MRV_VI_CHAN_MODE_MASK 0x00007000U
#define MRV_VI_CHAN_MODE_SHIFT 12U
#else
#define MRV_VI_CHAN_MODE_MASK 0x0000000CU
#define MRV_VI_CHAN_MODE_SHIFT 2U
#endif
/*! Slice: vi_mp_mux:*/
/*! data path selector for main path */
/* 00: data from DMA read port to JPEG encoder */
/* 01: data from main resize to MI, uncompressed */
/* 10: data from main resize to JPEG encoder */
/* 11: reserved */
#define MRV_VI_MP_MUX
#define MRV_VI_MP_MUX_MASK 0x00000003U
#define MRV_VI_MP_MUX_SHIFT 0U

#define MRV_VI_DPCL_STRM_MUX
#define MRV_VI_DPCL_STRM_MUX_MASK 0x00040000U
#define MRV_VI_DPCL_STRM_MUX_SHIFT 18U

/*! Register: img_eff_ctrl: Global control register (0x00000000)*/
/*! Slice: full_range:*/
/*! '0': pixel value range according to BT.601 */
/* '1': YCbCr full range 0...255 */
#define MRV_IMGEFF_FULL_RANGE
#define MRV_IMGEFF_FULL_RANGE_MASK 0x00000020U
#define MRV_IMGEFF_FULL_RANGE_SHIFT 5U
/*! Slice: cfg_upd:*/
/*! write '0': nothing happens */
/* write '1': update shadow registers */
/* read: always '0'*/
#define MRV_IMGEFF_CFG_UPD
#define MRV_IMGEFF_CFG_UPD_MASK 0x00000010U
#define MRV_IMGEFF_CFG_UPD_SHIFT 4U
/*! Slice: effect_mode:*/
/*! effect mode */
/* 000: black & white effect (grayscale)*/
/* 001: negative */
/* 010: sepia effect */
/* 011: color selection effect */
/* 100: emboss effect */
/* 101: sketch effect */
/* 110: sharpen effect */
/* 111: reserved */
#define MRV_IMGEFF_EFFECT_MODE
#define MRV_IMGEFF_EFFECT_MODE_MASK 0x0000000EU
#define MRV_IMGEFF_EFFECT_MODE_SHIFT 1U
/*! Slice: bypass_mode:*/
/*! bypass mode */
/* 1: processing is activated */
/* 0: processing is deactivated, bypass mode is selected */
#define MRV_IMGEFF_BYPASS_MODE
#define MRV_IMGEFF_BYPASS_MODE_MASK 0x00000001U
#define MRV_IMGEFF_BYPASS_MODE_SHIFT 0U

/*! Register: img_eff_color_sel: Color selection register (for color selection effect) (0x00000004)*/
/*! Slice: color_threshold:*/
/*! Threshold value of the RGB colors for the color selection effect.*/
#define MRV_IMGEFF_COLOR_THRESHOLD
#define MRV_IMGEFF_COLOR_THRESHOLD_MASK 0x0000FF00U
#define MRV_IMGEFF_COLOR_THRESHOLD_SHIFT 8U
/*! Slice: color_selection:*/
/*! Defining the maintained color:*/
/* 000: red green and blue */
/* 001: blue */
/* 010: green */
/* 011: green and blue */
/* 100: red */
/* 101: red and blue */
/* 110: red and green */
/* 111: red green and blue */
#define MRV_IMGEFF_COLOR_SELECTION
#define MRV_IMGEFF_COLOR_SELECTION_MASK 0x00000007U
#define MRV_IMGEFF_COLOR_SELECTION_SHIFT 0U

/*! Register: img_eff_mat_1: 3x3 matrix coefficients for emboss effect (1) (0x00000008)*/
/*! Slice: emb_coef_21_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_21_EN
#define MRV_IMGEFF_EMB_COEF_21_EN_MASK 0x00008000U
#define MRV_IMGEFF_EMB_COEF_21_EN_SHIFT 15U
/*! Slice: emb_coef_21:*/
/*! second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_21
#define MRV_IMGEFF_EMB_COEF_21_MASK 0x00007000U
#define MRV_IMGEFF_EMB_COEF_21_SHIFT 12U
/*! Slice: emb_coef_13_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_13_EN
#define MRV_IMGEFF_EMB_COEF_13_EN_MASK 0x00000800U
#define MRV_IMGEFF_EMB_COEF_13_EN_SHIFT 11U
/*! Slice: emb_coef_13:*/
/*! first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_13
#define MRV_IMGEFF_EMB_COEF_13_MASK 0x00000700U
#define MRV_IMGEFF_EMB_COEF_13_SHIFT 8U
/*! Slice: emb_coef_12_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_12_EN
#define MRV_IMGEFF_EMB_COEF_12_EN_MASK 0x00000080U
#define MRV_IMGEFF_EMB_COEF_12_EN_SHIFT 7U
/*! Slice: emb_coef_12:*/
/*! first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_12
#define MRV_IMGEFF_EMB_COEF_12_MASK 0x00000070U
#define MRV_IMGEFF_EMB_COEF_12_SHIFT 4U
/*! Slice: emb_coef_11_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_11_EN
#define MRV_IMGEFF_EMB_COEF_11_EN_MASK 0x00000008U
#define MRV_IMGEFF_EMB_COEF_11_EN_SHIFT 3U
/*! Slice: emb_coef_11:*/
/*! first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_11
#define MRV_IMGEFF_EMB_COEF_11_MASK 0x00000007U
#define MRV_IMGEFF_EMB_COEF_11_SHIFT 0U

/*! Register: img_eff_mat_2: 3x3 matrix coefficients for emboss effect (2) (0x0000000c)*/
/*! Slice: emb_coef_32_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_32_EN
#define MRV_IMGEFF_EMB_COEF_32_EN_MASK 0x00008000U
#define MRV_IMGEFF_EMB_COEF_32_EN_SHIFT 15U
/*! Slice: emb_coef_32:*/
/*! third line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_32
#define MRV_IMGEFF_EMB_COEF_32_MASK 0x00007000U
#define MRV_IMGEFF_EMB_COEF_32_SHIFT 12U
/*! Slice: emb_coef_31_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_31_EN
#define MRV_IMGEFF_EMB_COEF_31_EN_MASK 0x00000800U
#define MRV_IMGEFF_EMB_COEF_31_EN_SHIFT 11U
/*! Slice: emb_coef_31:*/
/*! third line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_31
#define MRV_IMGEFF_EMB_COEF_31_MASK 0x00000700U
#define MRV_IMGEFF_EMB_COEF_31_SHIFT 8U
/*! Slice: emb_coef_23_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_23_EN
#define MRV_IMGEFF_EMB_COEF_23_EN_MASK 0x00000080U
#define MRV_IMGEFF_EMB_COEF_23_EN_SHIFT 7U
/*! Slice: emb_coef_23:*/
/*! second line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_23
#define MRV_IMGEFF_EMB_COEF_23_MASK 0x00000070U
#define MRV_IMGEFF_EMB_COEF_23_SHIFT 4U
/*! Slice: emb_coef_22_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_22_EN
#define MRV_IMGEFF_EMB_COEF_22_EN_MASK 0x00000008U
#define MRV_IMGEFF_EMB_COEF_22_EN_SHIFT 3U
/*! Slice: emb_coef_22:*/
/*! second line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_22
#define MRV_IMGEFF_EMB_COEF_22_MASK 0x00000007U
#define MRV_IMGEFF_EMB_COEF_22_SHIFT 0U

/*! Register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (0x00000010)*/
/*! Slice: sket_coef_13_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_13_EN
#define MRV_IMGEFF_SKET_COEF_13_EN_MASK 0x00008000U
#define MRV_IMGEFF_SKET_COEF_13_EN_SHIFT 15U
/*! Slice: sket_coef_13:*/
/*! first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_13
#define MRV_IMGEFF_SKET_COEF_13_MASK 0x00007000U
#define MRV_IMGEFF_SKET_COEF_13_SHIFT 12U
/*! Slice: sket_coef_12_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_12_EN
#define MRV_IMGEFF_SKET_COEF_12_EN_MASK 0x00000800U
#define MRV_IMGEFF_SKET_COEF_12_EN_SHIFT 11U
/*! Slice: sket_coef_12:*/
/*! first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_12
#define MRV_IMGEFF_SKET_COEF_12_MASK 0x00000700U
#define MRV_IMGEFF_SKET_COEF_12_SHIFT 8U
/*! Slice: sket_coef_11_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_11_EN
#define MRV_IMGEFF_SKET_COEF_11_EN_MASK 0x00000080U
#define MRV_IMGEFF_SKET_COEF_11_EN_SHIFT 7U
/*! Slice: sket_coef_11:*/
/*! first line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_11
#define MRV_IMGEFF_SKET_COEF_11_MASK 0x00000070U
#define MRV_IMGEFF_SKET_COEF_11_SHIFT 4U
/*! Slice: emb_coef_33_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_EMB_COEF_33_EN
#define MRV_IMGEFF_EMB_COEF_33_EN_MASK 0x00000008U
#define MRV_IMGEFF_EMB_COEF_33_EN_SHIFT 3U
/*! Slice: emb_coef_33:*/
/*! third line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_EMB_COEF_33
#define MRV_IMGEFF_EMB_COEF_33_MASK 0x00000007U
#define MRV_IMGEFF_EMB_COEF_33_SHIFT 0U

/*! Register: img_eff_mat_4: 3x3 matrix coefficients for sketch/sharpen effect (2) (0x00000014)*/
/*! Slice: sket_coef_31_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_31_EN
#define MRV_IMGEFF_SKET_COEF_31_EN_MASK 0x00008000U
#define MRV_IMGEFF_SKET_COEF_31_EN_SHIFT 15U
/*! Slice: sket_coef_31:*/
/*! third line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_31
#define MRV_IMGEFF_SKET_COEF_31_MASK 0x00007000U
#define MRV_IMGEFF_SKET_COEF_31_SHIFT 12U
/*! Slice: sket_coef_23_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_23_EN
#define MRV_IMGEFF_SKET_COEF_23_EN_MASK 0x00000800U
#define MRV_IMGEFF_SKET_COEF_23_EN_SHIFT 11U
/*! Slice: sket_coef_23:*/
/*! second line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_23
#define MRV_IMGEFF_SKET_COEF_23_MASK 0x00000700U
#define MRV_IMGEFF_SKET_COEF_23_SHIFT 8U
/*! Slice: sket_coef_22_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_22_EN
#define MRV_IMGEFF_SKET_COEF_22_EN_MASK 0x00000080U
#define MRV_IMGEFF_SKET_COEF_22_EN_SHIFT 7U
/*! Slice: sket_coef_22:*/
/*! second line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_22
#define MRV_IMGEFF_SKET_COEF_22_MASK 0x00000070U
#define MRV_IMGEFF_SKET_COEF_22_SHIFT 4U
/*! Slice: sket_coef_21_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_21_EN
#define MRV_IMGEFF_SKET_COEF_21_EN_MASK 0x00000008U
#define MRV_IMGEFF_SKET_COEF_21_EN_SHIFT 3U
/*! Slice: sket_coef_21:*/
/*! second line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_21
#define MRV_IMGEFF_SKET_COEF_21_MASK 0x00000007U
#define MRV_IMGEFF_SKET_COEF_21_SHIFT 0U

/*! Register: img_eff_mat_5: 3x3 matrix coefficients for sketch/sharpen effect (3) (0x00000018)*/
/*! Slice: sket_coef_33_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_33_EN
#define MRV_IMGEFF_SKET_COEF_33_EN_MASK 0x00000080U
#define MRV_IMGEFF_SKET_COEF_33_EN_SHIFT 7U
/*! Slice: sket_coef_33:*/
/*! third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_33
#define MRV_IMGEFF_SKET_COEF_33_MASK 0x00000070U
#define MRV_IMGEFF_SKET_COEF_33_SHIFT 4U
/*! Slice: sket_coef_32_en:*/
/*! 0: entry not used (coefficient is zero)*/
/* 1: entry used */
#define MRV_IMGEFF_SKET_COEF_32_EN
#define MRV_IMGEFF_SKET_COEF_32_EN_MASK 0x00000008U
#define MRV_IMGEFF_SKET_COEF_32_EN_SHIFT 3U
/*! Slice: sket_coef_32:*/
/*! third line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
#define MRV_IMGEFF_SKET_COEF_32
#define MRV_IMGEFF_SKET_COEF_32_MASK 0x00000007U
#define MRV_IMGEFF_SKET_COEF_32_SHIFT 0U

/*! Register: img_eff_tint: Chrominance increment values of a tint (used for sepia effect) (0x0000001c)*/
/*! Slice: incr_cr:*/
/*! Cr increment value of a tint. 7 bits for value, 1 sign bit.*/
/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
#define MRV_IMGEFF_INCR_CR
#define MRV_IMGEFF_INCR_CR_MASK 0x0000FF00U
#define MRV_IMGEFF_INCR_CR_SHIFT 8U
/*! Slice: incr_cb:*/
/*! Cb increment value of a tint. 7 bits for value, 1 sign bit.*/
/* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
#define MRV_IMGEFF_INCR_CB
#define MRV_IMGEFF_INCR_CB_MASK 0x000000FFU
#define MRV_IMGEFF_INCR_CB_SHIFT 0U

/*! Register: img_eff_ctrl_shd: Shadow register for control register (0x00000020)*/
/*! Slice: effect_mode_shd:*/
/*! effect mode */
/* 000: black & white effect (grayscale)*/
/* 001: negative */
/* 010: sepia effect */
/* 011: color selection effect */
/* 100: emboss effect */
/* 101: sketch effect */
/* 110: sharpen effect */
/* 111: reserved */
#define MRV_IMGEFF_EFFECT_MODE_SHD
#define MRV_IMGEFF_EFFECT_MODE_SHD_MASK 0x0000000EU
#define MRV_IMGEFF_EFFECT_MODE_SHD_SHIFT 1U

/*! Register: img_eff_sharpen: Factor and threshold for sharpen effect (0x00000024)*/
/*! Slice: sharp_factor:*/
/*! 6Bit Factor for sharpening function. Value range is from 0x0 to 0x3F. High value means strong sharpening. The resulting factors are for example:*/
/* 0x00 =	0 (no sharpen effect like bypass)*/
/* 0x01 =	0.25 */
/* 0x02 =	0.5 */
/* 0x03 =	0.75 */
/* 0x04 =	1.0 */
/* 0x05 =	1.25 */
/* 0x06 =	1.5 */
/* 0x08 =	2.0 */
/* 0x0A =	2.5 */
/* 0x0C =	3.0 */
/* 0x10 =	4.0 */
/* 0x18 =	6.0 */
/* 0x20 =	8.0 */
/* 0x30 =	12.0 */
/* 0x3F =	15.75 */
#define MRV_IMGEFF_SHARP_FACTOR
#define MRV_IMGEFF_SHARP_FACTOR_MASK 0x00003F00U
#define MRV_IMGEFF_SHARP_FACTOR_SHIFT 8U
/*! Slice: coring_thr:*/
/*! Threshold for coring function. This value is used to avoid amplifying noise too much by suppressing sharpening for small gradients. Higher value means less sharpening for smooth edges.  Threshold zero means no coring, so all gradients are treated the same. Threshold 255 means nearly no sharpening. An absolute value for the highpass signal is defined here. The highpass signal is truncated at the defined level.*/
#define MRV_IMGEFF_CORING_THR
#define MRV_IMGEFF_CORING_THR_MASK 0x000000FFU
#define MRV_IMGEFF_CORING_THR_SHIFT 0U

/*! Register: super_imp_ctrl: Global control register (0x00000000)*/
/*! Slice: transparency_mode:*/
/*! transparency mode */
/* 1: transparency mode disabled */
/* 0: transparency mode enabled */
#define MRV_SI_TRANSPARENCY_MODE
#define MRV_SI_TRANSPARENCY_MODE_MASK 0x00000004U
#define MRV_SI_TRANSPARENCY_MODE_SHIFT 2U
/*! Slice: ref_image:*/
/*! define the reference image */
/* 1: superimpose bitmap from main memory */
/* 0: image from the Image Effect module */
/* Note: the reference image defines the size of the output image */
#define MRV_SI_REF_IMAGE
#define MRV_SI_REF_IMAGE_MASK 0x00000002U
#define MRV_SI_REF_IMAGE_SHIFT 1U
/*! Slice: bypass_mode:*/
/*! Bypass mode */
/* 0: bypass mode */
/* 1: normal operation */
/* Note: in the bypass mode the data stream from Image Effect is transmitted to MUX module without overlaying */
#define MRV_SI_BYPASS_MODE
#define MRV_SI_BYPASS_MODE_MASK 0x00000001U
#define MRV_SI_BYPASS_MODE_SHIFT 0U

/*! Register: super_imp_offset_x: Offset x register (0x00000004)*/
/*! Slice: offset_x:*/
/*! Offset X */
/* Note: the bit 0 is dont care (write 1 doesnt have any effect, the read access always gives 0)*/
/* Note: the offset_x is positive and refers to the reference image */
#define MRV_SI_OFFSET_X
#define MRV_SI_OFFSET_X_MASK 0x00003FFEU
#define MRV_SI_OFFSET_X_SHIFT 1U

/*! Register: super_imp_offset_y: Offset y register (0x00000008)*/
/*! Slice: offset_y:*/
/*! Offset Y */
/* Note: the offset_y is positive and refers to the reference image */
#define MRV_SI_OFFSET_Y
#define MRV_SI_OFFSET_Y_MASK 0x00003FFFU
#define MRV_SI_OFFSET_Y_SHIFT 0U

/*! Register: super_imp_color_y: Y component of transparent key color (0x0000000c)*/
/*! Slice: y_comp:*/
/*! Y component of transparent key color */
#define MRV_SI_Y_COMP
#define MRV_SI_Y_COMP_MASK 0x000000FFU
#define MRV_SI_Y_COMP_SHIFT 0U

/*! Register: super_imp_color_cb: Cb component of transparent key color (0x00000010)*/
/*! Slice: cb_comp:*/
/*! Cb component of transparent key color */
#define MRV_SI_CB_COMP
#define MRV_SI_CB_COMP_MASK 0x000000FFU
#define MRV_SI_CB_COMP_SHIFT 0U

/*! Register: super_imp_color_cr: Cr component of transparent key color (0x00000014)*/
/*! Slice: cr_comp:*/
/*! Cr component of transparent key color */
#define MRV_SI_CR_COMP
#define MRV_SI_CR_COMP_MASK 0x000000FFU
#define MRV_SI_CR_COMP_SHIFT 0U

/*! Register: isp_ctrl: global control register (0x00000000)*/
#ifdef ISP_RGBIR
/*! Slice ISP_IR_RAW_OUT:*/
/*! 0: RGBIR IR RAW OUT is disable */
/*! 1: RGBIR IR RAW OUT is enable */
#define ISP_IR_RAW_OUT
#define ISP_IR_RAW_OUT_MASK 0x000400000U
#define ISP_IR_RAW_OUT_SHIFT 22U
#endif

/*! Slice PP_WRITE_SEL:*/
/*! 0: select yuv output */
/*! 1: select raw output */
#define PP_WRITE_SEL
#define PP_WRITE_SEL_MASK 0x1 << 23
#define PP_WRITE_SEL_SHIFT 23U

#ifdef ISP_DPF_RAW
/*! Slice MRV_ISP_DPF_RAW_OUT:*/
/*! 0: DPF RAW OUT is disable */
/*! 1: DPF RAW OUT is enable */
#define MRV_ISP_DPF_RAW_OUT
#define MRV_ISP_DPF_RAW_OUT_MASK 0x00040000U
#define MRV_ISP_DPF_RAW_OUT_SHIFT 18U
#endif

/*! Slice: digi_gain_EN:*/
/*! 0:  is disbaled */
/* 1:  is enabled.*/
#define MRV_ISP_DIGITAL_GAIN_EN
#define MRV_ISP_DIGITAL_GAIN_EN_MASK 0x00080000U
#define MRV_ISP_DIGITAL_GAIN_EN_SHIFT 19U

/*! Slice: CNR_EN:*/
/*! 0: CNR is disbaled */
/* 1: CNR is enabled.*/
#define MRV_ISP_CNR_EN
#define MRV_ISP_CNR_EN_MASK 0x00020000U
#define MRV_ISP_CNR_EN_SHIFT 17U
/*! Slice: CTRL_RESERVED_1:*/
/*! reserved */
#define MRV_ISP_CTRL_RESERVED_1
#define MRV_ISP_CTRL_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_CTRL_RESERVED_1_SHIFT 16U
/*! Slice: CTRL_RESERVED_2:*/
/*! reserved */
#define MRV_ISP_CTRL_RESERVED_2
#define MRV_ISP_CTRL_RESERVED_2_MASK 0x00008000U
#define MRV_ISP_CTRL_RESERVED_2_SHIFT 15U
/*! Slice: ISP_CSM_C_RANGE:*/
/*! Color Space Matrix chrominance clipping range for ISP output */
/* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
/* 1: full UV range 0..1023 ( 0..255)*/
/* Numbers in brackets are for 8 bit resolution.*/
/* This bit also configures the YCbCr sequence align block accordingly.*/
#define MRV_ISP_ISP_CSM_C_RANGE
#define MRV_ISP_ISP_CSM_C_RANGE_MASK 0x00004000U
#define MRV_ISP_ISP_CSM_C_RANGE_SHIFT 14U
/*! Slice: ISP_CSM_Y_RANGE:*/
/*! Color Space Matrix luminance clipping range for ISP output */
/* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
/* 1: full Y range 0..1023 ( 0..255)*/
/* Numbers in brackets are for 8 bit resolution.*/
/* This bit also configures the YCbCr sequence align block accordingly.*/
#define MRV_ISP_ISP_CSM_Y_RANGE
#define MRV_ISP_ISP_CSM_Y_RANGE_MASK 0x00002000U
#define MRV_ISP_ISP_CSM_Y_RANGE_SHIFT 13U
/*! Slice: ISP_FLASH_MODE:*/
/*! 0: sensor interface works independently from flash control unit */
/* 1: one frame is captured when signaled by flash control unit */
#define MRV_ISP_ISP_FLASH_MODE
#define MRV_ISP_ISP_FLASH_MODE_MASK 0x00001000U
#define MRV_ISP_ISP_FLASH_MODE_SHIFT 12U
/*! Slice: ISP_GAMMA_OUT_ENABLE:*/
/*! gamma ON/OFF */
#define MRV_ISP_ISP_GAMMA_OUT_ENABLE
#define MRV_ISP_ISP_GAMMA_OUT_ENABLE_MASK 0x00000800U
#define MRV_ISP_ISP_GAMMA_OUT_ENABLE_SHIFT 11U
/*! Slice: ISP_GEN_CFG_UPD:*/
/*! 1: generate frame synchronous configuration signal at the output of ISP for shadow registers of the following processing modules, write only */
#define MRV_ISP_ISP_GEN_CFG_UPD
#define MRV_ISP_ISP_GEN_CFG_UPD_MASK 0x00000400U
#define MRV_ISP_ISP_GEN_CFG_UPD_SHIFT 10U
/*! Slice: ISP_CFG_UPD:*/
/*! 1: immediately configure (update) shadow registers, write only */
#define MRV_ISP_ISP_CFG_UPD
#define MRV_ISP_ISP_CFG_UPD_MASK 0x00000200U
#define MRV_ISP_ISP_CFG_UPD_SHIFT 9U
/*! Slice: ISP_CFG_UPD_PERMANENT:*/
/*! 1: permanent configure (update) shadow registers on frame end.*/
#define MRV_ISP_ISP_CFG_UPD_PERMANENT
#define MRV_ISP_ISP_CFG_UPD_PERMANENT_MASK 0x00000100U
#define MRV_ISP_ISP_CFG_UPD_PERMANENT_SHIFT 8U
/*! Slice: ISP_AWB_ENABLE:*/
/*! auto white balance ON/OFF */
#define MRV_ISP_ISP_AWB_ENABLE
#define MRV_ISP_ISP_AWB_ENABLE_MASK 0x00000080U
#define MRV_ISP_ISP_AWB_ENABLE_SHIFT 7U
/*! Slice: ISP_GAMMA_IN_ENABLE:*/
/*! Sensor De-gamma ON/OFF */
#define MRV_ISP_ISP_GAMMA_IN_ENABLE
#define MRV_ISP_ISP_GAMMA_IN_ENABLE_MASK 0x00000040U
#define MRV_ISP_ISP_GAMMA_IN_ENABLE_SHIFT 6U
/*! Slice: ISP_INFORM_ENABLE:*/
/*! 1: input formatter enabled */
/* 0: input formatter disabled */
/* The ISP input formatter is enabled or disabled by this bit immediately, but always starts or stops acquisition frame synchronously.*/
#define MRV_ISP_ISP_INFORM_ENABLE
#define MRV_ISP_ISP_INFORM_ENABLE_MASK 0x00000010U
#define MRV_ISP_ISP_INFORM_ENABLE_SHIFT 4U
/*! Slice: ISP_MODE:*/
/*! 000 - RAW picture with BT.601 sync (ISP bypass)*/
/* 001 - ITU-R BT.656 (YUV with embedded sync)*/
/* 010 - ITU-R BT.601 (YUV input with H and Vsync signals)*/
/* 011 - Bayer RGB processing with H and Vsync signals */
/* 100 - data mode (ISP bypass, sync signals interpreted as data enable)*/
/* 101 - Bayer RGB processing with BT.656 synchronization */
/* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/
/* 111 - reserved */
 /**/
/* Side effect:*/
/* If RAW, BT.601, BT.656, or data mode is selected, the clock of the ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off. Only in Bayer RGB mode the clock to the SRAMs is enabled. This further reduces power consumption.*/
#define MRV_ISP_ISP_MODE
#define MRV_ISP_ISP_MODE_MASK 0x0000000EU
#define MRV_ISP_ISP_MODE_SHIFT 1U
/*! Slice: ISP_ENABLE:*/
/*! 1: ISP data output enabled */
/* 0: ISP data output disabled */
/* Controls output formatter frame synchronously, if isp_gen_cfg_upd is used to activate this bit. For immediate update isp_cfg_upd must be used.*/
#define MRV_ISP_ISP_ENABLE
#define MRV_ISP_ISP_ENABLE_MASK 0x00000001U
#define MRV_ISP_ISP_ENABLE_SHIFT 0U
/*! Register: isp_acq_prop: ISP acquisition properties (0x00000004)*/
#ifdef ISP_DVP_PINMAPPING
/*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */
/*! Bit Mapping for LSB to MSP for ISPNano.*/
/*! 3'b000: normal 12-bit external interface */
/*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/
/*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/
/*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/
/*! 3'b100..3'b111: rsvd */
#define MRV_ISP_DVP_INPUT_PIN_MAPPING
#define MRV_ISP_DVP_INPUT_PIN_MAPPING_MASK 0x000E0000U
#define MRV_ISP_DVP_INPUT_PIN_MAPPING_SHIFT 17U
#endif
/*! Slice: DMA_YUV_SELECTION */
/*! 0: use align or conversion data for isp_is input */
/*! 1: use dma yuv read data for isp_is input */
#define MRV_ISP_DMA_YUV_SELECTION
#define MRV_ISP_DMA_YUV_SELECTION_MASK 0x00010000U
#define MRV_ISP_DMA_YUV_SELECTION_SHIFT 16U
/*! Slice: LATENCY_FIFO_SELECTION:*/
/*! 0: use input formatter input for latency fifo.*/
/* 1: use dma rgb read input for latency fifo.*/
#define MRV_ISP_LATENCY_FIFO_SELECTION
#define MRV_ISP_LATENCY_FIFO_SELECTION_MASK 0x00008000U
#define MRV_ISP_LATENCY_FIFO_SELECTION_SHIFT 15U
/*! Slice: INPUT_SELECTION:*/
/*! 000- 12Bit external Interface */
/* 001- 10Bit Interface, append 2 zeroes as LSBs */
/* 010- 10Bit Interface, append 2 MSBs as LSBs */
/* 011- 8Bit Interface, append 4 zeroes as LSBs */
/* 100- 8Bit Interface, append 4 MSBs as LSBs */
/* 101...111 reserved */
#define MRV_ISP_INPUT_SELECTION
#define MRV_ISP_INPUT_SELECTION_MASK 0x00007000U
#define MRV_ISP_INPUT_SELECTION_SHIFT 12U
/*! Slice: FIELD_INV:*/
/*! 1: swap odd and even fields */
/* 0: do not swap fields */
#define MRV_ISP_FIELD_INV
#define MRV_ISP_FIELD_INV_MASK 0x00000800U
#define MRV_ISP_FIELD_INV_SHIFT 11U
/*! Slice: FIELD_SELECTION:*/
/*! 00- sample all fields (don�t care about fields)*/
/* 01- sample only even fields */
/* 10- sample only odd fields */
/* 11- reserved */
#define MRV_ISP_FIELD_SELECTION
#define MRV_ISP_FIELD_SELECTION_MASK 0x00000600U
#define MRV_ISP_FIELD_SELECTION_SHIFT 9U
/*! Slice: CCIR_SEQ:*/
/*! 00- YCbYCr */
/* 01- YCrYCb */
/* 10- CbYCrY */
/* 11- CrYCbY */
#define MRV_ISP_CCIR_SEQ
#define MRV_ISP_CCIR_SEQ_MASK 0x00000180U
#define MRV_ISP_CCIR_SEQ_SHIFT 7U
/*! Slice: CONV_422:*/
/*! 00- co-sited color subsampling Y0Cb0Cr0  Y1 */
/* 01- interleaved color subsampling Y0Cb0  Y1Cr1 (not recommended)*/
/* 10- non-cosited color subsampling Y0Cb(0+1)/2  Y1Cr(0+1)/2 */
/* 11- reserved */
#define MRV_ISP_CONV_422
#define MRV_ISP_CONV_422_MASK 0x00000060U
#define MRV_ISP_CONV_422_SHIFT 5U
/*! Slice: BAYER_PAT:*/
/*! color components from sensor, starting with top left position in sampled frame (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/
/* 00- first line: RGRG..., second line: GBGB..., etc.*/
/* 01- first line: GRGR..., second line: BGBG..., etc.*/
/* 10- first line: GBGB..., second line: RGRG..., etc.*/
/* 11- first line: BGBG..., second line: GRGR..., etc.*/
/* This configuration applies for the black level area after cropping by the input formatter.*/
#define MRV_ISP_BAYER_PAT
#define MRV_ISP_BAYER_PAT_MASK 0x00000018U
#define MRV_ISP_BAYER_PAT_SHIFT 3U
/*! Slice: VSYNC_POL:*/
/*! vertical sync polarity */
/* 0: high active */
/* 1: low active */
#define MRV_ISP_VSYNC_POL
#define MRV_ISP_VSYNC_POL_MASK 0x00000004U
#define MRV_ISP_VSYNC_POL_SHIFT 2U
/*! Slice: HSYNC_POL:*/
/*! horizontal sync polarity */
/* 0: high active */
/* 1: low active */
#define MRV_ISP_HSYNC_POL
#define MRV_ISP_HSYNC_POL_MASK 0x00000002U
#define MRV_ISP_HSYNC_POL_SHIFT 1U
/*! Slice: SAMPLE_EDGE:*/
/*! 0- negative edge sampling */
/* 1- positive edge sampling */
#define MRV_ISP_SAMPLE_EDGE
#define MRV_ISP_SAMPLE_EDGE_MASK 0x00000001U
#define MRV_ISP_SAMPLE_EDGE_SHIFT 0U
/*! Register: isp_acq_h_offs: horizontal input offset (0x00000008)*/
/*! Slice: ACQ_H_OFFS:*/
/*! horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/
#define MRV_ISP_ACQ_H_OFFS
#define MRV_ISP_ACQ_H_OFFS_MASK 0x00007FFFU
#define MRV_ISP_ACQ_H_OFFS_SHIFT 0U
/*! Register: isp_acq_v_offs: vertical input offset (0x0000000c)*/
/*! Slice: ACQ_V_OFFS:*/
/*! vertical sample offset in lines */
#define MRV_ISP_ACQ_V_OFFS
#define MRV_ISP_ACQ_V_OFFS_MASK 0x00003FFFU
#define MRV_ISP_ACQ_V_OFFS_SHIFT 0U
/*! Register: isp_acq_h_size: horizontal input size (0x00000010)*/
/*! Slice: ACQ_H_SIZE:*/
/*! horizontal sample size in 12-bit samples */
/* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */
/* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */
#define MRV_ISP_ACQ_H_SIZE
#define MRV_ISP_ACQ_H_SIZE_MASK 0x00007FFFU
#define MRV_ISP_ACQ_H_SIZE_SHIFT 0U
/*! Register: isp_acq_v_size: vertical input size (0x00000014)*/
/*! Slice: ACQ_V_SIZE:*/
/*! vertical sample size in lines */
#define MRV_ISP_ACQ_V_SIZE
#define MRV_ISP_ACQ_V_SIZE_MASK 0x00003FFFU
#define MRV_ISP_ACQ_V_SIZE_SHIFT 0U
/*! Register: isp_acq_nr_frames: Number of frames to be captured (0x00000018)*/
/*! Slice: ACQ_NR_FRAMES:*/
/*! number of input frames to be sampled ( 0 = continuous )*/
#define MRV_ISP_ACQ_NR_FRAMES
#define MRV_ISP_ACQ_NR_FRAMES_MASK 0x000003FFU
#define MRV_ISP_ACQ_NR_FRAMES_SHIFT 0U
/*! Register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments (sampling points) (0x0000001c)*/
/*! Slice: GAMMA_DX_8:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_8
#define MRV_ISP_GAMMA_DX_8_MASK 0x70000000U
#define MRV_ISP_GAMMA_DX_8_SHIFT 28U
/*! Slice: GAMMA_DX_7:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_7
#define MRV_ISP_GAMMA_DX_7_MASK 0x07000000U
#define MRV_ISP_GAMMA_DX_7_SHIFT 24U
/*! Slice: GAMMA_DX_6:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_6
#define MRV_ISP_GAMMA_DX_6_MASK 0x00700000U
#define MRV_ISP_GAMMA_DX_6_SHIFT 20U
/*! Slice: GAMMA_DX_5:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_5
#define MRV_ISP_GAMMA_DX_5_MASK 0x00070000U
#define MRV_ISP_GAMMA_DX_5_SHIFT 16U
/*! Slice: GAMMA_DX_4:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_4
#define MRV_ISP_GAMMA_DX_4_MASK 0x00007000U
#define MRV_ISP_GAMMA_DX_4_SHIFT 12U
/*! Slice: GAMMA_DX_3:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_3
#define MRV_ISP_GAMMA_DX_3_MASK 0x00000700U
#define MRV_ISP_GAMMA_DX_3_SHIFT 8U
/*! Slice: GAMMA_DX_2:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_2
#define MRV_ISP_GAMMA_DX_2_MASK 0x00000070U
#define MRV_ISP_GAMMA_DX_2_SHIFT 4U
/*! Slice: GAMMA_DX_1:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_1
#define MRV_ISP_GAMMA_DX_1_MASK 0x00000007U
#define MRV_ISP_GAMMA_DX_1_SHIFT 0U
/*! Register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments (sampling points) (0x00000020)*/
/*! Slice: GAMMA_DX_16:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_16
#define MRV_ISP_GAMMA_DX_16_MASK 0x70000000U
#define MRV_ISP_GAMMA_DX_16_SHIFT 28U
/*! Slice: GAMMA_DX_15:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_15
#define MRV_ISP_GAMMA_DX_15_MASK 0x07000000U
#define MRV_ISP_GAMMA_DX_15_SHIFT 24U
/*! Slice: GAMMA_DX_14:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_14
#define MRV_ISP_GAMMA_DX_14_MASK 0x00700000U
#define MRV_ISP_GAMMA_DX_14_SHIFT 20U
/*! Slice: GAMMA_DX_13:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_13
#define MRV_ISP_GAMMA_DX_13_MASK 0x00070000U
#define MRV_ISP_GAMMA_DX_13_SHIFT 16U
/*! Slice: GAMMA_DX_12:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_12
#define MRV_ISP_GAMMA_DX_12_MASK 0x00007000U
#define MRV_ISP_GAMMA_DX_12_SHIFT 12U
/*! Slice: GAMMA_DX_11:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_11
#define MRV_ISP_GAMMA_DX_11_MASK 0x00000700U
#define MRV_ISP_GAMMA_DX_11_SHIFT 8U
/*! Slice: GAMMA_DX_10:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_10
#define MRV_ISP_GAMMA_DX_10_MASK 0x00000070U
#define MRV_ISP_GAMMA_DX_10_SHIFT 4U
/*! Slice: GAMMA_DX_9:*/
/*! gamma curve sample point definition x-axis (input)*/
#define MRV_ISP_GAMMA_DX_9
#define MRV_ISP_GAMMA_DX_9_MASK 0x00000007U
#define MRV_ISP_GAMMA_DX_9_SHIFT 0U
/*! Register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0048 + n*0x4 (n=0..16))*/
/*! Slice: GAMMA_R_Y:*/
/* gamma curve point definition y-axis (output) for red */
/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
#define MRV_ISP_GAMMA_R_Y
#define MRV_ISP_GAMMA_R_Y_MASK 0x00000FFFU
#define MRV_ISP_GAMMA_R_Y_SHIFT 0U
/*! Register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0090 + n*0x4 (n=0..16))*/
/*! Slice: GAMMA_G_Y:*/
/* gamma curve point definition y-axis (output) for green */
/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
#define MRV_ISP_GAMMA_G_Y
#define MRV_ISP_GAMMA_G_Y_MASK 0x00000FFFU
#define MRV_ISP_GAMMA_G_Y_SHIFT 0U
/*! Register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00D8 + n*0x4 (n=0..16))*/
/*! Slice: GAMMA_B_Y:*/
/* gamma curve point definition y-axis (output) for blue */
/* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
#define MRV_ISP_GAMMA_B_Y
#define MRV_ISP_GAMMA_B_Y_MASK 0x00000FFFU
#define MRV_ISP_GAMMA_B_Y_SHIFT 0U
/*! Register: isp_awb_prop: Auto white balance properties (0x00000110)*/
/*! Slice: AWB_MEAS_MODE:*/
/*! 1: RGB based measurement mode */
/* 0: near white discrimination mode using YCbCr color space */
#define MRV_ISP_AWB_MEAS_MODE
#define MRV_ISP_AWB_MEAS_MODE_MASK 0x80000000U
#define MRV_ISP_AWB_MEAS_MODE_SHIFT 31U
/*! Slice: AWB_MAX_EN:*/
/*! 1: enable Y_MAX compare */
/* 0: disable Y_MAX compare */
/* Not valid in RGB measurement mode.*/
#define MRV_ISP_AWB_MAX_EN
#define MRV_ISP_AWB_MAX_EN_MASK 0x00000004U
#define MRV_ISP_AWB_MAX_EN_SHIFT 2U
/*! Slice: AWB_MODE:*/
/*! AWB_MODE(1:0):*/
/* 11: reserved */
/* 10: measurement of YCbCr means (AWB_MEAS_MODE = 0) or RGB means (AWB_MEAS_MODE = 1)*/
/* 01: reserved */
/* 00: no measurement */
#define MRV_ISP_AWB_MODE
#define MRV_ISP_AWB_MODE_MASK 0x00000003U
#define MRV_ISP_AWB_MODE_SHIFT 0U
/*! Register: isp_awb_h_offs: Auto white balance horizontal offset of measure window (0x00000114)*/
/*! Slice: AWB_H_OFFS:*/
/*! horizontal window offset in pixel */
#define MRV_ISP_AWB_H_OFFS
#define MRV_ISP_AWB_H_OFFS_MASK 0x00001FFFU
#define MRV_ISP_AWB_H_OFFS_SHIFT 0U
/*! Register: isp_awb_v_offs: Auto white balance vertical offset of measure window (0x00000118)*/
/*! Slice: AWB_V_OFFS:*/
/*! vertical window offset in lines */
#define MRV_ISP_AWB_V_OFFS
#define MRV_ISP_AWB_V_OFFS_MASK 0x00001FFFU
#define MRV_ISP_AWB_V_OFFS_SHIFT 0U
/*! Register: isp_awb_h_size: Auto white balance horizontal window size (0x0000011c)*/
/*! Slice: AWB_H_SIZE:*/
/*! horizontal measurement window size in pixel */
#define MRV_ISP_AWB_H_SIZE
#define MRV_ISP_AWB_H_SIZE_MASK 0x00003FFFU
#define MRV_ISP_AWB_H_SIZE_SHIFT 0U
/*! Register: isp_awb_v_size: Auto white balance vertical window size (0x00000120)*/
/*! Slice: AWB_V_SIZE:*/
/*! vertical measurement window size in lines */
#define MRV_ISP_AWB_V_SIZE
#define MRV_ISP_AWB_V_SIZE_MASK 0x00003FFFU
#define MRV_ISP_AWB_V_SIZE_SHIFT 0U
/*! Register: isp_awb_frames: Auto white balance mean value over multiple frames (0x00000124)*/
/*! Slice: AWB_FRAMES:*/
/*! number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/
#define MRV_ISP_AWB_FRAMES
#define MRV_ISP_AWB_FRAMES_MASK 0x00000007U
#define MRV_ISP_AWB_FRAMES_SHIFT 0U
/*! Register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x00000128)*/
/*! Slice: AWB_REF_CR__MAX_R:*/
/*! - reference Cr value for AWB regulation, target for AWB */
/* - maximum red value, if RGB measurement mode is selected */
#define MRV_ISP_AWB_REF_CR__MAX_R
#define MRV_ISP_AWB_REF_CR__MAX_R_MASK 0x0000FF00U
#define MRV_ISP_AWB_REF_CR__MAX_R_SHIFT 8U
/*! Slice: AWB_REF_CB__MAX_B:*/
/*! - reference Cb value for AWB regulation, target for AWB */
/* - maximum blue value, if RGB measurement mode is selected */
#define MRV_ISP_AWB_REF_CB__MAX_B
#define MRV_ISP_AWB_REF_CB__MAX_B_MASK 0x000000FFU
#define MRV_ISP_AWB_REF_CB__MAX_B_SHIFT 0U
/*! Register: isp_awb_thresh: Auto white balance threshold values (0x0000012c)*/
/*! Slice: AWB_MAX_Y:*/
/*! Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by register AWB_MODE bit AWB_MAX_EN). Not valid for RGB measurement mode.*/
#define MRV_ISP_AWB_MAX_Y
#define MRV_ISP_AWB_MAX_Y_MASK 0xFF000000U
#define MRV_ISP_AWB_MAX_Y_SHIFT 24U
/*! Slice: AWB_MIN_Y__MAX_G:*/
/*! - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */
/* - maximum green value, if RGB measurement mode is selected */
#define MRV_ISP_AWB_MIN_Y__MAX_G
#define MRV_ISP_AWB_MIN_Y__MAX_G_MASK 0x00FF0000U
#define MRV_ISP_AWB_MIN_Y__MAX_G_SHIFT 16U
/*! Slice: AWB_MAX_CSUM:*/
/*! Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */
#define MRV_ISP_AWB_MAX_CSUM
#define MRV_ISP_AWB_MAX_CSUM_MASK 0x0000FF00U
#define MRV_ISP_AWB_MAX_CSUM_SHIFT 8U
/*! Slice: AWB_MIN_C:*/
/*! Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */
#define MRV_ISP_AWB_MIN_C
#define MRV_ISP_AWB_MIN_C_MASK 0x000000FFU
#define MRV_ISP_AWB_MIN_C_SHIFT 0U

#ifdef  ISP_AWB_0410 //This is Gain value component  4 bit int part and 10 bit fractional part
/*! Register: isp_awb_gain_g: Auto white balance gain green (0x00000138)*/
/*! Slice: AWB_GAIN_GR:*/
/*! gain value for green component in red line 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
#define MRV_ISP_AWB_GAIN_GR
#define MRV_ISP_AWB_GAIN_GR_MASK 0x3FFF0000U
#define MRV_ISP_AWB_GAIN_GR_SHIFT 16U
/*! Slice: AWB_GAIN_GB:*/
/*! gain value for green component in blue line 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
#define MRV_ISP_AWB_GAIN_GB
#define MRV_ISP_AWB_GAIN_GB_MASK 0x00003FFFU
#define MRV_ISP_AWB_GAIN_GB_SHIFT 0U
/*! Register: isp_awb_gain_rb: Auto white balance gain red and blue (0x0000013c)*/
/*! Slice: AWB_GAIN_R:*/
/*! gain value for red component 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
#define MRV_ISP_AWB_GAIN_R
#define MRV_ISP_AWB_GAIN_R_MASK 0x3FFF0000U
#define MRV_ISP_AWB_GAIN_R_SHIFT 16U
/*! Slice: AWB_GAIN_B:*/
/*! gain value for blue component 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
#define MRV_ISP_AWB_GAIN_B
#define MRV_ISP_AWB_GAIN_B_MASK 0x00003FFFU
#define MRV_ISP_AWB_GAIN_B_SHIFT 0U
#else//This is Gain value component  2 bit int part and 8 bit fractional part
/*! Register: isp_awb_gain_g: Auto white balance gain green (0x00000138)*/
/*! Slice: AWB_GAIN_GR:*/
/*! gain value for green component in red line 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
#define MRV_ISP_AWB_GAIN_GR
#define MRV_ISP_AWB_GAIN_GR_MASK 0x03FF0000U
#define MRV_ISP_AWB_GAIN_GR_SHIFT 16U
/*! Slice: AWB_GAIN_GB:*/
/*! gain value for green component in blue line 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
#define MRV_ISP_AWB_GAIN_GB
#define MRV_ISP_AWB_GAIN_GB_MASK 0x000003FFU
#define MRV_ISP_AWB_GAIN_GB_SHIFT 0U
/*! Register: isp_awb_gain_rb: Auto white balance gain red and blue (0x0000013c)*/
/*! Slice: AWB_GAIN_R:*/
/*! gain value for red component 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
#define MRV_ISP_AWB_GAIN_R
#define MRV_ISP_AWB_GAIN_R_MASK 0x03FF0000U
#define MRV_ISP_AWB_GAIN_R_SHIFT 16U
/*! Slice: AWB_GAIN_B:*/
/*! gain value for blue component 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
#define MRV_ISP_AWB_GAIN_B
#define MRV_ISP_AWB_GAIN_B_MASK 0x000003FFU
#define MRV_ISP_AWB_GAIN_B_SHIFT 0U
#endif
/*! Register: isp_awb_white_cnt: Auto white balance white pixel count (0x00000140)*/
/*! Slice: AWB_WHITE_CNT:*/
/*! White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */
#define MRV_ISP_AWB_WHITE_CNT
#define MRV_ISP_AWB_WHITE_CNT_MASK 0x03FFFFFFU
#define MRV_ISP_AWB_WHITE_CNT_SHIFT 0U
/*! Register: isp_awb_mean: Auto white balance measured mean value (0x00000144)*/
/*! Slice: AWB_MEAN_Y__G:*/
/*! - mean value of Y within window and frames */
/* - mean value of green, if RGB measurement mode is selected */
#define MRV_ISP_AWB_MEAN_Y__G
#define MRV_ISP_AWB_MEAN_Y__G_MASK 0x00FF0000U
#define MRV_ISP_AWB_MEAN_Y__G_SHIFT 16U
/*! Slice: AWB_MEAN_CB__B:*/
/*! - mean value of Cb within window and frames */
/* - mean value of blue, if RGB measurement mode is selected */
#define MRV_ISP_AWB_MEAN_CB__B
#define MRV_ISP_AWB_MEAN_CB__B_MASK 0x0000FF00U
#define MRV_ISP_AWB_MEAN_CB__B_SHIFT 8U
/*! Slice: AWB_MEAN_CR__R:*/
/*! - mean value of Cr within window and frames */
/* - mean value of red, if RGB measurement mode is selected */
#define MRV_ISP_AWB_MEAN_CR__R
#define MRV_ISP_AWB_MEAN_CR__R_MASK 0x000000FFU
#define MRV_ISP_AWB_MEAN_CR__R_SHIFT 0U
/*! Register: isp_cc_coeff_0: Color conversion coefficient 0 (0x00000170)*/
/*! Slice: cc_coeff_0:*/
/*! coefficient 0 for color space conversion */
#define MRV_ISP_CC_COEFF_0
#define MRV_ISP_CC_COEFF_0_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_0_SHIFT 0U
/*! Register: isp_cc_coeff_1: Color conversion coefficient 1 (0x00000174)*/
/*! Slice: cc_coeff_1:*/
/*! coefficient 1 for color space conversion */
#define MRV_ISP_CC_COEFF_1
#define MRV_ISP_CC_COEFF_1_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_1_SHIFT 0U
/*! Register: isp_cc_coeff_2: Color conversion coefficient 2 (0x00000178)*/
/*! Slice: cc_coeff_2:*/
/*! coefficient 2 for color space conversion */
#define MRV_ISP_CC_COEFF_2
#define MRV_ISP_CC_COEFF_2_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_2_SHIFT 0U
/*! Register: isp_cc_coeff_3: Color conversion coefficient 3 (0x0000017c)*/
/*! Slice: cc_coeff_3:*/
/*! coefficient 3 for color space conversion */
#define MRV_ISP_CC_COEFF_3
#define MRV_ISP_CC_COEFF_3_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_3_SHIFT 0U
/*! Register: isp_cc_coeff_4: Color conversion coefficient 4 (0x00000180)*/
/*! Slice: cc_coeff_4:*/
/*! coefficient 4 for color space conversion */
#define MRV_ISP_CC_COEFF_4
#define MRV_ISP_CC_COEFF_4_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_4_SHIFT 0U
/*! Register: isp_cc_coeff_5: Color conversion coefficient 5 (0x00000184)*/
/*! Slice: cc_coeff_5:*/
/*! coefficient 5 for color space conversion */
#define MRV_ISP_CC_COEFF_5
#define MRV_ISP_CC_COEFF_5_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_5_SHIFT 0U
/*! Register: isp_cc_coeff_6: Color conversion coefficient 6 (0x00000188)*/
/*! Slice: cc_coeff_6:*/
/*! coefficient 6 for color space conversion */
#define MRV_ISP_CC_COEFF_6
#define MRV_ISP_CC_COEFF_6_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_6_SHIFT 0U
/*! Register: isp_cc_coeff_7: Color conversion coefficient 7 (0x0000018c)*/
/*! Slice: cc_coeff_7:*/
/*! coefficient 7 for color space conversion */
#define MRV_ISP_CC_COEFF_7
#define MRV_ISP_CC_COEFF_7_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_7_SHIFT 0U
/*! Register: isp_cc_coeff_8: Color conversion coefficient 8 (0x00000190)*/
/*! Slice: cc_coeff_8:*/
/*! coefficient 8 for color space conversion */
#define MRV_ISP_CC_COEFF_8
#define MRV_ISP_CC_COEFF_8_MASK 0x000001FFU
#define MRV_ISP_CC_COEFF_8_SHIFT 0U
/*! Register: isp_out_h_offs: Horizontal offset of output window (0x00000194)*/
/*! Slice: ISP_OUT_H_OFFS:*/
/*! vertical pic offset in lines */
#define MRV_ISP_ISP_OUT_H_OFFS
#define MRV_ISP_ISP_OUT_H_OFFS_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_H_OFFS_SHIFT 0U
/*! Register: isp_out_v_offs: Vertical offset of output window (0x00000198)*/
/*! Slice: ISP_OUT_V_OFFS:*/
/*! vertical pic offset in lines */
#define MRV_ISP_ISP_OUT_V_OFFS
#define MRV_ISP_ISP_OUT_V_OFFS_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_V_OFFS_SHIFT 0U
/*! Register: isp_out_h_size: Output horizontal picture size (0x0000019c)*/
/*! Slice: ISP_OUT_H_SIZE:*/
/*! horizontal picture size in pixel */
/* if ISP_MODE is set to */
/* 001-(ITU-R BT.656 YUV),*/
/* 010-( ITU-R BT.601 YUV),*/
/* 011-( ITU-R BT.601 Bayer RGB),*/
/* 101-( ITU-R BT.656 Bayer RGB)*/
/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the 422 output. (if an odd size is programmed the value will be truncated to even size)*/
#define MRV_ISP_ISP_OUT_H_SIZE
#define MRV_ISP_ISP_OUT_H_SIZE_MASK 0x00007FFFU
#define MRV_ISP_ISP_OUT_H_SIZE_SHIFT 0U
/*! Register: isp_out_v_size: Output vertical picture size (0x000001a0)*/
/*! Slice: ISP_OUT_V_SIZE:*/
/*! vertical pic size in lines */
#define MRV_ISP_ISP_OUT_V_SIZE
#define MRV_ISP_ISP_OUT_V_SIZE_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_V_SIZE_SHIFT 0U
/*! Register: isp_demosaic: Demosaic parameters (0x000001a4)*/
/*! Slice: DEMOSAIC_BYPASS:*/
/*! 0: normal operation for RGB Bayer Pattern input */
/* 1: demosaicing bypass for Black&White input data */
#define MRV_ISP_DEMOSAIC_BYPASS
#define MRV_ISP_DEMOSAIC_BYPASS_MASK 0x00000400U
#define MRV_ISP_DEMOSAIC_BYPASS_SHIFT 10U
/*! Slice: DEMOSAIC_TH:*/
/*! Threshold for Bayer demosaicing texture detection. This value shifted left 4bit is compared with the difference of the vertical and horizontal 12Bit wide texture indicators, to decide if the vertical or horizontal texture flag must be set.*/
/* 0xFF: no texture detection */
/* 0x00: maximum edge sensitivity */
#define MRV_ISP_DEMOSAIC_TH
#define MRV_ISP_DEMOSAIC_TH_MASK 0x000000FFU
#define MRV_ISP_DEMOSAIC_TH_SHIFT 0U
/*! Register: isp_flags_shd: Flags (current status) of certain signals and Shadow regs for enable signals (0x000001a8)*/
/*! Slice: S_HSYNC:*/
/*! state of ISP input port s_hsync, for test purposes */
#define MRV_ISP_S_HSYNC
#define MRV_ISP_S_HSYNC_MASK 0x80000000U
#define MRV_ISP_S_HSYNC_SHIFT 31U
/*! Slice: S_VSYNC:*/
/*! state of ISP input port s_vsync, for test purposes */
#define MRV_ISP_S_VSYNC
#define MRV_ISP_S_VSYNC_MASK 0x40000000U
#define MRV_ISP_S_VSYNC_SHIFT 30U
/*! Slice: S_DATA:*/
/*! state of ISP input port s_data, for test purposes */
#define MRV_ISP_S_DATA
#define MRV_ISP_S_DATA_MASK 0x0FFF0000U
#define MRV_ISP_S_DATA_SHIFT 16U
/*! Slice: INFORM_FIELD:*/
/*! current field information (0=odd, 1=even)*/
#define MRV_ISP_INFORM_FIELD
#define MRV_ISP_INFORM_FIELD_MASK 0x00000004U
#define MRV_ISP_INFORM_FIELD_SHIFT 2U
/*! Slice: ISP_INFORM_ENABLE_SHD:*/
/*! Input formatter enable shadow register */
#define MRV_ISP_ISP_INFORM_ENABLE_SHD
#define MRV_ISP_ISP_INFORM_ENABLE_SHD_MASK 0x00000002U
#define MRV_ISP_ISP_INFORM_ENABLE_SHD_SHIFT 1U
/*! Slice: ISP_ENABLE_SHD:*/
/*! ISP enable shadow register */
/* shows, if ISP currently outputs data (1) or not (0)*/
#define MRV_ISP_ISP_ENABLE_SHD
#define MRV_ISP_ISP_ENABLE_SHD_MASK 0x00000001U
#define MRV_ISP_ISP_ENABLE_SHD_SHIFT 0U
/*! Register: isp_out_h_offs_shd: current horizontal offset of output window (shadow register) (0x000001ac)*/
/*! Slice: ISP_OUT_H_OFFS_SHD:*/
/*! current vertical pic offset in lines */
#define MRV_ISP_ISP_OUT_H_OFFS_SHD
#define MRV_ISP_ISP_OUT_H_OFFS_SHD_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_H_OFFS_SHD_SHIFT 0U
/*! Register: isp_out_v_offs_shd: current vertical offset of output window (shadow register) (0x000001b0)*/
/*! Slice: ISP_OUT_V_OFFS_SHD:*/
/*! current vertical pic offset in lines */
#define MRV_ISP_ISP_OUT_V_OFFS_SHD
#define MRV_ISP_ISP_OUT_V_OFFS_SHD_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_V_OFFS_SHD_SHIFT 0U
/*! Register: isp_out_h_size_shd: current output horizontal picture size (shadow register) (0x000001b4)*/
/*! Slice: ISP_OUT_H_SIZE_SHD:*/
/*! current horizontal pic size in pixel */
#define MRV_ISP_ISP_OUT_H_SIZE_SHD
#define MRV_ISP_ISP_OUT_H_SIZE_SHD_MASK 0x00007FFFU
#define MRV_ISP_ISP_OUT_H_SIZE_SHD_SHIFT 0U
/*! Register: isp_out_v_size_shd: current output vertical picture size (shadow register) (0x000001b8)*/
/*! Slice: ISP_OUT_V_SIZE_SHD:*/
/*! vertical pic size in lines */
#define MRV_ISP_ISP_OUT_V_SIZE_SHD
#define MRV_ISP_ISP_OUT_V_SIZE_SHD_MASK 0x00003FFFU
#define MRV_ISP_ISP_OUT_V_SIZE_SHD_SHIFT 0U
/*! Register: isp_imsc: Interrupt mask (0x000001bc)*/
/*! Slice: IMSC_VSM_END:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_VSM_END
#define MRV_ISP_IMSC_VSM_END_MASK 0x00080000U
#define MRV_ISP_IMSC_VSM_END_SHIFT 19U
/*! Slice: IMSC_EXP_END:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_EXP_END
#define MRV_ISP_IMSC_EXP_END_MASK 0x00040000U
#define MRV_ISP_IMSC_EXP_END_SHIFT 18U
/*! Slice: IMSC_FLASH_CAP:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_FLASH_CAP
#define MRV_ISP_IMSC_FLASH_CAP_MASK 0x00020000U
#define MRV_ISP_IMSC_FLASH_CAP_SHIFT 17U
/*! Slice: IMSC_RESERVED_1:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_RESERVED_1
#define MRV_ISP_IMSC_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_IMSC_RESERVED_1_SHIFT 16U
/*! Slice: IMSC_HIST_MEASURE_RDY:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_HIST_MEASURE_RDY
#define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0x00008000U
#define MRV_ISP_IMSC_HIST_MEASURE_RDY_SHIFT 15U
/*! Slice: IMSC_AFM_FIN:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_AFM_FIN
#define MRV_ISP_IMSC_AFM_FIN_MASK 0x00004000U
#define MRV_ISP_IMSC_AFM_FIN_SHIFT 14U
/*! Slice: IMSC_AFM_LUM_OF:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_AFM_LUM_OF
#define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0x00002000U
#define MRV_ISP_IMSC_AFM_LUM_OF_SHIFT 13U
/*! Slice: IMSC_AFM_SUM_OF:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_AFM_SUM_OF
#define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0x00001000U
#define MRV_ISP_IMSC_AFM_SUM_OF_SHIFT 12U
/*! Slice: IMSC_SHUTTER_OFF:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_SHUTTER_OFF
#define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0x00000800U
#define MRV_ISP_IMSC_SHUTTER_OFF_SHIFT 11U
/*! Slice: IMSC_SHUTTER_ON:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_SHUTTER_ON
#define MRV_ISP_IMSC_SHUTTER_ON_MASK 0x00000400U
#define MRV_ISP_IMSC_SHUTTER_ON_SHIFT 10U
/*! Slice: IMSC_FLASH_OFF:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_FLASH_OFF
#define MRV_ISP_IMSC_FLASH_OFF_MASK 0x00000200U
#define MRV_ISP_IMSC_FLASH_OFF_SHIFT 9U
/*! Slice: IMSC_FLASH_ON:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_FLASH_ON
#define MRV_ISP_IMSC_FLASH_ON_MASK 0x00000100U
#define MRV_ISP_IMSC_FLASH_ON_SHIFT 8U
/*! Slice: IMSC_H_START:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_H_START
#define MRV_ISP_IMSC_H_START_MASK 0x00000080U
#define MRV_ISP_IMSC_H_START_SHIFT 7U
/*! Slice: IMSC_V_START:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_V_START
#define MRV_ISP_IMSC_V_START_MASK 0x00000040U
#define MRV_ISP_IMSC_V_START_SHIFT 6U
/*! Slice: IMSC_FRAME_IN:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_FRAME_IN
#define MRV_ISP_IMSC_FRAME_IN_MASK 0x00000020U
#define MRV_ISP_IMSC_FRAME_IN_SHIFT 5U
/*! Slice: IMSC_AWB_DONE:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_AWB_DONE
#define MRV_ISP_IMSC_AWB_DONE_MASK 0x00000010U
#define MRV_ISP_IMSC_AWB_DONE_SHIFT 4U
/*! Slice: IMSC_PIC_SIZE_ERR:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_PIC_SIZE_ERR
#define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0x00000008U
#define MRV_ISP_IMSC_PIC_SIZE_ERR_SHIFT 3U
/*! Slice: IMSC_DATA_LOSS:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_DATA_LOSS
#define MRV_ISP_IMSC_DATA_LOSS_MASK 0x00000004U
#define MRV_ISP_IMSC_DATA_LOSS_SHIFT 2U
/*! Slice: IMSC_FRAME:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_FRAME
#define MRV_ISP_IMSC_FRAME_MASK 0x00000002U
#define MRV_ISP_IMSC_FRAME_SHIFT 1U
/*! Slice: IMSC_ISP_OFF:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_ISP_IMSC_ISP_OFF
#define MRV_ISP_IMSC_ISP_OFF_MASK 0x00000001U
#define MRV_ISP_IMSC_ISP_OFF_SHIFT 0U
/*! Register: isp_ris: Raw interrupt status (0x000001c0)*/
/*! Slice: RIS_VSM_END:*/
/*! VSM measurement complete */
#define MRV_ISP_RIS_VSM_END
#define MRV_ISP_RIS_VSM_END_MASK 0x00080000U
#define MRV_ISP_RIS_VSM_END_SHIFT 19U
/*! Slice: RIS_EXP_END:*/
/*! Exposure measurement complete */
#define MRV_ISP_RIS_EXP_END
#define MRV_ISP_RIS_EXP_END_MASK 0x00040000U
#define MRV_ISP_RIS_EXP_END_SHIFT 18U
/*! Slice: RIS_FLASH_CAP:*/
/*! Signaling captured frame */
#define MRV_ISP_RIS_FLASH_CAP
#define MRV_ISP_RIS_FLASH_CAP_MASK 0x00020000U
#define MRV_ISP_RIS_FLASH_CAP_SHIFT 17U
/*! Slice: RIS_RESERVED_1:*/
/*! reserved */
#define MRV_ISP_RIS_RESERVED_1
#define MRV_ISP_RIS_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_RIS_RESERVED_1_SHIFT 16U
/*! Slice: RIS_HIST_MEASURE_RDY:*/
/*! Histogram measurement ready. (old or new histogram measurement)*/
#define MRV_ISP_RIS_HIST_MEASURE_RDY
#define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0x00008000U
#define MRV_ISP_RIS_HIST_MEASURE_RDY_SHIFT 15U
/*! Slice: RIS_AFM_FIN:*/
/*! AF measurement finished: this interrupt is set when the first complete frame is calculated after enabling the AF measurement */
#define MRV_ISP_RIS_AFM_FIN
#define MRV_ISP_RIS_AFM_FIN_MASK 0x00004000U
#define MRV_ISP_RIS_AFM_FIN_SHIFT 14U
/*! Slice: RIS_AFM_LUM_OF:*/
/*! Auto focus luminance overflow */
#define MRV_ISP_RIS_AFM_LUM_OF
#define MRV_ISP_RIS_AFM_LUM_OF_MASK 0x00002000U
#define MRV_ISP_RIS_AFM_LUM_OF_SHIFT 13U
/*! Slice: RIS_AFM_SUM_OF:*/
/*! Auto focus sum overflow */
#define MRV_ISP_RIS_AFM_SUM_OF
#define MRV_ISP_RIS_AFM_SUM_OF_MASK 0x00001000U
#define MRV_ISP_RIS_AFM_SUM_OF_SHIFT 12U
/*! Slice: RIS_SHUTTER_OFF:*/
/*! Mechanical shutter is switched off */
#define MRV_ISP_RIS_SHUTTER_OFF
#define MRV_ISP_RIS_SHUTTER_OFF_MASK 0x00000800U
#define MRV_ISP_RIS_SHUTTER_OFF_SHIFT 11U
/*! Slice: RIS_SHUTTER_ON:*/
/*! Mechanical shutter is switched on */
#define MRV_ISP_RIS_SHUTTER_ON
#define MRV_ISP_RIS_SHUTTER_ON_MASK 0x00000400U
#define MRV_ISP_RIS_SHUTTER_ON_SHIFT 10U
/*! Slice: RIS_FLASH_OFF:*/
/*! Flash light is switched off */
#define MRV_ISP_RIS_FLASH_OFF
#define MRV_ISP_RIS_FLASH_OFF_MASK 0x00000200U
#define MRV_ISP_RIS_FLASH_OFF_SHIFT 9U
/*! Slice: RIS_FLASH_ON:*/
/*! Flash light is switched on */
#define MRV_ISP_RIS_FLASH_ON
#define MRV_ISP_RIS_FLASH_ON_MASK 0x00000100U
#define MRV_ISP_RIS_FLASH_ON_SHIFT 8U
/*! Slice: RIS_H_START:*/
/*! Start edge of h_sync */
#define MRV_ISP_RIS_H_START
#define MRV_ISP_RIS_H_START_MASK 0x00000080U
#define MRV_ISP_RIS_H_START_SHIFT 7U
/*! Slice: RIS_V_START:*/
/*! Start edge of v_sync */
#define MRV_ISP_RIS_V_START
#define MRV_ISP_RIS_V_START_MASK 0x00000040U
#define MRV_ISP_RIS_V_START_SHIFT 6U
/*! Slice: RIS_FRAME_IN:*/
/*! sampled input frame is complete */
#define MRV_ISP_RIS_FRAME_IN
#define MRV_ISP_RIS_FRAME_IN_MASK 0x00000020U
#define MRV_ISP_RIS_FRAME_IN_SHIFT 5U
/*! Slice: RIS_AWB_DONE:*/
/*! White balancing measurement cycle is complete, results can be read out */
#define MRV_ISP_RIS_AWB_DONE
#define MRV_ISP_RIS_AWB_DONE_MASK 0x00000010U
#define MRV_ISP_RIS_AWB_DONE_SHIFT 4U
/*! Slice: RIS_PIC_SIZE_ERR:*/
/*! pic size violation occurred, programming seems wrong */
#define MRV_ISP_RIS_PIC_SIZE_ERR
#define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0x00000008U
#define MRV_ISP_RIS_PIC_SIZE_ERR_SHIFT 3U
/*! Slice: RIS_DATA_LOSS:*/
/*! loss of data occurred within a line, processing failure */
#define MRV_ISP_RIS_DATA_LOSS
#define MRV_ISP_RIS_DATA_LOSS_MASK 0x00000004U
#define MRV_ISP_RIS_DATA_LOSS_SHIFT 2U
/*! Slice: RIS_FRAME:*/
/*! frame was completely put out */
#define MRV_ISP_RIS_FRAME
#define MRV_ISP_RIS_FRAME_MASK 0x00000002U
#define MRV_ISP_RIS_FRAME_SHIFT 1U
/*! Slice: RIS_ISP_OFF:*/
/*! isp output was disabled (vsynced) due to f_cnt reached or manual */
#define MRV_ISP_RIS_ISP_OFF
#define MRV_ISP_RIS_ISP_OFF_MASK 0x00000001U
#define MRV_ISP_RIS_ISP_OFF_SHIFT 0U
/*! Register: isp_mis: Masked interrupt status (0x000001c4)*/
/*! Slice: MIS_VSM_END:*/
/*! VSM measurement complete */
#define MRV_ISP_MIS_VSM_END
#define MRV_ISP_MIS_VSM_END_MASK 0x00080000U
#define MRV_ISP_MIS_VSM_END_SHIFT 19U
/*! Slice: MIS_EXP_END:*/
/*! Exposure measurement complete */
#define MRV_ISP_MIS_EXP_END
#define MRV_ISP_MIS_EXP_END_MASK 0x00040000U
#define MRV_ISP_MIS_EXP_END_SHIFT 18U
/*! Slice: MIS_FLASH_CAP:*/
/*! Captured is frame is detected */
#define MRV_ISP_MIS_FLASH_CAP
#define MRV_ISP_MIS_FLASH_CAP_MASK 0x00020000U
#define MRV_ISP_MIS_FLASH_CAP_SHIFT 17U
/*! Slice: MIS_RESERVED_1:*/
/*! reserved */
#define MRV_ISP_MIS_RESERVED_1
#define MRV_ISP_MIS_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_MIS_RESERVED_1_SHIFT 16U
/*! Slice: MIS_HIST_MEASURE_RDY:*/
/*! Histogram measurement ready. (old or new histogram measurement)*/
#define MRV_ISP_MIS_HIST_MEASURE_RDY
#define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0x00008000U
#define MRV_ISP_MIS_HIST_MEASURE_RDY_SHIFT 15U
/*! Slice: MIS_AFM_FIN:*/
/*! AF measurement finished: this interrupt is set when the first complete frame is calculated after enabling the AF measurement */
#define MRV_ISP_MIS_AFM_FIN
#define MRV_ISP_MIS_AFM_FIN_MASK 0x00004000U
#define MRV_ISP_MIS_AFM_FIN_SHIFT 14U
/*! Slice: MIS_AFM_LUM_OF:*/
/*! Luminance overflow */
#define MRV_ISP_MIS_AFM_LUM_OF
#define MRV_ISP_MIS_AFM_LUM_OF_MASK 0x00002000U
#define MRV_ISP_MIS_AFM_LUM_OF_SHIFT 13U
/*! Slice: MIS_AFM_SUM_OF:*/
/*! Sum overflow */
#define MRV_ISP_MIS_AFM_SUM_OF
#define MRV_ISP_MIS_AFM_SUM_OF_MASK 0x00001000U
#define MRV_ISP_MIS_AFM_SUM_OF_SHIFT 12U
/*! Slice: MIS_SHUTTER_OFF:*/
/*! Mechanical shutter is switched off */
#define MRV_ISP_MIS_SHUTTER_OFF
#define MRV_ISP_MIS_SHUTTER_OFF_MASK 0x00000800U
#define MRV_ISP_MIS_SHUTTER_OFF_SHIFT 11U
/*! Slice: MIS_SHUTTER_ON:*/
/*! Mechanical shutter is switched on */
#define MRV_ISP_MIS_SHUTTER_ON
#define MRV_ISP_MIS_SHUTTER_ON_MASK 0x00000400U
#define MRV_ISP_MIS_SHUTTER_ON_SHIFT 10U
/*! Slice: MIS_FLASH_OFF:*/
/*! Flash light is switched off */
#define MRV_ISP_MIS_FLASH_OFF
#define MRV_ISP_MIS_FLASH_OFF_MASK 0x00000200U
#define MRV_ISP_MIS_FLASH_OFF_SHIFT 9U
/*! Slice: MIS_FLASH_ON:*/
/*! Flash light is switched on */
#define MRV_ISP_MIS_FLASH_ON
#define MRV_ISP_MIS_FLASH_ON_MASK 0x00000100U
#define MRV_ISP_MIS_FLASH_ON_SHIFT 8U
/*! Slice: MIS_H_START:*/
/*! Start edge of h_sync */
#define MRV_ISP_MIS_H_START
#define MRV_ISP_MIS_H_START_MASK 0x00000080U
#define MRV_ISP_MIS_H_START_SHIFT 7U
/*! Slice: MIS_V_START:*/
/*! Start edge of v_sync */
#define MRV_ISP_MIS_V_START
#define MRV_ISP_MIS_V_START_MASK 0x00000040U
#define MRV_ISP_MIS_V_START_SHIFT 6U
/*! Slice: MIS_FRAME_IN:*/
/*! sampled input frame is complete */
#define MRV_ISP_MIS_FRAME_IN
#define MRV_ISP_MIS_FRAME_IN_MASK 0x00000020U
#define MRV_ISP_MIS_FRAME_IN_SHIFT 5U
/*! Slice: MIS_AWB_DONE:*/
/*! White balancing measurement cycle is complete, results can be read out */
#define MRV_ISP_MIS_AWB_DONE
#define MRV_ISP_MIS_AWB_DONE_MASK 0x00000010U
#define MRV_ISP_MIS_AWB_DONE_SHIFT 4U
/*! Slice: MIS_PIC_SIZE_ERR:*/
/*! pic size violation occurred, programming seems wrong */
#define MRV_ISP_MIS_PIC_SIZE_ERR
#define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0x00000008U
#define MRV_ISP_MIS_PIC_SIZE_ERR_SHIFT 3U
/*! Slice: MIS_DATA_LOSS:*/
/*! loss of data occurred within a line, processing failure */
#define MRV_ISP_MIS_DATA_LOSS
#define MRV_ISP_MIS_DATA_LOSS_MASK 0x00000004U
#define MRV_ISP_MIS_DATA_LOSS_SHIFT 2U
/*! Slice: MIS_FRAME:*/
/*! frame was completely put out */
#define MRV_ISP_MIS_FRAME
#define MRV_ISP_MIS_FRAME_MASK 0x00000002U
#define MRV_ISP_MIS_FRAME_SHIFT 1U
/*! Slice: MIS_ISP_OFF:*/
/*! isp was turned off (vsynced) due to f_cnt reached or manual */
#define MRV_ISP_MIS_ISP_OFF
#define MRV_ISP_MIS_ISP_OFF_MASK 0x00000001U
#define MRV_ISP_MIS_ISP_OFF_SHIFT 0U
/*! Register: isp_icr: Interrupt clear register (0x000001c8)*/
/*! Slice: ICR_VSM_END:*/
/*! clear interrupt */
#define MRV_ISP_ICR_VSM_END
#define MRV_ISP_ICR_VSM_END_MASK 0x00080000U
#define MRV_ISP_ICR_VSM_END_SHIFT 19U
/*! Slice: ICR_EXP_END:*/
/*! clear interrupt */
#define MRV_ISP_ICR_EXP_END
#define MRV_ISP_ICR_EXP_END_MASK 0x00040000U
#define MRV_ISP_ICR_EXP_END_SHIFT 18U
/*! Slice: ICR_FLASH_CAP:*/
/*! clear interrupt */
#define MRV_ISP_ICR_FLASH_CAP
#define MRV_ISP_ICR_FLASH_CAP_MASK 0x00020000U
#define MRV_ISP_ICR_FLASH_CAP_SHIFT 17U
/*! Slice: ICR_RESERVED_1:*/
/*! clear interrupt */
#define MRV_ISP_ICR_RESERVED_1
#define MRV_ISP_ICR_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_ICR_RESERVED_1_SHIFT 16U
/*! Slice: ICR_HIST_MEASURE_RDY:*/
/*! clear interrupt */
#define MRV_ISP_ICR_HIST_MEASURE_RDY
#define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0x00008000U
#define MRV_ISP_ICR_HIST_MEASURE_RDY_SHIFT 15U
/*! Slice: ICR_AFM_FIN:*/
/*! clear interrupt */
#define MRV_ISP_ICR_AFM_FIN
#define MRV_ISP_ICR_AFM_FIN_MASK 0x00004000U
#define MRV_ISP_ICR_AFM_FIN_SHIFT 14U
/*! Slice: ICR_AFM_LUM_OF:*/
/*! clear interrupt */
#define MRV_ISP_ICR_AFM_LUM_OF
#define MRV_ISP_ICR_AFM_LUM_OF_MASK 0x00002000U
#define MRV_ISP_ICR_AFM_LUM_OF_SHIFT 13U
/*! Slice: ICR_AFM_SUM_OF:*/
/*! clear interrupt */
#define MRV_ISP_ICR_AFM_SUM_OF
#define MRV_ISP_ICR_AFM_SUM_OF_MASK 0x00001000U
#define MRV_ISP_ICR_AFM_SUM_OF_SHIFT 12U
/*! Slice: ICR_SHUTTER_OFF:*/
/*! clear interrupt */
#define MRV_ISP_ICR_SHUTTER_OFF
#define MRV_ISP_ICR_SHUTTER_OFF_MASK 0x00000800U
#define MRV_ISP_ICR_SHUTTER_OFF_SHIFT 11U
/*! Slice: ICR_SHUTTER_ON:*/
/*! clear interrupt */
#define MRV_ISP_ICR_SHUTTER_ON
#define MRV_ISP_ICR_SHUTTER_ON_MASK 0x00000400U
#define MRV_ISP_ICR_SHUTTER_ON_SHIFT 10U
/*! Slice: ICR_FLASH_OFF:*/
/*! clear interrupt */
#define MRV_ISP_ICR_FLASH_OFF
#define MRV_ISP_ICR_FLASH_OFF_MASK 0x00000200U
#define MRV_ISP_ICR_FLASH_OFF_SHIFT 9U
/*! Slice: ICR_FLASH_ON:*/
/*! clear interrupt */
#define MRV_ISP_ICR_FLASH_ON
#define MRV_ISP_ICR_FLASH_ON_MASK 0x00000100U
#define MRV_ISP_ICR_FLASH_ON_SHIFT 8U
/*! Slice: ICR_H_START:*/
/*! clear interrupt */
#define MRV_ISP_ICR_H_START
#define MRV_ISP_ICR_H_START_MASK 0x00000080U
#define MRV_ISP_ICR_H_START_SHIFT 7U
/*! Slice: ICR_V_START:*/
/*! clear interrupt */
#define MRV_ISP_ICR_V_START
#define MRV_ISP_ICR_V_START_MASK 0x00000040U
#define MRV_ISP_ICR_V_START_SHIFT 6U
/*! Slice: ICR_FRAME_IN:*/
/*! clear interrupt */
#define MRV_ISP_ICR_FRAME_IN
#define MRV_ISP_ICR_FRAME_IN_MASK 0x00000020U
#define MRV_ISP_ICR_FRAME_IN_SHIFT 5U
/*! Slice: ICR_AWB_DONE:*/
/*! clear interrupt */
#define MRV_ISP_ICR_AWB_DONE
#define MRV_ISP_ICR_AWB_DONE_MASK 0x00000010U
#define MRV_ISP_ICR_AWB_DONE_SHIFT 4U
/*! Slice: ICR_PIC_SIZE_ERR:*/
/*! clear interrupt */
#define MRV_ISP_ICR_PIC_SIZE_ERR
#define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0x00000008U
#define MRV_ISP_ICR_PIC_SIZE_ERR_SHIFT 3U
/*! Slice: ICR_DATA_LOSS:*/
/*! clear interrupt */
#define MRV_ISP_ICR_DATA_LOSS
#define MRV_ISP_ICR_DATA_LOSS_MASK 0x00000004U
#define MRV_ISP_ICR_DATA_LOSS_SHIFT 2U
/*! Slice: ICR_FRAME:*/
/*! clear interrupt */
#define MRV_ISP_ICR_FRAME
#define MRV_ISP_ICR_FRAME_MASK 0x00000002U
#define MRV_ISP_ICR_FRAME_SHIFT 1U
/*! Slice: ICR_ISP_OFF:*/
/*! clear interrupt */
#define MRV_ISP_ICR_ISP_OFF
#define MRV_ISP_ICR_ISP_OFF_MASK 0x00000001U
#define MRV_ISP_ICR_ISP_OFF_SHIFT 0U
/*! Register: isp_isr: Interrupt set register (0x000001cc)*/
/*! Slice: ISR_VSM_END:*/
/*! set interrupt */
#define MRV_ISP_ISR_VSM_END
#define MRV_ISP_ISR_VSM_END_MASK 0x00080000U
#define MRV_ISP_ISR_VSM_END_SHIFT 19U
/*! Slice: ISR_EXP_END:*/
/*! set interrupt */
#define MRV_ISP_ISR_EXP_END
#define MRV_ISP_ISR_EXP_END_MASK 0x00040000U
#define MRV_ISP_ISR_EXP_END_SHIFT 18U
/*! Slice: ISR_FLASH_CAP:*/
/*! set interrupt */
#define MRV_ISP_ISR_FLASH_CAP
#define MRV_ISP_ISR_FLASH_CAP_MASK 0x00020000U
#define MRV_ISP_ISR_FLASH_CAP_SHIFT 17U
/*! Slice: ISR_RESERVED_1:*/
/*! set interrupt */
#define MRV_ISP_ISR_RESERVED_1
#define MRV_ISP_ISR_RESERVED_1_MASK 0x00010000U
#define MRV_ISP_ISR_RESERVED_1_SHIFT 16U
/*! Slice: ISR_HIST_MEASURE_RDY:*/
/*! set interrupt */
#define MRV_ISP_ISR_HIST_MEASURE_RDY
#define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0x00008000U
#define MRV_ISP_ISR_HIST_MEASURE_RDY_SHIFT 15U
/*! Slice: ISR_AFM_FIN:*/
/*! set interrupt */
#define MRV_ISP_ISR_AFM_FIN
#define MRV_ISP_ISR_AFM_FIN_MASK 0x00004000U
#define MRV_ISP_ISR_AFM_FIN_SHIFT 14U
/*! Slice: ISR_AFM_LUM_OF:*/
/*! set interrupt */
#define MRV_ISP_ISR_AFM_LUM_OF
#define MRV_ISP_ISR_AFM_LUM_OF_MASK 0x00002000U
#define MRV_ISP_ISR_AFM_LUM_OF_SHIFT 13U
/*! Slice: ISR_AFM_SUM_OF:*/
/*! set interrupt */
#define MRV_ISP_ISR_AFM_SUM_OF
#define MRV_ISP_ISR_AFM_SUM_OF_MASK 0x00001000U
#define MRV_ISP_ISR_AFM_SUM_OF_SHIFT 12U
/*! Slice: ISR_SHUTTER_OFF:*/
/*! set interrupt */
#define MRV_ISP_ISR_SHUTTER_OFF
#define MRV_ISP_ISR_SHUTTER_OFF_MASK 0x00000800U
#define MRV_ISP_ISR_SHUTTER_OFF_SHIFT 11U
/*! Slice: ISR_SHUTTER_ON:*/
/*! set interrupt */
#define MRV_ISP_ISR_SHUTTER_ON
#define MRV_ISP_ISR_SHUTTER_ON_MASK 0x00000400U
#define MRV_ISP_ISR_SHUTTER_ON_SHIFT 10U
/*! Slice: ISR_FLASH_OFF:*/
/*! set interrupt */
#define MRV_ISP_ISR_FLASH_OFF
#define MRV_ISP_ISR_FLASH_OFF_MASK 0x00000200U
#define MRV_ISP_ISR_FLASH_OFF_SHIFT 9U
/*! Slice: ISR_FLASH_ON:*/
/*! set interrupt */
#define MRV_ISP_ISR_FLASH_ON
#define MRV_ISP_ISR_FLASH_ON_MASK 0x00000100U
#define MRV_ISP_ISR_FLASH_ON_SHIFT 8U
/*! Slice: ISR_H_START:*/
/*! set interrupt */
#define MRV_ISP_ISR_H_START
#define MRV_ISP_ISR_H_START_MASK 0x00000080U
#define MRV_ISP_ISR_H_START_SHIFT 7U
/*! Slice: ISR_V_START:*/
/*! set interrupt */
#define MRV_ISP_ISR_V_START
#define MRV_ISP_ISR_V_START_MASK 0x00000040U
#define MRV_ISP_ISR_V_START_SHIFT 6U
/*! Slice: ISR_FRAME_IN:*/
/*! set interrupt */
#define MRV_ISP_ISR_FRAME_IN
#define MRV_ISP_ISR_FRAME_IN_MASK 0x00000020U
#define MRV_ISP_ISR_FRAME_IN_SHIFT 5U
/*! Slice: ISR_AWB_DONE:*/
/*! set interrupt */
#define MRV_ISP_ISR_AWB_DONE
#define MRV_ISP_ISR_AWB_DONE_MASK 0x00000010U
#define MRV_ISP_ISR_AWB_DONE_SHIFT 4U
/*! Slice: ISR_PIC_SIZE_ERR:*/
/*! set interrupt */
#define MRV_ISP_ISR_PIC_SIZE_ERR
#define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0x00000008U
#define MRV_ISP_ISR_PIC_SIZE_ERR_SHIFT 3U
/*! Slice: ISR_DATA_LOSS:*/
/*! set interrupt */
#define MRV_ISP_ISR_DATA_LOSS
#define MRV_ISP_ISR_DATA_LOSS_MASK 0x00000004U
#define MRV_ISP_ISR_DATA_LOSS_SHIFT 2U
/*! Slice: ISR_FRAME:*/
/*! set interrupt */
#define MRV_ISP_ISR_FRAME
#define MRV_ISP_ISR_FRAME_MASK 0x00000002U
#define MRV_ISP_ISR_FRAME_SHIFT 1U
/*! Slice: ISR_ISP_OFF:*/
/*! set interrupt */
#define MRV_ISP_ISR_ISP_OFF
#define MRV_ISP_ISR_ISP_OFF_MASK 0x00000001U
#define MRV_ISP_ISR_ISP_OFF_SHIFT 0U

#ifdef  ISP_CTM_0507                     // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF). 
/*! Register array: isp_ct_coeff: cross-talk configuration register (color correction matrix) (0x03A0 + n*0x4 (n=0..8))*/
/*! Slice: ct_coeff:*/
/* Coefficient n for cross talk matrix.*/
     /**/
/* Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part,*/
/* ranging from -16 (0x800) to +15.992 (0x7FF). */
#define MRV_ISP_CT_COEFF
#define MRV_ISP_CT_COEFF_MASK 0x00000FFFU
#define MRV_ISP_CT_COEFF_SHIFT 0U

#else                              // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF). 
/*! Register array: isp_ct_coeff: cross-talk configuration register (color correction matrix) (0x03A0 + n*0x4 (n=0..8))*/
/*! Slice: ct_coeff:*/
/* Coefficient n for cross talk matrix.*/
     /**/
/* Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part,*/
/* ranging from -8 (0x400) to +7.992 (0x3FF). 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/
#define MRV_ISP_CT_COEFF
#define MRV_ISP_CT_COEFF_MASK 0x000007FFU
#define MRV_ISP_CT_COEFF_SHIFT 0U
#endif //CTM_0507
/*! Register: isp_gamma_out_mode: gamma segmentation mode register for output gamma (0x000001f4)*/
/*! Slice: equ_segm:*/
/*! 0: logarithmic like segmentation of gamma curve (default after reset)*/
/*   segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */
/* 1: equidistant segmentation (all 16 segments are 256 )*/
#define MRV_ISP_EQU_SEGM
#define MRV_ISP_EQU_SEGM_MASK 0x00000001U
#define MRV_ISP_EQU_SEGM_SHIFT 0U
/*! Register array: isp_gamma_out_y: Gamma Out Curve definition y_ (0x03F0 + n*0x4 (n=0..16))*/
/*! Slice: isp_gamma_out_y:*/
/* Gamma_out curve point definition y-axis (output) for all color components (red,green,blue)*/
/* RESTRICTION: The difference between two Y_n (dy = Y_n - Y_n-1) is restricted to +511/-512 (10 bit signed)!*/
#define MRV_ISP_ISP_GAMMA_OUT_Y
#define MRV_ISP_ISP_GAMMA_OUT_Y_MASK 0x000003FFU
#define MRV_ISP_ISP_GAMMA_OUT_Y_SHIFT 0U
/*! Register: isp_err: ISP error register (0x0000023c)*/
/*! Slice: outform_size_err:*/
/*! size error is generated in outmux submodule */
#define MRV_ISP_OUTFORM_SIZE_ERR
#define MRV_ISP_OUTFORM_SIZE_ERR_MASK 0x00000004U
#define MRV_ISP_OUTFORM_SIZE_ERR_SHIFT 2U
/*! Slice: is_size_err:*/
/*! size error is generated in image stabilization submodule */
#define MRV_ISP_IS_SIZE_ERR
#define MRV_ISP_IS_SIZE_ERR_MASK 0x00000002U
#define MRV_ISP_IS_SIZE_ERR_SHIFT 1U
#ifdef ISP_RAWIS
/*! Register: isp_raw_is_ctrl: Raw Image Stabilization Control Register (0x00000000)*/
/*! Slice: is_en:*/
/*! 1: image stabilization switched on */
/* 0: image stabilization switched off */
#define MRV_ISP_RAW_IS_EN
#define MRV_ISP_RAW_IS_EN_MASK 0x00000001U
#define MRV_ISP_RAW_IS_EN_SHIFT 0U
/*! Register: isp_raw_is_recenter: Recenter register (0x00000004)*/
/*! Slice: is_recenter:*/
/*! 000: recenter feature switched off */
/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
#define MRV_ISP_RAW_IS_RECENTER
#define MRV_ISP_RAW_IS_RECENTER_MASK 0x00000007U
#define MRV_ISP_RAW_IS_RECENTER_SHIFT 0U
/*! Register: isp_raw_is_h_offs: Horizontal offset of output window (0x00000008)*/
/*! Slice: is_h_offs:*/
/*! horizontal picture offset in pixel */
#define MRV_ISP_RAW_IS_H_OFFS
#define MRV_ISP_RAW_IS_H_OFFS_MASK 0x00001FFFU
#define MRV_ISP_RAW_IS_H_OFFS_SHIFT 0U
/*! Register: isp_raw_is_v_offs: Vertical offset of output window (0x0000000c)*/
/*! Slice: is_v_offs:*/
/*! vertical picture offset in lines */
#define MRV_ISP_RAW_IS_V_OFFS
#define MRV_ISP_RAW_IS_V_OFFS_MASK 0x00000FFFU
#define MRV_ISP_RAW_IS_V_OFFS_SHIFT 0U
/*! Register: isp_raw_is_h_size: Output horizontal picture size (0x00000010)*/
/*! Slice: is_h_size:*/
/*! horizontal picture size in pixel */
/* if ISP_MODE is set to */
/* 001-(ITU-R BT.656 YUV),*/
/* 010-( ITU-R BT.601 YUV),*/
/* 011-( ITU-R BT.601 Bayer RGB),*/
/* 101-( ITU-R BT.656 Bayer RGB)*/
/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/
#define MRV_ISP_RAW_IS_H_SIZE
#define MRV_ISP_RAW_IS_H_SIZE_MASK 0x00001FFFU
#define MRV_ISP_RAW_IS_H_SIZE_SHIFT 0U
/*! Register: isp_raw_is_v_size: Output vertical picture size (0x00000014)*/
/*! Slice: is_v_size:*/
/*! vertical picture size in lines */
#define MRV_ISP_RAW_IS_V_SIZE
#define MRV_ISP_RAW_IS_V_SIZE_MASK 0x00000FFFU
#define MRV_ISP_RAW_IS_V_SIZE_SHIFT 0U
/*! Register: isp_raw_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/
/*! Slice: is_max_dx:*/
/*! maximum allowed accumulated horizontal displacement in pixels */
#define MRV_ISP_RAW_IS_MAX_DX
#define MRV_ISP_RAW_IS_MAX_DX_MASK 0x00000FFFU
#define MRV_ISP_RAW_IS_MAX_DX_SHIFT 0U
/*! Register: isp_raw_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/
/*! Slice: is_max_dy:*/
/*! maximum allowed accumulated vertical displacement in lines */
#define MRV_ISP_RAW_IS_MAX_DY
#define MRV_ISP_RAW_IS_MAX_DY_MASK 0x00000FFFU
#define MRV_ISP_RAW_IS_MAX_DY_SHIFT 0U
/*! Register: isp_raw_is_displace: Camera displacement (0x00000020)*/
/*! Slice: dy:*/
/*! ISP_RAW_IS will compensate for vertical camera displacement of DY lines in the next frame */
#define MRV_ISP_RAW_IS_DY
#define MRV_ISP_RAW_IS_DY_MASK 0x0FFF0000U
#define MRV_ISP_RAW_IS_DY_SHIFT 16U
/*! Slice: dx:*/
/*! ISP_RAW_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
#define MRV_ISP_RAW_IS_DX
#define MRV_ISP_RAW_IS_DX_MASK 0x00000FFFU
#define MRV_ISP_RAW_IS_DX_SHIFT 0U
#endif
/*! Slice: inform_size_err:*/
/*! size error is generated in inform submodule */
#define MRV_ISP_INFORM_SIZE_ERR
#define MRV_ISP_INFORM_SIZE_ERR_MASK 0x00000001U
#define MRV_ISP_INFORM_SIZE_ERR_SHIFT 0U
/*! Register: isp_err_clr: ISP error clear register (0x00000240)*/
/*! Slice: outform_size_err_clr:*/
/*! size error is cleared */
#define MRV_ISP_OUTFORM_SIZE_ERR_CLR
#define MRV_ISP_OUTFORM_SIZE_ERR_CLR_MASK 0x00000004U
#define MRV_ISP_OUTFORM_SIZE_ERR_CLR_SHIFT 2U
/*! Slice: is_size_err_clr:*/
/*! size error is cleared */
#define MRV_ISP_IS_SIZE_ERR_CLR
#define MRV_ISP_IS_SIZE_ERR_CLR_MASK 0x00000002U
#define MRV_ISP_IS_SIZE_ERR_CLR_SHIFT 1U
/*! Slice: inform_size_err_clr:*/
/*! size error is cleared */
#define MRV_ISP_INFORM_SIZE_ERR_CLR
#define MRV_ISP_INFORM_SIZE_ERR_CLR_MASK 0x00000001U
#define MRV_ISP_INFORM_SIZE_ERR_CLR_SHIFT 0U
/*! Register: isp_frame_count: Frame counter (0x00000244)*/
/*! Slice: frame_counter:*/
/*! Current frame count of processing */
#define MRV_ISP_FRAME_COUNTER
#define MRV_ISP_FRAME_COUNTER_MASK 0x000003FFU
#define MRV_ISP_FRAME_COUNTER_SHIFT 0U
/*! Register: isp_ct_offset_r: cross-talk offset red (0x00000248)*/
/*! Slice: ct_offset_r:*/
/*! Offset red for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
#define MRV_ISP_CT_OFFSET_R
#define MRV_ISP_CT_OFFSET_R_MASK 0x00000FFFU
#define MRV_ISP_CT_OFFSET_R_SHIFT 0U
/*! Register: isp_ct_offset_g: cross-talk offset green (0x0000024c)*/
/*! Slice: ct_offset_g:*/
/*! Offset green for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
#define MRV_ISP_CT_OFFSET_G
#define MRV_ISP_CT_OFFSET_G_MASK 0x00000FFFU
#define MRV_ISP_CT_OFFSET_G_SHIFT 0U
/*! Register: isp_ct_offset_b: cross-talk offset blue (0x00000250)*/
/*! Slice: ct_offset_b:*/
/*! Offset blue for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
#define MRV_ISP_CT_OFFSET_B
#define MRV_ISP_CT_OFFSET_B_MASK 0x00000FFFU
#define MRV_ISP_CT_OFFSET_B_SHIFT 0U
/*! Register: isp_cnr_linesize: chroma noise reduction line size (0x00000254)*/
/*! Slice: cnr_linesize:*/
/*! horizontal image size for chroma noise reduction */
#define MRV_ISP_CNR_LINESIZE
#define MRV_ISP_CNR_LINESIZE_MASK 0x00003FFFU
#define MRV_ISP_CNR_LINESIZE_SHIFT 0U
/*! Register: isp_cnr_threshold_c1: chroma noise reduction C1 Threshold (0x00000258)*/
/*! Slice: cnr_threshold_c1:*/
/*! Avoid filtering at edges for C1 by using low threshold values for C1 chroma noise filtering.*/
/* 0: No filtering */
/* 32767: all samples are filtered.*/
#define MRV_ISP_CNR_THRESHOLD_C1
#define MRV_ISP_CNR_THRESHOLD_C1_MASK 0x00007FFFU
#define MRV_ISP_CNR_THRESHOLD_C1_SHIFT 0U
/*! Register: isp_cnr_threshold_c2: chroma noise reduction C2 Threshold (0x0000025c)*/
/*! Slice: cnr_threshold_c2:*/
/*! Avoid filtering at edges for C2 by using low threshold values for C2 chroma noise filtering.*/
/* 0: No filtering */
/* 32767: all samples are filtered.*/
#define MRV_ISP_CNR_THRESHOLD_C2
#define MRV_ISP_CNR_THRESHOLD_C2_MASK 0x00007FFFU
#define MRV_ISP_CNR_THRESHOLD_C2_SHIFT 0U
/*! Register: isp_flash_cmd: Flash command (0x00000000)*/
/*! Slice: preflash_on:*/
/*! preflash on */
/* 0: no effect */
/* 1: flash delay counter is started at next trigger event */
/* No capture event is signaled to the sensor interface block.*/
#define MRV_FLASH_PREFLASH_ON
#define MRV_FLASH_PREFLASH_ON_MASK 0x00000004U
#define MRV_FLASH_PREFLASH_ON_SHIFT 2U
/*! Slice: flash_on:*/
/*! flash on */
/* 0: no effect */
/* 1: flash delay counter is started at next trigger event */
/* A capture event is signaled to the sensor interface block.*/
#define MRV_FLASH_FLASH_ON
#define MRV_FLASH_FLASH_ON_MASK 0x00000002U
#define MRV_FLASH_FLASH_ON_SHIFT 1U
/*! Slice: prelight_on:*/
/*! prelight on */
/* 0: prelight is switched off at next trigger event */
/* 1: prelight is switched on at next trigger event */
#define MRV_FLASH_PRELIGHT_ON
#define MRV_FLASH_PRELIGHT_ON_MASK 0x00000001U
#define MRV_FLASH_PRELIGHT_ON_SHIFT 0U
/*! Register: isp_flash_config: Flash config (0x00000004)*/
/*! Slice: fl_cap_del:*/
/*! capture delay */
/* frame number (0 to 15) to be captured after trigger event */
#define MRV_FLASH_FL_CAP_DEL
#define MRV_FLASH_FL_CAP_DEL_MASK 0x000000F0U
#define MRV_FLASH_FL_CAP_DEL_SHIFT 4U
/*! Slice: fl_trig_src:*/
/*! trigger source for flash and prelight */
/* 0: use vds_vsync for trigger event (with evaluation of vs_in_edge)*/
/* 1: use fl_trig for trigger event (positive edge)*/
#define MRV_FLASH_FL_TRIG_SRC
#define MRV_FLASH_FL_TRIG_SRC_MASK 0x00000008U
#define MRV_FLASH_FL_TRIG_SRC_SHIFT 3U
/*! Slice: fl_pol:*/
/*! polarity of flash related signals */
/* 0: flash_trig, prelight_trig are high active */
/* 1: flash_trig, prelight_trig are low active */
#define MRV_FLASH_FL_POL
#define MRV_FLASH_FL_POL_MASK 0x00000004U
#define MRV_FLASH_FL_POL_SHIFT 2U
/*! Slice: vs_in_edge:*/
/*! VSYNC edge */
/* 0: use negative edge of vds_vsync if generating a trigger event */
/* 1: use positive edge of vds_vsync if generating a trigger event */
#define MRV_FLASH_VS_IN_EDGE
#define MRV_FLASH_VS_IN_EDGE_MASK 0x00000002U
#define MRV_FLASH_VS_IN_EDGE_SHIFT 1U
/*! Slice: prelight_mode:*/
/*! prelight mode */
/* 0: prelight is switched off at begin of flash */
/* 1: prelight is switched off at end of flash */
#define MRV_FLASH_PRELIGHT_MODE
#define MRV_FLASH_PRELIGHT_MODE_MASK 0x00000001U
#define MRV_FLASH_PRELIGHT_MODE_SHIFT 0U
/*! Register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008)*/
/*! Slice: fl_pre_div:*/
/*! pre-divider for flush/preflash counter */
#define MRV_FLASH_FL_PRE_DIV
#define MRV_FLASH_FL_PRE_DIV_MASK 0x000003FFU
#define MRV_FLASH_FL_PRE_DIV_SHIFT 0U
/*! Register: isp_flash_delay: Flash Delay (0x0000000c)*/
/*! Slice: fl_delay:*/
/*! counter value for flash/preflash delay */
/* open_delay =  (fl_delay + 1) * (fl_pre_div+1) / clk_isp */
/* fl_delay =  (open_delay * clk_isp) / (fl_pre_div+1) - 1 */
#define MRV_FLASH_FL_DELAY
#define MRV_FLASH_FL_DELAY_MASK 0x0003FFFFU
#define MRV_FLASH_FL_DELAY_SHIFT 0U
/*! Register: isp_flash_time: Flash time (0x00000010)*/
/*! Slice: fl_time:*/
/*! counter value for flash/preflash time */
/* open_time =  (fl_time + 1) * (fl_pre_div+1) / clk_isp */
/* fl_time =  (open_time * clk_isp) / (fl_pre_div+1) - 1 */
#define MRV_FLASH_FL_TIME
#define MRV_FLASH_FL_TIME_MASK 0x0003FFFFU
#define MRV_FLASH_FL_TIME_SHIFT 0U
/*! Register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014)*/
/*! Slice: fl_maxp:*/
/*! maximum period value for flash or preflash */
/* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */
/* fl_maxp =  (max_period * clk_isp) / 214  - 1 */
#define MRV_FLASH_FL_MAXP
#define MRV_FLASH_FL_MAXP_MASK 0x0000FFFFU
#define MRV_FLASH_FL_MAXP_SHIFT 0U
/*! Register: isp_sh_ctrl: mechanical shutter control (0x00000000)*/
/*! Slice: sh_open_pol:*/
/*! shutter_open polarity */
/* 0: shutter_open is high active */
/* 1: shutter_open is low active */
#define MRV_SHUT_SH_OPEN_POL
#define MRV_SHUT_SH_OPEN_POL_MASK 0x00000010U
#define MRV_SHUT_SH_OPEN_POL_SHIFT 4U
/*! Slice: sh_trig_en:*/
/*! mechanical shutter trigger edge */
/* 0: use negative edge of trigger signal */
/* 1: use positive edge of trigger signal */
#define MRV_SHUT_SH_TRIG_EN
#define MRV_SHUT_SH_TRIG_EN_MASK 0x00000008U
#define MRV_SHUT_SH_TRIG_EN_SHIFT 3U
/*! Slice: sh_trig_src:*/
/*! mechanical shutter trigger source */
/* 0: use vds_vsync for trigger event */
/* 1: use shutter_trig for trigger event */
#define MRV_SHUT_SH_TRIG_SRC
#define MRV_SHUT_SH_TRIG_SRC_MASK 0x00000004U
#define MRV_SHUT_SH_TRIG_SRC_SHIFT 2U
/*! Slice: sh_rep_en:*/
/*! mechanical shutter repetition enable */
/* 0: shutter is opened only once */
/* 1: shutter is opened with the repetition rate of the trigger signal */
#define MRV_SHUT_SH_REP_EN
#define MRV_SHUT_SH_REP_EN_MASK 0x00000002U
#define MRV_SHUT_SH_REP_EN_SHIFT 1U
/*! Slice: sh_en:*/
/*! mechanical shutter enable */
/* 0: mechanical shutter function is disabled */
/* 1: mechanical shutter function is enabled */
#define MRV_SHUT_SH_EN
#define MRV_SHUT_SH_EN_MASK 0x00000001U
#define MRV_SHUT_SH_EN_SHIFT 0U
/*! Register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x00000004)*/
/*! Slice: sh_pre_div:*/
/*! pre-divider for mechanical shutter open_delay and open_time counter */
#define MRV_SHUT_SH_PRE_DIV
#define MRV_SHUT_SH_PRE_DIV_MASK 0x000003FFU
#define MRV_SHUT_SH_PRE_DIV_SHIFT 0U
/*! Register: isp_sh_delay: Delay register (0x00000008)*/
/*! Slice: sh_delay:*/
/*! counter value for delay */
/* open_delay =  (sh_delay + 1) * (fl_pre_div+1) / clk_isp */
/* sh_delay =  (open_delay * clk_isp) / (sh_pre_div+1)  1 */
#define MRV_SHUT_SH_DELAY
#define MRV_SHUT_SH_DELAY_MASK 0x000FFFFFU
#define MRV_SHUT_SH_DELAY_SHIFT 0U
/*! Register: isp_sh_time: Time register (0x0000000c)*/
/*! Slice: sh_time:*/
/*! counter value for time */
/* open_time =  (sh_time + 1) * (fl_pre_div+1) / clk_isp */
/* sh_time =  (open_time * clk_isp) / (sh_pre_div+1) - 1 */
#define MRV_SHUT_SH_TIME
#define MRV_SHUT_SH_TIME_MASK 0x000FFFFFU
#define MRV_SHUT_SH_TIME_SHIFT 0U
/*! Register: cproc_ctrl: Global control register (0x00000000)*/
/*! Slice: cproc_c_out_range:*/
/*! Color processing chrominance pixel clipping range at output */
/* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
/* 1: full UV_out clipping range 0..255 */
#define MRV_CPROC_CPROC_C_OUT_RANGE
#define MRV_CPROC_CPROC_C_OUT_RANGE_MASK 0x00000008U
#define MRV_CPROC_CPROC_C_OUT_RANGE_SHIFT 3U
/*! Slice: cproc_y_in_range:*/
/*! Color processing luminance input range (offset processing)*/
/* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/
/* offset of 64 will be subtracted from Y_in */
/* 1: Y_in full range 0..1023;  no offset will be subtracted from Y_in */
#define MRV_CPROC_CPROC_Y_IN_RANGE
#define MRV_CPROC_CPROC_Y_IN_RANGE_MASK 0x00000004U
#define MRV_CPROC_CPROC_Y_IN_RANGE_SHIFT 2U
/*! Slice: cproc_y_out_range:*/
/*! Color processing luminance output clipping range */
/* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
/* 1: Y_out clipping range 0..255; no offset is added to Y_out */
#define MRV_CPROC_CPROC_Y_OUT_RANGE
#define MRV_CPROC_CPROC_Y_OUT_RANGE_MASK 0x00000002U
#define MRV_CPROC_CPROC_Y_OUT_RANGE_SHIFT 1U
/*! Slice: cproc_enable:*/
/*! color processing enable */
/* 0: color processing is bypassed */
/* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */
/* 1: color processing is active */
/* output data are rounded to 2 * 8Bit and clipping is active */
#define MRV_CPROC_CPROC_ENABLE
#define MRV_CPROC_CPROC_ENABLE_MASK 0x00000001U
#define MRV_CPROC_CPROC_ENABLE_SHIFT 0U
/*! Register: cproc_contrast: Color Processing contrast register (0x00000004)*/
/*! Slice: cproc_contrast:*/
/*! contrast adjustment value */
/* 00H equals x 0.0 */
/* */
/* 80H equals x 1.0 */
/* */
/* FFH equals x 1.992 */
#define MRV_CPROC_CPROC_CONTRAST
#define MRV_CPROC_CPROC_CONTRAST_MASK 0x000000FFU
#define MRV_CPROC_CPROC_CONTRAST_SHIFT 0U
/*! Register: cproc_brightness: Color Processing brightness register (0x00000008)*/
/*! Slice: cproc_brightness:*/
/*! brightness adjustment value */
/* 80H equals -128 */
/* */
/* 00H equals +0 */
/* */
/* 7FH equals +127 */
#define MRV_CPROC_CPROC_BRIGHTNESS
#define MRV_CPROC_CPROC_BRIGHTNESS_MASK 0x000000FFU
#define MRV_CPROC_CPROC_BRIGHTNESS_SHIFT 0U
/*! Register: cproc_saturation: Color Processing saturation register (0x0000000c)*/
/*! Slice: cproc_saturation:*/
/*! saturation adjustment value */
/* 00H equals x 0.0 */
/* */
/* 80H equals x 1.0 */
/* */
/* FFH equals x 1.992 */
#define MRV_CPROC_CPROC_SATURATION
#define MRV_CPROC_CPROC_SATURATION_MASK 0x000000FFU
#define MRV_CPROC_CPROC_SATURATION_SHIFT 0U
/*! Register: cproc_hue: Color Processing hue register (0x00000010)*/
/*! Slice: cproc_hue:*/
/*! hue adjustment value */
/* 80H equals -90 deg */
/* */
/* 00H equals 0 deg */
/* */
/* 7FH equals +87.188 deg */
#define MRV_CPROC_CPROC_HUE
#define MRV_CPROC_CPROC_HUE_MASK 0x000000FFU
#define MRV_CPROC_CPROC_HUE_SHIFT 0U
#ifdef ISP8000NANO_BASE
/*! Register: mrsz_ctrl: global control register (0x00000000)*/
/*! Slice: auto_upd:*/
/*! 1: automatic register update at frame end enabled.*/
/* 0: automatic register update at frame end disabled.*/
#define MRV_MRSZ_AUTO_UPD
#define MRV_MRSZ_AUTO_UPD_MASK 0x00000200U
#define MRV_MRSZ_AUTO_UPD_SHIFT 9U
/*! Slice: cfg_upd:*/
/*! write 0: nothing happens */
/* write 1: update shadow registers */
/* read: always 0 */
#define MRV_MRSZ_CFG_UPD
#define MRV_MRSZ_CFG_UPD_MASK 0x00000100U
#define MRV_MRSZ_CFG_UPD_SHIFT 8U
#else
/*! Register: mrsz_ctrl: global control register (0x00000000)*/
/*! Slice: auto_upd:*/
/*! 1: automatic register update at frame end enabled.*/
/* 0: automatic register update at frame end disabled.*/
#define MRV_MRSZ_AUTO_UPD
#define MRV_MRSZ_AUTO_UPD_MASK 0x00000400U
#define MRV_MRSZ_AUTO_UPD_SHIFT 10U
/*! Slice: cfg_upd:*/
/*! write 0: nothing happens */
/* write 1: update shadow registers */
/* read: always 0 */
#define MRV_MRSZ_CFG_UPD
#define MRV_MRSZ_CFG_UPD_MASK 0x00000200U
#define MRV_MRSZ_CFG_UPD_SHIFT 9U
/*! Slice: crop_enable:*/
#define MRV_MRSZ_CROP_ENABLE
#define MRV_MRSZ_CROP_ENABLE_MASK 0x00000100U
#define MRV_MRSZ_CROP_ENABLE_SHIFT 8U
#endif
/*! Slice: scale_vc_up:*/
/*! 1: vertical chrominance upscaling selected */
/* 0: vertical chrominance downscaling selected */
#define MRV_MRSZ_SCALE_VC_UP
#define MRV_MRSZ_SCALE_VC_UP_MASK 0x00000080U
#define MRV_MRSZ_SCALE_VC_UP_SHIFT 7U
/*! Slice: scale_vy_up:*/
/*! 1: vertical luminance upscaling selected */
/* 0: vertical luminance downscaling selected */
#define MRV_MRSZ_SCALE_VY_UP
#define MRV_MRSZ_SCALE_VY_UP_MASK 0x00000040U
#define MRV_MRSZ_SCALE_VY_UP_SHIFT 6U
/*! Slice: scale_hc_up:*/
/*! 1: horizontal chrominance upscaling selected */
/* 0: horizontal chrominance downscaling selected */
#define MRV_MRSZ_SCALE_HC_UP
#define MRV_MRSZ_SCALE_HC_UP_MASK 0x00000020U
#define MRV_MRSZ_SCALE_HC_UP_SHIFT 5U
/*! Slice: scale_hy_up:*/
/*! 1: horizontal luminance upscaling selected */
/* 0: horizontal luminance downscaling selected */
#define MRV_MRSZ_SCALE_HY_UP
#define MRV_MRSZ_SCALE_HY_UP_MASK 0x00000010U
#define MRV_MRSZ_SCALE_HY_UP_SHIFT 4U
/*! Slice: scale_vc_enable:*/
/*! 0: bypass vertical chrominance scaling unit */
/* 1: enable vertical chrominance scaling unit */
#define MRV_MRSZ_SCALE_VC_ENABLE
#define MRV_MRSZ_SCALE_VC_ENABLE_MASK 0x00000008U
#define MRV_MRSZ_SCALE_VC_ENABLE_SHIFT 3U
/*! Slice: scale_vy_enable:*/
/*! 0: bypass vertical luminance scaling unit */
/* 1: enable vertical luminance scaling unit */
#define MRV_MRSZ_SCALE_VY_ENABLE
#define MRV_MRSZ_SCALE_VY_ENABLE_MASK 0x00000004U
#define MRV_MRSZ_SCALE_VY_ENABLE_SHIFT 2U
/*! Slice: scale_hc_enable:*/
/*! 0: bypass horizontal chrominance scaling unit */
/* 1: enable horizontal chrominance scaling unit */
#define MRV_MRSZ_SCALE_HC_ENABLE
#define MRV_MRSZ_SCALE_HC_ENABLE_MASK 0x00000002U
#define MRV_MRSZ_SCALE_HC_ENABLE_SHIFT 1U
/*! Slice: scale_hy_enable:*/
/*! 0: bypass horizontal luminance scaling unit */
/* 1: enable horizontal luminance scaling unit */
#define MRV_MRSZ_SCALE_HY_ENABLE
#define MRV_MRSZ_SCALE_HY_ENABLE_MASK 0x00000001U
#define MRV_MRSZ_SCALE_HY_ENABLE_SHIFT 0U
/*! Register: mrsz_scale_hy: horizontal luminance scale factor register (0x00000004)*/
/*! Slice: scale_hy:*/
/*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
#define MRV_MRSZ_SCALE_HY
#define MRV_MRSZ_SCALE_HY_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HY_SHIFT 0U
/*! Register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008)*/
/*! Slice: scale_hcb:*/
/*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
#define MRV_MRSZ_SCALE_HCB
#define MRV_MRSZ_SCALE_HCB_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HCB_SHIFT 0U
/*! Register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)*/
/*! Slice: scale_hcr:*/
/*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
#define MRV_MRSZ_SCALE_HCR
#define MRV_MRSZ_SCALE_HCR_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HCR_SHIFT 0U
/*! Register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010)*/
/*! Slice: scale_vy:*/
/*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
#define MRV_MRSZ_SCALE_VY
#define MRV_MRSZ_SCALE_VY_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_VY_SHIFT 0U
/*! Register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014)*/
/*! Slice: scale_vc:*/
/*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
#define MRV_MRSZ_SCALE_VC
#define MRV_MRSZ_SCALE_VC_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_VC_SHIFT 0U
/*! Register: mrsz_phase_hy: horizontal luminance phase register (0x00000018)*/
/*! Slice: phase_hy:*/
/*! This register is set to the horizontal luminance phase offset */
#define MRV_MRSZ_PHASE_HY
#define MRV_MRSZ_PHASE_HY_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_HY_SHIFT 0U
/*! Register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c)*/
/*! Slice: phase_hc:*/
/*! This register is set to the horizontal chrominance phase offset */
#define MRV_MRSZ_PHASE_HC
#define MRV_MRSZ_PHASE_HC_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_HC_SHIFT 0U
/*! Register: mrsz_phase_vy: vertical luminance phase register (0x00000020)*/
/*! Slice: phase_vy:*/
/*! This register is set to the vertical luminance phase offset */
#define MRV_MRSZ_PHASE_VY
#define MRV_MRSZ_PHASE_VY_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_VY_SHIFT 0U
/*! Register: mrsz_phase_vc: vertical chrominance phase register (0x00000024)*/
/*! Slice: phase_vc:*/
/*! This register is set to the vertical chrominance phase offset */
#define MRV_MRSZ_PHASE_VC
#define MRV_MRSZ_PHASE_VC_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_VC_SHIFT 0U
/*! Register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table (0x00000028)*/
/*! Slice: scale_lut_addr:*/
/*! Pointer to entry of lookup table */
#define MRV_MRSZ_SCALE_LUT_ADDR
#define MRV_MRSZ_SCALE_LUT_ADDR_MASK 0x0000003FU
#define MRV_MRSZ_SCALE_LUT_ADDR_SHIFT 0U
/*! Register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c)*/
/*! Slice: scale_lut:*/
/*! Entry of lookup table at position scale_lut_addr. The lookup table must be filled with appropriate values before the up-scaling functionality can be used.*/
#define MRV_MRSZ_SCALE_LUT
#define MRV_MRSZ_SCALE_LUT_MASK 0x0000003FU
#define MRV_MRSZ_SCALE_LUT_SHIFT 0U
/*! Register: mrsz_ctrl_shd: global control shadow register (0x00000030)*/
/*! Slice: scale_vc_up_shd:*/
/*! 1: vertical chrominance upscaling selected */
/* 0: vertical chrominance downscaling selected */
#define MRV_MRSZ_SCALE_VC_UP_SHD
#define MRV_MRSZ_SCALE_VC_UP_SHD_MASK 0x00000080U
#define MRV_MRSZ_SCALE_VC_UP_SHD_SHIFT 7U
/*! Slice: scale_vy_up_shd:*/
/*! 1: vertical luminance upscaling selected */
/* 0: vertical luminance downscaling selected */
#define MRV_MRSZ_SCALE_VY_UP_SHD
#define MRV_MRSZ_SCALE_VY_UP_SHD_MASK 0x00000040U
#define MRV_MRSZ_SCALE_VY_UP_SHD_SHIFT 6U
/*! Slice: scale_hc_up_shd:*/
/*! 1: horizontal chrominance upscaling selected */
/* 0: horizontal chrominance downscaling selected */
#define MRV_MRSZ_SCALE_HC_UP_SHD
#define MRV_MRSZ_SCALE_HC_UP_SHD_MASK 0x00000020U
#define MRV_MRSZ_SCALE_HC_UP_SHD_SHIFT 5U
/*! Slice: scale_hy_up_shd:*/
/*! 1: horizontal luminance upscaling selected */
/* 0: horizontal luminance downscaling selected */
#define MRV_MRSZ_SCALE_HY_UP_SHD
#define MRV_MRSZ_SCALE_HY_UP_SHD_MASK 0x00000010U
#define MRV_MRSZ_SCALE_HY_UP_SHD_SHIFT 4U
/*! Slice: scale_vc_enable_shd:*/
/*! 0: bypass vertical chrominance scaling unit */
/* 1: enable vertical chrominance scaling unit */
#define MRV_MRSZ_SCALE_VC_ENABLE_SHD
#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008U
#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3U
/*! Slice: scale_vy_enable_shd:*/
/*! 0: bypass vertical luminance scaling unit */
/* 1: enable vertical luminance scaling unit */
#define MRV_MRSZ_SCALE_VY_ENABLE_SHD
#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004U
#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2U
/*! Slice: scale_hc_enable_shd:*/
/*! 0: bypass horizontal chrominance scaling unit */
/* 1: enable horizontal chrominance scaling unit */
#define MRV_MRSZ_SCALE_HC_ENABLE_SHD
#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002U
#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1U
/*! Slice: scale_hy_enable_shd:*/
/*! 0: bypass horizontal luminance scaling unit */
/* 1: enable horizontal luminance scaling unit */
#define MRV_MRSZ_SCALE_HY_ENABLE_SHD
#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001U
#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0U
/*! Register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow register (0x00000034)*/
/*! Slice: scale_hy_shd:*/
/*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
#define MRV_MRSZ_SCALE_HY_SHD
#define MRV_MRSZ_SCALE_HY_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HY_SHD_SHIFT 0U
/*! Register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register (0x00000038)*/
/*! Slice: scale_hcb_shd:*/
/*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
#define MRV_MRSZ_SCALE_HCB_SHD
#define MRV_MRSZ_SCALE_HCB_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HCB_SHD_SHIFT 0U
/*! Register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register (0x0000003c)*/
/*! Slice: scale_hcr_shd:*/
/*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
#define MRV_MRSZ_SCALE_HCR_SHD
#define MRV_MRSZ_SCALE_HCR_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_HCR_SHD_SHIFT 0U
/*! Register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register (0x00000040)*/
/*! Slice: scale_vy_shd:*/
/*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
#define MRV_MRSZ_SCALE_VY_SHD
#define MRV_MRSZ_SCALE_VY_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_VY_SHD_SHIFT 0U
/*! Register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow register (0x00000044)*/
/*! Slice: scale_vc_shd:*/
/*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
#define MRV_MRSZ_SCALE_VC_SHD
#define MRV_MRSZ_SCALE_VC_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_SCALE_VC_SHD_SHIFT 0U
/*! Register: mrsz_phase_hy_shd: horizontal luminance phase shadow register (0x00000048)*/
/*! Slice: phase_hy_shd:*/
/*! This register is set to the horizontal luminance phase offset */
#define MRV_MRSZ_PHASE_HY_SHD
#define MRV_MRSZ_PHASE_HY_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_HY_SHD_SHIFT 0U
/*! Register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register (0x0000004c)*/
/*! Slice: phase_hc_shd:*/
/*! This register is set to the horizontal chrominance phase offset */
#define MRV_MRSZ_PHASE_HC_SHD
#define MRV_MRSZ_PHASE_HC_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_HC_SHD_SHIFT 0U
/*! Register: mrsz_phase_vy_shd: vertical luminance phase shadow register (0x00000050)*/
/*! Slice: phase_vy_shd:*/
/*! This register is set to the vertical luminance phase offset */
#define MRV_MRSZ_PHASE_VY_SHD
#define MRV_MRSZ_PHASE_VY_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_VY_SHD_SHIFT 0U

/*! Register: mrsz_phase_crop_x_dir: Crop range in x direction register (0x00000058)*/
/*! Slice: crop_h_start:*/
/*! This slice is Selected picture start pixel position in the x-direction. */
#define MRV_MRSZ_PHASE_H_START
#define MRV_MRSZ_PHASE_H_START_MASK 0x00001FFFU
#define MRV_MRSZ_PHASE_H_START_SHIFT 0U

/*! Register: mrsz_phase_crop_x_dir: Crop range in x direction register (0x00000058)*/
/*! Slice: crop_h_end:*/
/*! This slice is Selected picture end pixel position in the x-direction.. */
#define MRV_MRSZ_PHASE_H_END
#define MRV_MRSZ_PHASE_H_END_MASK 0x1fff0000U
#define MRV_MRSZ_PHASE_H_END_SHIFT 16U

/*! Register: mrsz_phase_crop_y_dir: Crop range in y direction register (0x0000005c)*/
/*! Slice: crop_y_start:*/
/*! This slice is Selected picture start pixel position in the y-direction. */
#define MRV_MRSZ_PHASE_V_START
#define MRV_MRSZ_PHASE_V_START_MASK 0x00001FFFU
#define MRV_MRSZ_PHASE_V_START_SHIFT 0U

/*! Register: mrsz_phase_crop_y_dir: Crop range in y direction register (0x0000005c)*/
/*! Slice: crop_v_end:*/
/*! This slice is Selected picture end pixel position in the v-direction.. */
#define MRV_MRSZ_PHASE_V_END
#define MRV_MRSZ_PHASE_V_END_MASK 0x1fff0000U
#define MRV_MRSZ_PHASE_V_END_SHIFT 16U


/*! Register: mrsz_phase_vc_shd: vertical chrominance phase shadow register (0x00000054)*/
/*! Slice: phase_vc_shd:*/
/*! This register is set to the vertical chrominance phase offset */
#define MRV_MRSZ_PHASE_VC_SHD
#define MRV_MRSZ_PHASE_VC_SHD_MASK 0x0000FFFFU
#define MRV_MRSZ_PHASE_VC_SHD_SHIFT 0U
#define MRV_MRSZ_COVERT_OUTPUT
#define MRV_MRSZ_COVERT_OUTPUT_MASK 0x0000001CU
#define MRV_MRSZ_COVERT_OUTPUT_SHIFT 2U
#define MRV_MRSZ_COVERT_INPUT
#define MRV_MRSZ_COVERT_INPUT_MASK 0x00000003U
#define MRV_MRSZ_COVERT_INPUT_SHIFT 0U
#define MRV_MRSZ_COVERT_10_ENABLE
#define MRV_MRSZ_COVERT_10_ENABLE_MASK  0X00000100U
#define MRV_MRSZ_COVERT_10_ENABLE_SHIFT 8U
#define MRV_MRSZ_COVERT_10_METHOD
#define MRV_MRSZ_COVERT_10_METHOD_MASK  0X00000200U
#define MRV_MRSZ_COVERT_10_METHOD_SHIFT 9U
#define MRV_MRSZ_COVERT_PACK_FORMAT
#define MRV_MRSZ_COVERT_PACK_FORMAT_MASK 0x00000400U
#define MRV_MRSZ_COVERT_PACK_FORMAT_SHIFT 10U
/*! Register: srsz_ctrl: global control register (0x00000000)*/
/*! Slice: auto_upd:*/
/*! 1: automatic register update at frame end enabled.*/
/* 0: automatic register update at frame end disabled.*/
#define MRV_SRSZ_AUTO_UPD
#define MRV_SRSZ_AUTO_UPD_MASK 0x00000200U
#define MRV_SRSZ_AUTO_UPD_SHIFT 9U
/*! Slice: cfg_upd:*/
/*! write 0: nothing happens */
/* write 1: update shadow registers */
/* read: always 0 */
#define MRV_SRSZ_CFG_UPD
#define MRV_SRSZ_CFG_UPD_MASK 0x00000100U
#define MRV_SRSZ_CFG_UPD_SHIFT 8U
/*! Slice: scale_vc_up:*/
/*! 1: vertical chrominance upscaling selected */
/* 0: vertical chrominance downscaling selected */
#define MRV_SRSZ_SCALE_VC_UP
#define MRV_SRSZ_SCALE_VC_UP_MASK 0x00000080U
#define MRV_SRSZ_SCALE_VC_UP_SHIFT 7U
/*! Slice: scale_vy_up:*/
/*! 1: vertical luminance upscaling selected */
/* 0: vertical luminance downscaling selected */
#define MRV_SRSZ_SCALE_VY_UP
#define MRV_SRSZ_SCALE_VY_UP_MASK 0x00000040U
#define MRV_SRSZ_SCALE_VY_UP_SHIFT 6U
/*! Slice: scale_hc_up:*/
/*! 1: horizontal chrominance upscaling selected */
/* 0: horizontal chrominance downscaling selected */
#define MRV_SRSZ_SCALE_HC_UP
#define MRV_SRSZ_SCALE_HC_UP_MASK 0x00000020U
#define MRV_SRSZ_SCALE_HC_UP_SHIFT 5U
/*! Slice: scale_hy_up:*/
/*! 1: horizontal luminance upscaling selected */
/* 0: horizontal luminance downscaling selected */
#define MRV_SRSZ_SCALE_HY_UP
#define MRV_SRSZ_SCALE_HY_UP_MASK 0x00000010U
#define MRV_SRSZ_SCALE_HY_UP_SHIFT 4U
/*! Slice: scale_vc_enable:*/
/*! 0: bypass vertical chrominance scaling unit */
/* 1: enable vertical chrominance scaling unit */
#define MRV_SRSZ_SCALE_VC_ENABLE
#define MRV_SRSZ_SCALE_VC_ENABLE_MASK 0x00000008U
#define MRV_SRSZ_SCALE_VC_ENABLE_SHIFT 3U
/*! Slice: scale_vy_enable:*/
/*! 0: bypass vertical luminance scaling unit */
/* 1: enable vertical luminance scaling unit */
#define MRV_SRSZ_SCALE_VY_ENABLE
#define MRV_SRSZ_SCALE_VY_ENABLE_MASK 0x00000004U
#define MRV_SRSZ_SCALE_VY_ENABLE_SHIFT 2U
/*! Slice: scale_hc_enable:*/
/*! 0: bypass horizontal chrominance scaling unit */
/* 1: enable horizontal chrominance scaling unit */
#define MRV_SRSZ_SCALE_HC_ENABLE
#define MRV_SRSZ_SCALE_HC_ENABLE_MASK 0x00000002U
#define MRV_SRSZ_SCALE_HC_ENABLE_SHIFT 1U
/*! Slice: scale_hy_enable:*/
/*! 0: bypass horizontal luminance scaling unit */
/* 1: enable horizontal luminance scaling unit */
#define MRV_SRSZ_SCALE_HY_ENABLE
#define MRV_SRSZ_SCALE_HY_ENABLE_MASK 0x00000001U
#define MRV_SRSZ_SCALE_HY_ENABLE_SHIFT 0U
/*! Register: srsz_scale_hy: horizontal luminance scale factor register (0x00000004)*/
/*! Slice: scale_hy:*/
/*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
#define MRV_SRSZ_SCALE_HY
#define MRV_SRSZ_SCALE_HY_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HY_SHIFT 0U
/*! Register: srsz_scale_hcb: horizontal chrominance scale factor register (0x00000008)*/
/*! Slice: scale_hcb:*/
/*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
#define MRV_SRSZ_SCALE_HCB
#define MRV_SRSZ_SCALE_HCB_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HCB_SHIFT 0U
/*! Register: srsz_scale_hcr: horizontal chrominance scale factor register (0x0000000c)*/
/*! Slice: scale_hcr:*/
/*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
#define MRV_SRSZ_SCALE_HCR
#define MRV_SRSZ_SCALE_HCR_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HCR_SHIFT 0U
/*! Register: srsz_scale_vy: vertical luminance scale factor register (0x00000010)*/
/*! Slice: scale_vy:*/
/*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
#define MRV_SRSZ_SCALE_VY
#define MRV_SRSZ_SCALE_VY_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_VY_SHIFT 0U
/*! Register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014)*/
/*! Slice: scale_vc:*/
/*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
#define MRV_SRSZ_SCALE_VC
#define MRV_SRSZ_SCALE_VC_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_VC_SHIFT 0U
/*! Register: srsz_phase_hy: horizontal luminance phase register (0x00000018)*/
/*! Slice: phase_hy:*/
/*! This register is set to the horizontal luminance phase offset */
#define MRV_SRSZ_PHASE_HY
#define MRV_SRSZ_PHASE_HY_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_HY_SHIFT 0U
/*! Register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c)*/
/*! Slice: phase_hc:*/
/*! This register is set to the horizontal chrominance phase offset */
#define MRV_SRSZ_PHASE_HC
#define MRV_SRSZ_PHASE_HC_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_HC_SHIFT 0U
/*! Register: srsz_phase_vy: vertical luminance phase register (0x00000020)*/
/*! Slice: phase_vy:*/
/*! This register is set to the vertical luminance phase offset */
#define MRV_SRSZ_PHASE_VY
#define MRV_SRSZ_PHASE_VY_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_VY_SHIFT 0U
/*! Register: srsz_phase_vc: vertical chrominance phase register (0x00000024)*/
/*! Slice: phase_vc:*/
/*! This register is set to the vertical chrominance phase offset */
#define MRV_SRSZ_PHASE_VC
#define MRV_SRSZ_PHASE_VC_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_VC_SHIFT 0U
/*! Register: srsz_scale_lut_addr: Address pointer of up-scaling look up table (0x00000028)*/
/*! Slice: scale_lut_addr:*/
/*! Pointer to entry of lookup table */
#define MRV_SRSZ_SCALE_LUT_ADDR
#define MRV_SRSZ_SCALE_LUT_ADDR_MASK 0x0000003FU
#define MRV_SRSZ_SCALE_LUT_ADDR_SHIFT 0U
/*! Register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c)*/
/*! Slice: scale_lut:*/
/*! Entry of lookup table at position scale_lut_addr. The lookup table must be filled with appropriate values before the up-scaling functionality can be used.*/
#define MRV_SRSZ_SCALE_LUT
#define MRV_SRSZ_SCALE_LUT_MASK 0x0000003FU
#define MRV_SRSZ_SCALE_LUT_SHIFT 0U
/*! Register: srsz_ctrl_shd: global control shadow register (0x00000030)*/
/*! Slice: scale_vc_up_shd:*/
/*! 1: vertical chrominance upscaling selected */
/* 0: vertical chrominance downscaling selected */
#define MRV_SRSZ_SCALE_VC_UP_SHD
#define MRV_SRSZ_SCALE_VC_UP_SHD_MASK 0x00000080U
#define MRV_SRSZ_SCALE_VC_UP_SHD_SHIFT 7U
/*! Slice: scale_vy_up_shd:*/
/*! 1: vertical luminance upscaling selected */
/* 0: vertical luminance downscaling selected */
#define MRV_SRSZ_SCALE_VY_UP_SHD
#define MRV_SRSZ_SCALE_VY_UP_SHD_MASK 0x00000040U
#define MRV_SRSZ_SCALE_VY_UP_SHD_SHIFT 6U
/*! Slice: scale_hc_up_shd:*/
/*! 1: horizontal chrominance upscaling selected */
/* 0: horizontal chrominance downscaling selected */
#define MRV_SRSZ_SCALE_HC_UP_SHD
#define MRV_SRSZ_SCALE_HC_UP_SHD_MASK 0x00000020U
#define MRV_SRSZ_SCALE_HC_UP_SHD_SHIFT 5U
/*! Slice: scale_hy_up_shd:*/
/*! 1: horizontal luminance upscaling selected */
/* 0: horizontal luminance downscaling selected */
#define MRV_SRSZ_SCALE_HY_UP_SHD
#define MRV_SRSZ_SCALE_HY_UP_SHD_MASK 0x00000010U
#define MRV_SRSZ_SCALE_HY_UP_SHD_SHIFT 4U
/*! Slice: scale_vc_enable_shd:*/
/*! 0: bypass vertical chrominance scaling unit */
/* 1: enable vertical chrominance scaling unit */
#define MRV_SRSZ_SCALE_VC_ENABLE_SHD
#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008U
#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3U
/*! Slice: scale_vy_enable_shd:*/
/*! 0: bypass vertical luminance scaling unit */
/* 1: enable vertical luminance scaling unit */
#define MRV_SRSZ_SCALE_VY_ENABLE_SHD
#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004U
#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2U
/*! Slice: scale_hc_enable_shd:*/
/*! 0: bypass horizontal chrominance scaling unit */
/* 1: enable horizontal chrominance scaling unit */
#define MRV_SRSZ_SCALE_HC_ENABLE_SHD
#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002U
#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1U
/*! Slice: scale_hy_enable_shd:*/
/*! 0: bypass horizontal luminance scaling unit */
/* 1: enable horizontal luminance scaling unit */
#define MRV_SRSZ_SCALE_HY_ENABLE_SHD
#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001U
#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0U
/*! Register: srsz_scale_hy_shd: horizontal luminance scale factor shadow register (0x00000034)*/
/*! Slice: scale_hy_shd:*/
/*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
#define MRV_SRSZ_SCALE_HY_SHD
#define MRV_SRSZ_SCALE_HY_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HY_SHD_SHIFT 0U
/*! Register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register (0x00000038)*/
/*! Slice: scale_hcb_shd:*/
/*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
#define MRV_SRSZ_SCALE_HCB_SHD
#define MRV_SRSZ_SCALE_HCB_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HCB_SHD_SHIFT 0U
/*! Register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register (0x0000003c)*/
/*! Slice: scale_hcr_shd:*/
/*! This register is set to the horizontal r downscale factor or to the reciprocal of the horizontal r upscale factor */
#define MRV_SRSZ_SCALE_HCR_SHD
#define MRV_SRSZ_SCALE_HCR_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_HCR_SHD_SHIFT 0U
/*! Register: srsz_scale_vy_shd: vertical luminance scale factor shadow register (0x00000040)*/
/*! Slice: scale_vy_shd:*/
/*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
#define MRV_SRSZ_SCALE_VY_SHD
#define MRV_SRSZ_SCALE_VY_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_VY_SHD_SHIFT 0U
/*! Register: srsz_scale_vc_shd: vertical chrominance scale factor shadow register (0x00000044)*/
/*! Slice: scale_vc_shd:*/
/*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
#define MRV_SRSZ_SCALE_VC_SHD
#define MRV_SRSZ_SCALE_VC_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_SCALE_VC_SHD_SHIFT 0U
/*! Register: srsz_phase_hy_shd: horizontal luminance phase shadow register (0x00000048)*/
/*! Slice: phase_hy_shd:*/
/*! This register is set to the horizontal luminance phase offset */
#define MRV_SRSZ_PHASE_HY_SHD
#define MRV_SRSZ_PHASE_HY_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_HY_SHD_SHIFT 0U
/*! Register: srsz_phase_hc_shd: horizontal chrominance phase shadow register (0x0000004c)*/
/*! Slice: phase_hc_shd:*/
/*! This register is set to the horizontal chrominance phase offset */
#define MRV_SRSZ_PHASE_HC_SHD
#define MRV_SRSZ_PHASE_HC_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_HC_SHD_SHIFT 0U
/*! Register: srsz_phase_vy_shd: vertical luminance phase shadow register (0x00000050)*/
/*! Slice: phase_vy_shd:*/
/*! This register is set to the vertical luminance phase offset */
#define MRV_SRSZ_PHASE_VY_SHD
#define MRV_SRSZ_PHASE_VY_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_VY_SHD_SHIFT 0U
/*! Register: srsz_phase_vc_shd: vertical chrominance phase shadow register (0x00000054)*/
/*! Slice: phase_vc_shd:*/
/*! This register is set to the vertical chrominance phase offset */
#define MRV_SRSZ_PHASE_VC_SHD
#define MRV_SRSZ_PHASE_VC_SHD_MASK 0x0000FFFFU
#define MRV_SRSZ_PHASE_VC_SHD_SHIFT 0U
/*! Register: mi_ctrl: Global control register (0x00000000)*/
/*! Slice: sp_output_format:*/
/*! Selects output format of self picture. For possible restrictions see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
     /**/
/* 111: reserved */
/* 110: RGB 888 */
/* 101: RGB 666 */
/* 100: RGB 565 */
     /**/
/* 011: YCbCr  4:4:4 */
/* 010: YCbCr  4:2:2 */
/* 001: YCbCr  4:2:0 */
/* 000: YCbCr  4:0:0 */
     /**/
/* Note:*/
/* - Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
/* - for RGB output format the SP input format must be YCbCr 4:2:2 */
#define MRV_MI_SP_OUTPUT_FORMAT
#define MRV_MI_SP_OUTPUT_FORMAT_MASK 0x70000000U
#define MRV_MI_SP_OUTPUT_FORMAT_SHIFT 28U
/*! Slice: sp_input_format:*/
/*! Selects input format of self picture. For possible restrictions see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
     /**/
/* 11: YCbCr  4:4:4 */
/* 10: YCbCr  4:2:2 */
/* 01: YCbCr  4:2:0 */
/* 00: YCbCr  4:0:0 */
     /**/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_INPUT_FORMAT
#define MRV_MI_SP_INPUT_FORMAT_MASK 0x0C000000U
#define MRV_MI_SP_INPUT_FORMAT_SHIFT 26U
/*! Slice: sp_write_format:*/
/*! defines how YCbCr self picture data is written to memory.*/
/* Must be set to 00 if RGB conversion is active. Note that with RGB conversion active the output format is always interleaved.*/
     /**/
/* 00:	planar */
/* 01:	semi planar, for YCbCr 4:2:x */
/* 10:	interleaved (combined), for YCbCr 4:2:2 only */
/* 11:	reserved */
     /**/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_WRITE_FORMAT
#define MRV_MI_SP_WRITE_FORMAT_MASK 0x03000000U
#define MRV_MI_SP_WRITE_FORMAT_SHIFT 24U
/*! Slice: mp_write_format:*/
/*! Defines how YCbCr main picture data is written to memory. Ignored if JPEG data is chosen.*/
/* In YCbCr mode the following meaning is applicable */
/* 00:	planar */
/* 01:	semi planar, for YCbCr 4:2:x */
/* 10:	interleaved (combined), for YCbCr 4:2:2 only */
/* 11:	reserved */
/* In RAW data mode the following meaning is applicable */
/* 00:	RAW 8 bit */
/* 01:	reserved */
/* 10:	RAW 12 bit */
/* 11:	reserved */
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main path.*/
#define MRV_MI_MP_WRITE_FORMAT
#define MRV_MI_MP_WRITE_FORMAT_MASK 0x00C00000U
#define MRV_MI_MP_WRITE_FORMAT_SHIFT 22U
/*! Slice: init_offset_en:*/
/*! Enables updating of the offset counters shadow registers for main and self picture to the programmed register init values.*/
/* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */
/* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */
/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/
/* After a picture skip has been performed init_offset_en selects between skip restart and skip init mode (see bit skip in register MI_INIT).*/
#define MRV_MI_INIT_OFFSET_EN
#define MRV_MI_INIT_OFFSET_EN_MASK 0x00200000U
#define MRV_MI_INIT_OFFSET_EN_SHIFT 21U
/*! Slice: init_base_en:*/
/*! Enables updating of the base address and buffer size shadow registers for main and self picture to the programmed register init values.*/
/* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */
/* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */
/* MI_MP/SP_Y/CB/CR_SIZE_INIT */
/* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */
/* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/
#define MRV_MI_INIT_BASE_EN
#define MRV_MI_INIT_BASE_EN_MASK 0x00100000U
#define MRV_MI_INIT_BASE_EN_SHIFT 20U
/*! Slice: burst_len_chrom:*/
/*! Burst length for Cb or Cr data affecting write port.*/
/* 00: 4-beat bursts */
/* 01: 8-beat bursts */
/* 10: 16-beat bursts */
/* 11: reserved */
/* Ignored if 8- or 16-beat bursts are not supported. If rotation is active, then only 4-beat bursts will be generated in self path, regardless of the setting here.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
#define MRV_MI_BURST_LEN_CHROM
#define MRV_MI_BURST_LEN_CHROM_MASK 0x000C0000U
#define MRV_MI_BURST_LEN_CHROM_SHIFT 18U
/*! Slice: burst_len_lum:*/
/*! Burst length for Y, JPEG, or raw data affecting write port.*/
/* 00: 4-beat bursts */
/* 01: 8-beat bursts */
/* 10: 16-beat bursts */
/* 11: reserved */
/* Ignored if 8- or 16-beat bursts are not supported.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
#define MRV_MI_BURST_LEN_LUM
#define MRV_MI_BURST_LEN_LUM_MASK 0x00030000U
#define MRV_MI_BURST_LEN_LUM_SHIFT 16U
/*! Slice: last_pixel_sig_en:*/
/*! enables the last pixel signalization */
/* 1: enabled */
/* 0: disabled */
#define MRV_MI_LAST_PIXEL_SIG_EN
#define MRV_MI_LAST_PIXEL_SIG_EN_MASK 0x00008000U
#define MRV_MI_LAST_PIXEL_SIG_EN_SHIFT 15U
/*! Slice: sp_auto_update:*/
/*! automatic update of configuration registers for self path at frame end.*/
/* 1: enabled */
/* 0: disabled */
#define MRV_MI_SP_AUTO_UPDATE
#define MRV_MI_SP_AUTO_UPDATE_MASK 0x00004000U
#define MRV_MI_SP_AUTO_UPDATE_SHIFT 14U
/*! Slice: mp_auto_update:*/
/*! automatic update of configuration registers for main path at frame end.*/
/* 1: enabled */
/* 0: disabled */
#define MRV_MI_MP_AUTO_UPDATE
#define MRV_MI_MP_AUTO_UPDATE_MASK 0x00002000U
#define MRV_MI_MP_AUTO_UPDATE_SHIFT 13U
/*! Slice: sp_pingpong_enable:*/
/*! pingpong  mode of configuration registers for self path at frame end.*/
/* 1: enabled */
/* 0: disabled */
#define MRV_MI_SP_PINGPONG_ENABLE
#define MRV_MI_SP_PINGPONG_ENABLE_MASK 0x00001000U
#define MRV_MI_SP_PINGPONG_ENABLE_SHIFT 12U
/*! Slice: mp_pingpong_enable:*/
/*! pingpong  mode of configuration registers for main path at frame end.*/
/* 1: enabled */
/* 0: disabled */
#define MRV_MI_MP_PINGPONG_ENABLE
#define MRV_MI_MP_PINGPONG_ENABLE_MASK 0x00000800U
#define MRV_MI_MP_PINGPONG_ENABLE_SHIFT 11U
/*! Slice: 422noncosited:*/
/*! Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */
/* (M5_v6, M5_v7 only)*/
/* 1: YCbCr422 data are non_co-sited (Cb and Cr samples are centered between Y samples) so modified interpolation is activated */
/* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are sampled at the same position)*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_422NONCOSITED
#define MRV_MI_422NONCOSITED_MASK 0x00000400U
#define MRV_MI_422NONCOSITED_SHIFT 10U
/*! Slice: cbcr_full_range:*/
/*! Enables CbCr full range for self path YCbCr -> RGB conversion */
/* (M5_v6, M5_v7 only)*/
/* 1: CbCr have full range (0..255)*/
/* 0: CbCr have compressed range range (16..240)*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_CBCR_FULL_RANGE
#define MRV_MI_CBCR_FULL_RANGE_MASK 0x00000200U
#define MRV_MI_CBCR_FULL_RANGE_SHIFT 9U
/*! Slice: y_full_range:*/
/*! Enables Y full range for self path YCbCr -> RGB conversion */
/* (M5_v6, M5_v7 only)*/
/* 1: Y has full range (0..255)*/
/* 0: Y has compressed range (16..235)*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_Y_FULL_RANGE
#define MRV_MI_Y_FULL_RANGE_MASK 0x00000100U
#define MRV_MI_Y_FULL_RANGE_SHIFT 8U
/*! Slice: byte_swap:*/
/*! Enables change of byte order of the 32 bit output word at write port */
/* 1: byte order is mirrored but the bit order within one byte doesnt change */
/* 0: no byte mirroring */
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
#define MRV_MI_BYTE_SWAP
#define MRV_MI_BYTE_SWAP_MASK 0x00000080U
#define MRV_MI_BYTE_SWAP_SHIFT 7U
/*! Slice: rot:*/
/*! Rotation 90 degree counter clockwise of self picture, only in RGB mode. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
/* For RGB 565 format the line length must be a multiple of 2. There are no restrictions for RGB 888/666.*/
/* 1: enabled */
/* 0: disabled */
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path. In rotation mode only 4-beat bursts are supported for self-path.*/
#define MRV_MI_ROT
#define MRV_MI_ROT_MASK 0x00000040U
#define MRV_MI_ROT_SHIFT 6U
/*! Slice: v_flip:*/
/*! Vertical flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
/* 1: enabled */
/* 0: disabled */
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_V_FLIP
#define MRV_MI_V_FLIP_MASK 0x00000020U
#define MRV_MI_V_FLIP_SHIFT 5U
/*! Slice: h_flip:*/
/*! Horizontal flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
/* 1: enabled */
/* 0: disabled */
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_H_FLIP
#define MRV_MI_H_FLIP_MASK 0x00000010U
#define MRV_MI_H_FLIP_SHIFT 4U
/*! Slice: path_enable:*/
/*! Enables data pathes of MI according to the following table:*/
     /**/
/* 0000: disabled, no data is transferred */
/* 0001: YUV data output, mainpath only (mp_enable only)*/
/* 0010: self-path only, output data format depending on other settings (sp_enable only)*/
/* 0011: YUV data output in mainpath and self-path image data active */
/* 0100: JPEG data output, mainpath only (jpeg_enable only)*/
/* 0101: not allowed */
/* 0110: JPEG data output in mainpath and self-path image data active */
/* 0111: not allowed */
/* 1000: RAW data output, mainpath only (raw_enable only)*/
/* 1001: defect pixel data on self-path, image data on mainpath */
/* 1010: defect pixel data on mainpath, image data on self-path */
/* 1011: not allowed */
/* 1100: defect pixel data on self-path, JPEG data on mainpath */
/* 1101: defect pixel data on mainpath only */
/* 1110: defect pixel data on self-path only */
/* 1111: defect pixel data on self-path, RAW data on mainpath */
     /**/
/* Programmed value becomes effective (visible in shadow register) after a soft reset, a forced software update or an automatic config update.  Affects MI_IN and MI_OUT module.*/
#define MRV_MI_PATH_ENABLE
#define MRV_MI_PATH_ENABLE_MASK 0x0000000FU
#define MRV_MI_PATH_ENABLE_SHIFT 0U
/*! Register: mi_init: Control register for address init and skip function (0x00000004)*/
/*! Slice: mi_output_format */
#define MRV_MI_MP_OUTPUT_FORMAT
#define MRV_MI_MP_OUTPUT_FORMAT_MASK 0x000001E0U
#define MRV_MI_MP_OUTPUT_FORMAT_SHIFT 5U
/*! Slice: mi_cfg_upd:*/
/*! Forced configuration update. Leads to an immediate update of the shadow registers.*/
/* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and init_base_en) the offset counter, base address and buffer size shadow registers are also updated.*/
#define MRV_MI_MI_CFG_UPD
#define MRV_MI_MI_CFG_UPD_MASK 0x00000010U
#define MRV_MI_MI_CFG_UPD_SHIFT 4U
/*! Slice: mi_skip:*/
/*! Skip of current or next starting main picture:*/
/* Aborts writing of main picture image data of the current frame to RAM (after the current burst transmission has been completed). Further main picture data up to the end of the current frame are discarded.*/
     /**/
/* No further makroblock line interrupt (mblk_line), no wrap around interrupt for main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/
     /**/
/* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/
/* Skip does not affect the processing of self picture and its corresponding interrupts namely the self path frame end interrupt (sp_frame_end).*/
     /**/
/* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/
     /**/
/* After a skip has been performed the offset counter for the main picture at the start of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/
     /**/
/* - Skip restart mode (init_offset_en = 0)*/
/* The offset counters of the main picture are restarted at the old start values of the previous skipped frame.*/
     /**/
/* - Skip init mode (init_offset_en = 1)*/
/* The offset counters of the main picture are initialized with the register contents of the offset counter init registers without any additional forced software update or automatic config update.*/
#define MRV_MI_MI_SKIP
#define MRV_MI_MI_SKIP_MASK 0x00000004U
#define MRV_MI_MI_SKIP_SHIFT 2U
/*! Register: mi_mp_y_base_ad_init: Base address for main picture Y component, JPEG or raw data (0x00000008)*/
/*! Slice: mp_y_base_ad_init:*/
/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
#ifdef ISP_MP_34BIT
#define MRV_MI_MP_Y_BASE_AD_INIT
#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFFEU
#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 1U
#else
#define MRV_MI_MP_Y_BASE_AD_INIT
#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 3U
#endif
/*! Register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw data (0x0000000c)*/
/*! Slice: mp_y_size_init:*/
/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
#define MRV_MI_MP_Y_SIZE_INIT
#define MRV_MI_MP_Y_SIZE_INIT_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_SIZE_INIT_SHIFT 3U
/*! Register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture Y, JPEG or raw data (0x00000010)*/
/*! Slice: mp_y_offs_cnt_init:*/
/*! Offset counter init value of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
#define MRV_MI_MP_Y_OFFS_CNT_INIT
#define MRV_MI_MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture Y, JPEG or raw data (0x00000014)*/
/*! Slice: mp_y_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (main picture Y component, JPEG or raw data). Updated at frame end.*/
/* Note: A soft reset resets the contents to the reset value.*/
#define MRV_MI_MP_Y_OFFS_CNT_START
#define MRV_MI_MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main picture Y, JPEG or raw data (0x00000018)*/
/*! Slice: mp_y_irq_offs_init:*/
/*! Reaching this programmed value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
#define MRV_MI_MP_Y_IRQ_OFFS_INIT
#define MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: mi_mp_cb_base_ad_init: Base address for main picture Cb component ring buffer (0x0000001c)*/
/*! Slice: mp_cb_base_ad_init:*/
/*! Base address of main picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#ifdef ISP_MP_34BIT
#define MRV_MI_MP_CB_BASE_AD_INIT
#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFFEU
#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 1U
#else
#define MRV_MI_MP_CB_BASE_AD_INIT
#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 3U
#endif
/*! Register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer (0x00000020)*/
/*! Slice: mp_cb_size_init:*/
/*! Size of main picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_MP_CB_SIZE_INIT
#define MRV_MI_MP_CB_SIZE_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CB_SIZE_INIT_SHIFT 3U
/*! Register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture Cb component ring buffer (0x00000024)*/
/*! Slice: mp_cb_offs_cnt_init:*/
/*! Offset counter init value of main picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/
#define MRV_MI_MP_CB_OFFS_CNT_INIT
#define MRV_MI_MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CB_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_mp_cb_offs_cnt_start: Offset counter start value for main picture Cb component ring buffer (0x00000028)*/
/*! Slice: mp_cb_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (main picture Cb component). Updated at frame end.*/
#define MRV_MI_MP_CB_OFFS_CNT_START
#define MRV_MI_MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CB_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_mp_cr_base_ad_init: Base address for main picture Cr component ring buffer (0x0000002c)*/
/*! Slice: mp_cr_base_ad_init:*/
/*! Base address of main picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#ifdef ISP_MP_34BIT
#define MRV_MI_MP_CR_BASE_AD_INIT
#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFFEU
#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 1U
#else
#define MRV_MI_MP_CR_BASE_AD_INIT
#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 3U
#endif
/*! Register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer (0x00000030)*/
/*! Slice: mp_cr_size_init:*/
/*! Size of main picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_MP_CR_SIZE_INIT
#define MRV_MI_MP_CR_SIZE_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CR_SIZE_INIT_SHIFT 3U
/*! Register: mi_mp_cr_offs_cnt_init: Offset counter init value for main picture Cr component ring buffer (0x00000034)*/
/*! Slice: mp_cr_offs_cnt_init:*/
/*! Offset counter init value of main picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/
#define MRV_MI_MP_CR_OFFS_CNT_INIT
#define MRV_MI_MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CR_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_mp_cr_offs_cnt_start: Offset counter start value for main picture Cr component ring buffer (0x00000038)*/
/*! Slice: mp_cr_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (main picture Cr component). Updated at frame end.*/
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_MP_CR_OFFS_CNT_START
#define MRV_MI_MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CR_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_sp_y_base_ad_init: Base address for self picture Y component ring buffer (0x0000003c)*/
/*! Slice: sp_y_base_ad_init:*/
/*! Base address of self picture Y component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_Y_BASE_AD_INIT
#define MRV_MI_SP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_SP_Y_BASE_AD_INIT_SHIFT 3U
/*! Register: mi_sp_y_size_init: Size of self picture Y component ring buffer (0x00000040)*/
/*! Slice: sp_y_size_init:*/
/*! Size of self picture Y component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_Y_SIZE_INIT
#define MRV_MI_SP_Y_SIZE_INIT_MASK 0x1FFFFFF8U
#define MRV_MI_SP_Y_SIZE_INIT_SHIFT 3U
/*! Register: mi_sp_y_offs_cnt_init: Offset counter init value for self picture Y component ring buffer (0x00000044)*/
/*! Slice: sp_y_offs_cnt_init:*/
/*! Offset counter init value of self picture Y component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_Y_OFFS_CNT_INIT
#define MRV_MI_SP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define MRV_MI_SP_Y_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_sp_y_offs_cnt_start: Offset counter start value for self picture Y component ring buffer (0x00000048)*/
/*! Slice: sp_y_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (self picture Y component). Updated at frame end.*/
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_SP_Y_OFFS_CNT_START
#define MRV_MI_SP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U
#define MRV_MI_SP_Y_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)*/
/*! Slice: sp_y_llength:*/
/*! Line length of self picture Y component or RGB picture in pixel, also known as line stride.*/
/* If no line stride is used, line length must match image width.*/
/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb and Cr component is assumed the same size.*/
/* Note: Line length always refers to the line length of the output image. This is particularly important when rotating.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_Y_LLENGTH
#define MRV_MI_SP_Y_LLENGTH_MASK 0x00007FFFU
#define MRV_MI_SP_Y_LLENGTH_SHIFT 0U
/*! Register: mi_sp_cb_base_ad_init: Base address for self picture Cb component ring buffer (0x00000050)*/
/*! Slice: sp_cb_base_ad_init:*/
/*! Base address of self picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CB_BASE_AD_INIT
#define MRV_MI_SP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CB_BASE_AD_INIT_SHIFT 3U
/*! Register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer (0x00000054)*/
/*! Slice: sp_cb_size_init:*/
/*! Size of self picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CB_SIZE_INIT
#define MRV_MI_SP_CB_SIZE_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CB_SIZE_INIT_SHIFT 3U
/*! Register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture Cb component ring buffer (0x00000058)*/
/*! Slice: sp_cb_offs_cnt_init:*/
/*! Offset counter init value of self picture Cb component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CB_OFFS_CNT_INIT
#define MRV_MI_SP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CB_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_sp_cb_offs_cnt_start: Offset counter start value for self picture Cb component ring buffer (0x0000005c)*/
/*! Slice: sp_cb_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (self picture Cb component). Updated at frame end.*/
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_SP_CB_OFFS_CNT_START
#define MRV_MI_SP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CB_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_sp_cr_base_ad_init: Base address for self picture Cr component ring buffer (0x00000060)*/
/*! Slice: sp_cr_base_ad_init:*/
/*! Base address of self picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CR_BASE_AD_INIT
#define MRV_MI_SP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CR_BASE_AD_INIT_SHIFT 3U
/*! Register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer (0x00000064)*/
/*! Slice: sp_cr_size_init:*/
/*! Size of self picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CR_SIZE_INIT
#define MRV_MI_SP_CR_SIZE_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CR_SIZE_INIT_SHIFT 3U
/*! Register: mi_sp_cr_offs_cnt_init: Offset counter init value for self picture Cr component ring buffer (0x00000068)*/
/*! Slice: sp_cr_offs_cnt_init:*/
/*! Offset counter init value of self picture Cr component ring buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CR_OFFS_CNT_INIT
#define MRV_MI_SP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CR_OFFS_CNT_INIT_SHIFT 3U
/*! Register: mi_sp_cr_offs_cnt_start: Offset counter start value for self picture Cr component ring buffer (0x0000006c)*/
/*! Slice: sp_cr_offs_cnt_start:*/
/*! Offset counter value which points to the start address of the previously processed picture (self picture Cr component). Updated at frame end.*/
#define MRV_MI_SP_CR_OFFS_CNT_START
#define MRV_MI_SP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CR_OFFS_CNT_START_SHIFT 3U
/*! Register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)*/
/*! Slice: byte_cnt:*/
/*! Counter value specifies the number of JPEG or RAW data bytes of the last transmitted frame. Updated at frame end.*/
/* A soft reset will set the byte counter to zero.*/
#define MRV_MI_BYTE_CNT
#define MRV_MI_BYTE_CNT_MASK 0x0FFFFFFFU
#define MRV_MI_BYTE_CNT_SHIFT 0U
/*! Register: mi_ctrl_shd: global control internal shadow register (0x00000074)*/
/*! Slice: path_enable_out:*/
/*! path_enable shadow register for module MI_OUT (former raw_enable_out, jpeg_enable_out, sp_enable_out, mp_enable_out)*/
#define MRV_MI_PATH_ENABLE_OUT
#define MRV_MI_PATH_ENABLE_OUT_MASK 0x000F0000U
#define MRV_MI_PATH_ENABLE_OUT_SHIFT 16U
/*! Slice: path_enable_in:*/
/*! path_enable shadow register for module MI_IN (former raw_enable_in, jpeg_enable_in, sp_enable_in, mp_enable_in)*/
#define MRV_MI_PATH_ENABLE_IN
#define MRV_MI_PATH_ENABLE_IN_MASK 0x0000000FU
#define MRV_MI_PATH_ENABLE_IN_SHIFT 0U
/*! Register: mi_mp_y_base_ad_shd: Base address shadow register for main picture Y component, JPEG or raw data ring buffer (0x00000078)*/
/*! Slice: mp_y_base_ad:*/
/*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
#define MRV_MI_MP_Y_BASE_AD
#define MRV_MI_MP_Y_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_MP_Y_BASE_AD_SHIFT 3U
/*! Register: mi_mp_y_size_shd: Size shadow register of main picture Y component, JPEG or raw data (0x0000007c)*/
/*! Slice: mp_y_size:*/
/*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
#define MRV_MI_MP_Y_SIZE
#define MRV_MI_MP_Y_SIZE_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_SIZE_SHIFT 3U
/*! Register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y component, JPEG or raw data ring buffer (0x00000080)*/
/*! Slice: mp_y_offs_cnt:*/
/*! Current offset counter of main picture Y component, JPEG or raw data ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_MP_Y_OFFS_CNT
#define MRV_MI_MP_Y_OFFS_CNT_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_OFFS_CNT_SHIFT 3U
/*! Register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (0x00000084)*/
/*! Slice: mp_y_irq_offs:*/
/*! Reaching this offset value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/
#define MRV_MI_MP_Y_IRQ_OFFS
#define MRV_MI_MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MRV_MI_MP_Y_IRQ_OFFS_SHIFT 3U
/*! Register: mi_mp_cb_base_ad_shd: Base address shadow register for main picture Cb component ring buffer (0x00000088)*/
/*! Slice: mp_cb_base_ad:*/
/*! Base address of main picture Cb component ring buffer.*/
#define MRV_MI_MP_CB_BASE_AD
#define MRV_MI_MP_CB_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CB_BASE_AD_SHIFT 3U
/*! Register: mi_mp_cb_size_shd: Size shadow register of main picture Cb component ring buffer (0x0000008c)*/
/*! Slice: mp_cb_size:*/
/*! Size of main picture Cb component ring buffer.*/
#define MRV_MI_MP_CB_SIZE
#define MRV_MI_MP_CB_SIZE_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CB_SIZE_SHIFT 3U
/*! Register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb component ring buffer (0x00000090)*/
/*! Slice: mp_cb_offs_cnt:*/
/*! Current offset counter of main picture Cb component ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_MP_CB_OFFS_CNT
#define MRV_MI_MP_CB_OFFS_CNT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CB_OFFS_CNT_SHIFT 3U
/*! Register: mi_mp_cr_base_ad_shd: Base address shadow register for main picture Cr component ring buffer (0x00000094)*/
/*! Slice: mp_cr_base_ad:*/
/*! Base address of main picture Cr component ring buffer.*/
#define MRV_MI_MP_CR_BASE_AD
#define MRV_MI_MP_CR_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CR_BASE_AD_SHIFT 3U
/*! Register: mi_mp_cr_size_shd: Size shadow register of main picture Cr component ring buffer (0x00000098)*/
/*! Slice: mp_cr_size:*/
/*! Size of main picture Cr component ring buffer.*/
#define MRV_MI_MP_CR_SIZE
#define MRV_MI_MP_CR_SIZE_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CR_SIZE_SHIFT 3U
/*! Register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr component ring buffer (0x0000009c)*/
/*! Slice: mp_cr_offs_cnt:*/
/*! Current offset counter of main picture Cr component ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_MP_CR_OFFS_CNT
#define MRV_MI_MP_CR_OFFS_CNT_MASK 0x0FFFFFF8U
#define MRV_MI_MP_CR_OFFS_CNT_SHIFT 3U
/*! Register: mi_sp_y_base_ad_shd: Base address shadow register for self picture Y component ring buffer (0x000000a0)*/
/*! Slice: sp_y_base_ad:*/
/*! Base address of self picture Y component ring buffer.*/
#define MRV_MI_SP_Y_BASE_AD
#define MRV_MI_SP_Y_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_SP_Y_BASE_AD_SHIFT 3U
/*! Register: mi_sp_y_size_shd: Size shadow register of self picture Y component ring buffer (0x000000a4)*/
/*! Slice: sp_y_size:*/
/*! Size of self picture Y component ring buffer.*/
#define MRV_MI_SP_Y_SIZE
#define MRV_MI_SP_Y_SIZE_MASK 0x1FFFFFF8U
#define MRV_MI_SP_Y_SIZE_SHIFT 3U
/*! Register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y component ring buffer (0x000000a8)*/
/*! Slice: sp_y_offs_cnt:*/
/*! Current offset counter of self picture Y component ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_SP_Y_OFFS_CNT
#define MRV_MI_SP_Y_OFFS_CNT_MASK 0x1FFFFFF8U
#define MRV_MI_SP_Y_OFFS_CNT_SHIFT 3U
/*! Register: mi_sp_cb_base_ad_shd: Base address shadow register for self picture Cb component ring buffer (0x000000b0)*/
/*! Slice: sp_cb_base_ad:*/
/*! Base address of self picture Cb component ring buffer.*/
#define MRV_MI_SP_CB_BASE_AD
#define MRV_MI_SP_CB_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CB_BASE_AD_SHIFT 3U
/*! Register: mi_sp_cb_size_shd: Size shadow register of self picture Cb component ring buffer (0x000000b4)*/
/*! Slice: sp_cb_size:*/
/*! Size of self picture Cb component ring buffer.*/
#define MRV_MI_SP_CB_SIZE
#define MRV_MI_SP_CB_SIZE_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CB_SIZE_SHIFT 3U
/*! Register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture Cb component ring buffer (0x000000b8)*/
/*! Slice: sp_cb_offs_cnt:*/
/*! Current offset counter of self picture Cb component ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_SP_CB_OFFS_CNT
#define MRV_MI_SP_CB_OFFS_CNT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CB_OFFS_CNT_SHIFT 3U
/*! Register: mi_sp_cr_base_ad_shd: Base address shadow register for self picture Cr component ring buffer (0x000000bc)*/
/*! Slice: sp_cr_base_ad:*/
/*! Base address of self picture Cr component ring buffer.*/
#define MRV_MI_SP_CR_BASE_AD
#define MRV_MI_SP_CR_BASE_AD_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CR_BASE_AD_SHIFT 3U
/*! Register: mi_sp_cr_size_shd: Size shadow register of self picture Cr component ring buffer (0x000000c0)*/
/*! Slice: sp_cr_size:*/
/*! Size of self picture Cr component ring buffer.*/
#define MRV_MI_SP_CR_SIZE
#define MRV_MI_SP_CR_SIZE_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CR_SIZE_SHIFT 3U
/*! Register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr component ring buffer (0x000000c4)*/
/*! Slice: sp_cr_offs_cnt:*/
/*! Current offset counter of self picture Cr component ring buffer for address generation */
/* Note: Soft reset will reset the contents to reset value.*/
#define MRV_MI_SP_CR_OFFS_CNT
#define MRV_MI_SP_CR_OFFS_CNT_MASK 0x0FFFFFF8U
#define MRV_MI_SP_CR_OFFS_CNT_SHIFT 3U
/*! Register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)*/
/*! Slice: dma_y_pic_start_ad:*/
/*! Image start address of the y component */
/* Note: Must be multiple of 4 in interleaved mode.*/
#define MRV_MI_DMA_Y_PIC_START_AD
#define MRV_MI_DMA_Y_PIC_START_AD_MASK 0xFFFFFFFFU
#define MRV_MI_DMA_Y_PIC_START_AD_SHIFT 0U
/*! Register: mi_dma_y_pic_width: Y component image width (0x000000cc)*/
/*! Slice: dma_y_pic_width:*/
/*! Image width of the Y component in pixel.*/
/* For YCbCr 4:2:x the image width must be a multiple of 2.*/
/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/
#define MRV_MI_DMA_Y_PIC_WIDTH
#define MRV_MI_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU
#define MRV_MI_DMA_Y_PIC_WIDTH_SHIFT 0U
/*! Register: mi_dma_y_llength: Y component original line length (0x000000d0)*/
/*! Slice: dma_y_llength:*/
/*! Line length of the Y component of the original image in memory */
/* For an uncropped image, where lines follow each other without offset (no line stride), line length must match image width.*/
/* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4.*/
/* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr line length is used.*/
#define MRV_MI_DMA_Y_LLENGTH
#define MRV_MI_DMA_Y_LLENGTH_MASK 0x00007FFFU
#define MRV_MI_DMA_Y_LLENGTH_SHIFT 0U
/*! Register: mi_dma_y_pic_size: Y component image size (0x000000d4)*/
/*! Slice: dma_y_pic_size:*/
/*! Image size of the Y component in pixel which has to be the Y line length multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/
/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb component (which includes Cr) is assumed half for 4:2:0 and the same size for 4:2:2. In interleave mode no Cb/Cr image size is used.*/
#define MRV_MI_DMA_Y_PIC_SIZE
#define MRV_MI_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU
#define MRV_MI_DMA_Y_PIC_SIZE_SHIFT 0U
/*! Register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)*/
/*! Slice: dma_cb_pic_start_ad:*/
/*! Image start address of the Cb component */
/* Note: Must be multiple of 2 in semi-planar mode.*/
#define MRV_MI_DMA_CB_PIC_START_AD
#define MRV_MI_DMA_CB_PIC_START_AD_MASK 0xFFFFFFFFU
#define MRV_MI_DMA_CB_PIC_START_AD_SHIFT 0U
/*! Register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)*/
/*! Slice: dma_cr_pic_start_ad:*/
/*! Image start address of the Cr component */
#define MRV_MI_DMA_CR_PIC_START_AD
#define MRV_MI_DMA_CR_PIC_START_AD_MASK 0xFFFFFFFFU
#define MRV_MI_DMA_CR_PIC_START_AD_SHIFT 0U
/*! Register: mi_imsc: Interrupt Mask (1: interrupt active, 0: interrupt masked) (0x000000f8)*/
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Slice mp_handshk_int:*/
/*! Mask bit for mp handshake interrupt */
#define MRV_MI_MP_HANDSHK_INT
#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
#endif
/*! Slice: dma_ready:*/
/*! Mask bit for dma ready interrupt */
#define MRV_MI_DMA_READY
#define MRV_MI_DMA_READY_MASK 0x00000800U
#define MRV_MI_DMA_READY_SHIFT 11U
/*! Slice: wrap_sp_cr:*/
/*! Mask bit for self picture Cr address wrap interrupt */
#define MRV_MI_WRAP_SP_CR
#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
#define MRV_MI_WRAP_SP_CR_SHIFT 9U
/*! Slice: wrap_sp_cb:*/
/*! Mask bit for self picture Cb address wrap interrupt */
#define MRV_MI_WRAP_SP_CB
#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
#define MRV_MI_WRAP_SP_CB_SHIFT 8U
/*! Slice: wrap_sp_y:*/
/*! Mask bit for self picture Y address wrap interrupt */
#define MRV_MI_WRAP_SP_Y
#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
#define MRV_MI_WRAP_SP_Y_SHIFT 7U
/*! Slice: wrap_mp_cr:*/
/*! Mask bit for main picture Cr address wrap interrupt */
#define MRV_MI_WRAP_MP_CR
#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
#define MRV_MI_WRAP_MP_CR_SHIFT 6U
/*! Slice: wrap_mp_cb:*/
/*! Mask bit for main picture Cb address wrap interrupt */
#define MRV_MI_WRAP_MP_CB
#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
#define MRV_MI_WRAP_MP_CB_SHIFT 5U
/*! Slice: wrap_mp_y:*/
/*! Mask bit for main picture Y address wrap interrupt */
#define MRV_MI_WRAP_MP_Y
#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
#define MRV_MI_WRAP_MP_Y_SHIFT 4U
/*! Slice: fill_mp_y:*/
/*! Mask bit for fill level interrupt of main picture Y, JPEG or raw data */
#define MRV_MI_FILL_MP_Y
#define MRV_MI_FILL_MP_Y_MASK 0x00000008U
#define MRV_MI_FILL_MP_Y_SHIFT 3U
/*! Slice: mblk_line:*/
/*! Mask bit for makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM)*/
#define MRV_MI_MBLK_LINE
#define MRV_MI_MBLK_LINE_MASK 0x00000004U
#define MRV_MI_MBLK_LINE_SHIFT 2U
/*! Slice: sp_frame_end:*/
/*! Mask self picture end of frame interrupt */
#define MRV_MI_SP_FRAME_END
#define MRV_MI_SP_FRAME_END_MASK 0x00000002U
#define MRV_MI_SP_FRAME_END_SHIFT 1U
/*! Slice: mp_frame_end:*/
/*! Mask main picture end of frame interrupt */
#define MRV_MI_MP_FRAME_END
#define MRV_MI_MP_FRAME_END_MASK 0x00000001U
#define MRV_MI_MP_FRAME_END_SHIFT 0U
/*! Register: mi_ris: Raw Interrupt Status (0x000000fc)*/
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Slice mp_handshk_int:*/
/*! Raw status of mp handshake interrupt */
#define MRV_MI_MP_HANDSHK_INT
#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
#endif
/*! Slice: dma_ready:*/
/*! Raw status of dma ready interrupt */
#define MRV_MI_DMA_READY
#define MRV_MI_DMA_READY_MASK 0x00000800U
#define MRV_MI_DMA_READY_SHIFT 11U
/*! Slice: wrap_sp_cr:*/
/*! Raw status of self picture Cr address wrap interrupt */
#define MRV_MI_WRAP_SP_CR
#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
#define MRV_MI_WRAP_SP_CR_SHIFT 9U
/*! Slice: wrap_sp_cb:*/
/*! Raw status of self picture Cb address wrap interrupt */
#define MRV_MI_WRAP_SP_CB
#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
#define MRV_MI_WRAP_SP_CB_SHIFT 8U
/*! Slice: wrap_sp_y:*/
/*! Raw status of self picture Y address wrap interrupt */
#define MRV_MI_WRAP_SP_Y
#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
#define MRV_MI_WRAP_SP_Y_SHIFT 7U
/*! Slice: wrap_mp_cr:*/
/*! Raw status of main picture Cr address wrap interrupt */
#define MRV_MI_WRAP_MP_CR
#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
#define MRV_MI_WRAP_MP_CR_SHIFT 6U
/*! Slice: wrap_mp_cb:*/
/*! Raw status of main picture Cb address wrap interrupt */
#define MRV_MI_WRAP_MP_CB
#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
#define MRV_MI_WRAP_MP_CB_SHIFT 5U
/*! Slice: wrap_mp_y:*/
/*! Raw status of main picture Y address wrap interrupt */
#define MRV_MI_WRAP_MP_Y
#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
#define MRV_MI_WRAP_MP_Y_SHIFT 4U
/*! Slice: fill_mp_y:*/
/*! Raw status of fill level interrupt of main picture Y, JPEG or raw data */
#define MRV_MI_FILL_MP_Y
#define MRV_MI_FILL_MP_Y_MASK 0x00000008U
#define MRV_MI_FILL_MP_Y_SHIFT 3U
/*! Slice: mblk_line:*/
/*! Raw status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/
#define MRV_MI_MBLK_LINE
#define MRV_MI_MBLK_LINE_MASK 0x00000004U
#define MRV_MI_MBLK_LINE_SHIFT 2U
/*! Slice: sp_frame_end:*/
/*! Raw status of self picture end of frame interrupt */
#define MRV_MI_SP_FRAME_END
#define MRV_MI_SP_FRAME_END_MASK 0x00000002U
#define MRV_MI_SP_FRAME_END_SHIFT 1U
/*! Slice: mp_frame_end:*/
/*! Raw status of main picture end of frame interrupt */
#define MRV_MI_MP_FRAME_END
#define MRV_MI_MP_FRAME_END_MASK 0x00000001U
#define MRV_MI_MP_FRAME_END_SHIFT 0U
#ifdef ISP_MI_BP
/*! Slice: bp_frame_end:*/
/*! Raw status of bp picture end of frame interrupt */
#define MRV_MI_BP_FRAME_END
#define MRV_MI_BP_FRAME_END_MASK 0x00004000U
#define MRV_MI_BP_FRAME_END_SHIFT 14U
/*! Slice: bp_wr_raw_aligned:*/
#define BP_WR_RAW_ALIGNED
#define BP_WR_RAW_ALIGNED_MASK 0x000000c0U
#define BP_WR_RAW_ALIGNED_SHIFT 6U
/*! Slice: bp_wr_byte_swap:*/
#define BP_WR_BYTE_SWAP
#define BP_WR_BYTE_SWAP_MASK 0x00007000U
#define BP_WR_BYTE_SWAP_SHIFT 12U
/*! Slice: bp_fill_r */
#define MRV_MI_BP_FILL_R
#define MRV_MI_BP_FILL_R_MASK 0x00008000U
#define MRV_MI_BP_FILL_R_SHIFT 15U
/*! Slice: wrap_bp_r:*/
#define MRV_MI_BP_WRAP_R
#define MRV_MI_BP_WRAP_R_MASK 0x00010000U
#define MRV_MI_BP_WRAP_R_SHIFT 16U
/*! Slice: wrap_bp_r:*/
#define MRV_MI_BP_WRAP_R
#define MRV_MI_BP_WRAP_R_MASK 0x00010000U
#define MRV_MI_BP_WRAP_R_SHIFT 16U
/*! Slice: wrap_bp_gr:*/
#define MRV_MI_BP_WRAP_GR
#define MRV_MI_BP_WRAP_GR_MASK 0x00020000U
#define MRV_MI_BP_WRAP_GR_SHIFT 17U
/*! Slice: wrap_bp_gb:*/
#define MRV_MI_BP_WRAP_GB
#define MRV_MI_BP_WRAP_GB_MASK 0x00040000U
#define MRV_MI_BP_WRAP_GB_SHIFT 18U
/*! Slice: wrap_bp_b:*/
#define MRV_MI_BP_WRAP_B
#define MRV_MI_BP_WRAP_B_MASK 0x00080000U
#define MRV_MI_BP_WRAP_B_SHIFT 19U
/*! Register: miv1_bp_r_base_ad_init (0x000015d8)*/
/*! Slice: bp_r_base_ad_init:*/
#define BP_R_BASE_AD_INIT
#define BP_R_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define BP_R_BASE_AD_INIT_SHIFT 3U
/*! Register: miv1_bp_gr_base_ad_init (0x000015dc)*/
/*! Slice: bp_gr_base_ad_init:*/
#define BP_GR_BASE_AD_INIT
#define BP_GR_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define BP_GR_BASE_AD_INIT_SHIFT 3U
/*! Register: miv1_bp_gb_base_ad_init (0x000015e0)*/
/*! Slice: bp_gb_base_ad_init:*/
#define BP_GB_BASE_AD_INIT
#define BP_GB_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define BP_GB_BASE_AD_INIT_SHIFT 3U
/*! Register: miv1_bp_b_base_ad_init (0x000015e4)*/
/*! Slice: bp_b_base_ad_init:*/
#define BP_B_BASE_AD_INIT
#define BP_B_BASE_AD_INIT_MASK 0xFFFFFFF8U
#define BP_B_BASE_AD_INIT_SHIFT 3U
/*! Register: miv1_bp_r_offs_cnt_init (0x000015c8)*/
/*! Slice: bp_r_offs_cnt_init:*/
#define BP_R_OFFS_CNT_INIT
#define BP_R_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define BP_R_OFFS_CNT_INIT_SHIFT 3U
/*! Register: miv1_bp_gr_offs_cnt_init (0x000015cc)*/
/*! Slice: bp_gr_offs_cnt_init:*/
#define BP_GR_OFFS_CNT_INIT
#define BP_GR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define BP_GR_OFFS_CNT_INIT_SHIFT 3U
/*! Register: miv1_bp_gb_offs_cnt_init (0x000015d0)*/
/*! Slice: bp_gb_offs_cnt_init:*/
#define BP_GB_OFFS_CNT_INIT
#define BP_GB_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define BP_GB_OFFS_CNT_INIT_SHIFT 3U
/*! Register: miv1_bp_b_offs_cnt_init (0x000015d4)*/
/*! Slice: bp_b_offs_cnt_init:*/
#define BP_B_OFFS_CNT_INIT
#define BP_B_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define BP_B_OFFS_CNT_INIT_SHIFT 3U
/*! Register: miv1_bp_wr_offs_cnt_init (0x000015A4)*/
/*! Slice: mi_bp_wr_offs_cnt_init:*/
#define BP_PIC_WR_OFFS_CNT_INIT
#define BP_PIC_WR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
#define BP_PIC_WR_OFFS_CNT_INIT_SHIFT 3U
/*! Register: miv1_bp_wr_irq_offs_init (0x000015AC)*/
/*! Slice: mi_bp_wr_irq_offs_init:*/
#define BP_PIC_IRQ_OFFS_INIT
#define BP_PIC_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define BP_PIC_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv1_bp_wr_size_init (0x000015B4)*/
/*! Slice: mi_bp_wr_size_init:*/
#define BP_PIC_WR_SIZE_INIT
#define BP_PIC_WR_SIZE_INIT_MASK 0x1FFFFFF8U
#define BP_PIC_WR_SIZE_INIT_SHIFT 3U
/*! Register: miv1_bp_pic_width (0x000015bc)*/
/*! Slice: bp_pic_width:*/
#define BP_PIC_WIDTH
#define BP_PIC_WIDTH_MASK 0x4FFFU
#define BP_PIC_WIDTH_SHIFT 0U
/*! Register: miv1_bp_pic_height (0x000015c0)*/
/*! Slice: bp_pic_height:*/
#define BP_PIC_HEIGHT
#define BP_PIC_HEIGHT_MASK 0x4FFFU
#define BP_PIC_HEIGHT_SHIFT 0U
/*! Register: miv1_bp_pic_size (0x000015c4)*/
/*! Slice: bp_pic_size:*/
#define BP_PIC_SIZE
#define BP_PIC_SIZE_MASK 0x1FFFFFFU
#define BP_PIC_SIZE_SHIFT 0U
#endif
/*! Register: mi_mis: Masked Interrupt Status (0x00000100)*/
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Slice mp_handshk_int:*/
/*! Masked status for mp handshake interrupt */
#define MRV_MI_MP_HANDSHK_INT
#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
#endif
/*! Slice: dma_ready:*/
/*! Masked status of dma ready interrupt */
#define MRV_MI_DMA_READY
#define MRV_MI_DMA_READY_MASK 0x00000800U
#define MRV_MI_DMA_READY_SHIFT 11U
/*! Slice: wrap_sp_cr:*/
/*! Masked status of self picture Cr address wrap interrupt */
#define MRV_MI_WRAP_SP_CR
#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
#define MRV_MI_WRAP_SP_CR_SHIFT 9U
/*! Slice: wrap_sp_cb:*/
/*! Masked status of self picture Cb address wrap interrupt */
#define MRV_MI_WRAP_SP_CB
#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
#define MRV_MI_WRAP_SP_CB_SHIFT 8U
/*! Slice: wrap_sp_y:*/
/*! Masked status of self picture Y address wrap interrupt */
#define MRV_MI_WRAP_SP_Y
#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
#define MRV_MI_WRAP_SP_Y_SHIFT 7U
/*! Slice: wrap_mp_cr:*/
/*! Masked status of main picture Cr address wrap interrupt */
#define MRV_MI_WRAP_MP_CR
#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
#define MRV_MI_WRAP_MP_CR_SHIFT 6U
/*! Slice: wrap_mp_cb:*/
/*! Masked status of main picture Cb address wrap interrupt */
#define MRV_MI_WRAP_MP_CB
#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
#define MRV_MI_WRAP_MP_CB_SHIFT 5U
/*! Slice: wrap_mp_y:*/
/*! Masked status of main picture Y address wrap interrupt */
#define MRV_MI_WRAP_MP_Y
#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
#define MRV_MI_WRAP_MP_Y_SHIFT 4U
/*! Slice: fill_mp_y:*/
/*! Masked status of fill level interrupt of main picture Y, JPEG or raw data */
#define MRV_MI_FILL_MP_Y
#define MRV_MI_FILL_MP_Y_MASK 0x00000008U
#define MRV_MI_FILL_MP_Y_SHIFT 3U
/*! Slice: mblk_line:*/
/*! Masked status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/
#define MRV_MI_MBLK_LINE
#define MRV_MI_MBLK_LINE_MASK 0x00000004U
#define MRV_MI_MBLK_LINE_SHIFT 2U
/*! Slice: sp_frame_end:*/
/*! Masked status of self picture end of frame interrupt */
#define MRV_MI_SP_FRAME_END
#define MRV_MI_SP_FRAME_END_MASK 0x00000002U
#define MRV_MI_SP_FRAME_END_SHIFT 1U
/*! Slice: mp_frame_end:*/
/*! Masked status of main picture end of frame interrupt */
#define MRV_MI_MP_FRAME_END
#define MRV_MI_MP_FRAME_END_MASK 0x00000001U
#define MRV_MI_MP_FRAME_END_SHIFT 0U
/*! Register: mi_icr: Interrupt Clear Register (0x00000104)*/
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Slice mp_handshk_int:*/
/*! clear mp handshake interrupt */
#define MRV_MI_MP_HANDSHK_INT
#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
#endif
/*! Slice: dma_ready:*/
/*! Clear dma ready interrupt */
#define MRV_MI_DMA_READY
#define MRV_MI_DMA_READY_MASK 0x00000800U
#define MRV_MI_DMA_READY_SHIFT 11U
/*! Slice: wrap_sp_cr:*/
/*! Clear self picture Cr address wrap interrupt */
#define MRV_MI_WRAP_SP_CR
#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
#define MRV_MI_WRAP_SP_CR_SHIFT 9U
/*! Slice: wrap_sp_cb:*/
/*! Clear self picture Cb address wrap interrupt */
#define MRV_MI_WRAP_SP_CB
#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
#define MRV_MI_WRAP_SP_CB_SHIFT 8U
/*! Slice: wrap_sp_y:*/
/*! Clear self picture Y address wrap interrupt */
#define MRV_MI_WRAP_SP_Y
#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
#define MRV_MI_WRAP_SP_Y_SHIFT 7U
/*! Slice: wrap_mp_cr:*/
/*! Clear main picture Cr address wrap interrupt */
#define MRV_MI_WRAP_MP_CR
#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
#define MRV_MI_WRAP_MP_CR_SHIFT 6U
/*! Slice: wrap_mp_cb:*/
/*! Clear main picture Cb address wrap interrupt */
#define MRV_MI_WRAP_MP_CB
#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
#define MRV_MI_WRAP_MP_CB_SHIFT 5U
/*! Slice: wrap_mp_y:*/
/*! Clear main picture Y address wrap interrupt */
#define MRV_MI_WRAP_MP_Y
#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
#define MRV_MI_WRAP_MP_Y_SHIFT 4U
/*! Slice: fill_mp_y:*/
/*! Clear fill level interrupt */
#define MRV_MI_FILL_MP_Y
#define MRV_MI_FILL_MP_Y_MASK 0x00000008U
#define MRV_MI_FILL_MP_Y_SHIFT 3U
/*! Slice: mblk_line:*/
/*! Clear makroblock line interrupt */
#define MRV_MI_MBLK_LINE
#define MRV_MI_MBLK_LINE_MASK 0x00000004U
#define MRV_MI_MBLK_LINE_SHIFT 2U
/*! Slice: sp_frame_end:*/
/*! Clear self picture end of frame interrupt */
#define MRV_MI_SP_FRAME_END
#define MRV_MI_SP_FRAME_END_MASK 0x00000002U
#define MRV_MI_SP_FRAME_END_SHIFT 1U
/*! Slice: mp_frame_end:*/
/*! Clear main picture end of frame interrupt */
#define MRV_MI_MP_FRAME_END
#define MRV_MI_MP_FRAME_END_MASK 0x00000001U
#define MRV_MI_MP_FRAME_END_SHIFT 0U
/*! Register: mi_isr: Interrupt Set Register (0x00000108)*/
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Slice mp_handshk_int:*/
/*! Set mp handshake interrupt */
#define MRV_MI_MP_HANDSHK_INT
#define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
#define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
#endif
/*! Slice: dma_ready:*/
/*! Set dma ready interrupt */
#define MRV_MI_DMA_READY
#define MRV_MI_DMA_READY_MASK 0x00000800U
#define MRV_MI_DMA_READY_SHIFT 11U
/*! Slice: wrap_sp_cr:*/
/*! Set self picture Cr address wrap interrupt */
#define MRV_MI_WRAP_SP_CR
#define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
#define MRV_MI_WRAP_SP_CR_SHIFT 9U
/*! Slice: wrap_sp_cb:*/
/*! Set self picture Cb address wrap interrupt */
#define MRV_MI_WRAP_SP_CB
#define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
#define MRV_MI_WRAP_SP_CB_SHIFT 8U
/*! Slice: wrap_sp_y:*/
/*! Set self picture Y address wrap interrupt */
#define MRV_MI_WRAP_SP_Y
#define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
#define MRV_MI_WRAP_SP_Y_SHIFT 7U
/*! Slice: wrap_mp_cr:*/
/*! Set main picture Cr address wrap interrupt */
#define MRV_MI_WRAP_MP_CR
#define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
#define MRV_MI_WRAP_MP_CR_SHIFT 6U
/*! Slice: wrap_mp_cb:*/
/*! Set main picture Cb address wrap interrupt */
#define MRV_MI_WRAP_MP_CB
#define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
#define MRV_MI_WRAP_MP_CB_SHIFT 5U
/*! Slice: wrap_mp_y:*/
/*! Set main picture Y address wrap interrupt */
#define MRV_MI_WRAP_MP_Y
#define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
#define MRV_MI_WRAP_MP_Y_SHIFT 4U
/*! Slice: fill_mp_y:*/
/*! Set fill level interrupt */
#define MRV_MI_FILL_MP_Y
#define MRV_MI_FILL_MP_Y_MASK 0x00000008U
#define MRV_MI_FILL_MP_Y_SHIFT 3U
/*! Slice: mblk_line:*/
/*! Set makroblock line interrupt */
#define MRV_MI_MBLK_LINE
#define MRV_MI_MBLK_LINE_MASK 0x00000004U
#define MRV_MI_MBLK_LINE_SHIFT 2U
/*! Slice: sp_frame_end:*/
/*! Set self picture end of frame interrupt */
#define MRV_MI_SP_FRAME_END
#define MRV_MI_SP_FRAME_END_MASK 0x00000002U
#define MRV_MI_SP_FRAME_END_SHIFT 1U
/*! Slice: mp_frame_end:*/
/*! Set main picture end of frame interrupt */
#define MRV_MI_MP_FRAME_END
#define MRV_MI_MP_FRAME_END_MASK 0x00000001U
#define MRV_MI_MP_FRAME_END_SHIFT 0U
/*! Register: mi_status: MI Status Register (0x0000010c)*/
/*! Slice: sp_cr_fifo_full:*/
/*! FIFO full flag of Cr FIFO in self path asserted since last clear */
#define MRV_MI_SP_CR_FIFO_FULL
#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U
#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U
/*! Slice: sp_cb_fifo_full:*/
/*! FIFO full flag of Cb FIFO in self path asserted since last clear */
#define MRV_MI_SP_CB_FIFO_FULL
#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U
#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U
/*! Slice: sp_y_fifo_full:*/
/*! FIFO full flag of Y FIFO in self path asserted since last clear */
#define MRV_MI_SP_Y_FIFO_FULL
#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U
#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U
/*! Slice: mp_cr_fifo_full:*/
/*! FIFO full flag of Cr FIFO in main path asserted since last clear */
#define MRV_MI_MP_CR_FIFO_FULL
#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U
#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U
/*! Slice: mp_cb_fifo_full:*/
/*! FIFO full flag of Cb FIFO in main path asserted since last clear */
#define MRV_MI_MP_CB_FIFO_FULL
#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U
#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U
/*! Slice: mp_y_fifo_full:*/
/*! FIFO full flag of Y FIFO in main path asserted since last clear */
#define MRV_MI_MP_Y_FIFO_FULL
#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U
#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U
/*! Register: mi_status_clr: MI Status Clear Register (0x00000110)*/
/*! Slice: sp_cr_fifo_full:*/
/*! Clear status of Cr FIFO full flag in self path */
#define MRV_MI_SP_CR_FIFO_FULL
#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U
#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U
/*! Slice: sp_cb_fifo_full:*/
/*! Clear status of Cb FIFO full flag in self path */
#define MRV_MI_SP_CB_FIFO_FULL
#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U
#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U
/*! Slice: sp_y_fifo_full:*/
/*! Clear status of Y FIFO full flag in self path */
#define MRV_MI_SP_Y_FIFO_FULL
#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U
#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U
/*! Slice: mp_cr_fifo_full:*/
/*! Clear status of Cr FIFO full flag in main path */
#define MRV_MI_MP_CR_FIFO_FULL
#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U
#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U
/*! Slice: mp_cb_fifo_full:*/
/*! Clear status of Cb FIFO full flag in main path */
#define MRV_MI_MP_CB_FIFO_FULL
#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U
#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U
/*! Slice: mp_y_fifo_full:*/
/*! Clear status of Y FIFO full flag in main path */
#define MRV_MI_MP_Y_FIFO_FULL
#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U
#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U
/*! Register: mi_sp_y_pic_width: Y component image width (0x00000114)*/
/*! Slice: sp_y_pic_width:*/
/*! Image width of the self picture Y component or RGB picture in pixel.*/
/* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2. If no line stride is used but flipping required, the image width must be a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar. There are no restrictions for RGB 888/666.*/
/* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/
/* Note: Image width always refers to the picture width of the output image. This is particularly important when rotating.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_Y_PIC_WIDTH
#define MRV_MI_SP_Y_PIC_WIDTH_MASK 0x00007FFFU
#define MRV_MI_SP_Y_PIC_WIDTH_SHIFT 0U
/*! Register: mi_sp_y_pic_height: Y component image height (0x00000118)*/
/*! Slice: sp_y_pic_height:*/
/*! Image height of the y component or RGB picture in pixel.*/
/* In planar and semi planar mode the image width of the cb and cr component is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same for 4:2:2 and 4:4:4.*/
/* Note: Image height always refers to the picture height of the output image. This is particularly important when rotating.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_Y_PIC_HEIGHT
#define MRV_MI_SP_Y_PIC_HEIGHT_MASK 0x00007FFFU
#define MRV_MI_SP_Y_PIC_HEIGHT_SHIFT 0U
/*! Register: mi_sp_y_pic_size: Y component image size (0x0000011c)*/
/*! Slice: sp_y_pic_size:*/
/*! Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/
/* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb and Cr component is assumed half for 4:2:0 and the same size for 4:2:2.*/
/* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
#define MRV_MI_SP_Y_PIC_SIZE
#define MRV_MI_SP_Y_PIC_SIZE_MASK 0x01FFFFFFU
#define MRV_MI_SP_Y_PIC_SIZE_SHIFT 0U
/*! Register: mi_dma_ctrl: DMA control register (0x00000120)*/
/*! Slice: dma_rgb_format:*/
/*! Selects RGB Bayer data of read DMA picture */
/* 00: no DMA RGB Bayer data */
/* 01: 8 bit RGB Bayer data */
/* 10: 16 bit RGB Bayer data (12 bit used)*/
/* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/
/* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/
/* 11: reserved.*/
#define MRV_MI_DMA_RGB_FORMAT
#define MRV_MI_DMA_RGB_FORMAT_MASK 0x00003000U
#define MRV_MI_DMA_RGB_FORMAT_SHIFT 12U
/*! Slice: dma_frame_end_disable:*/
/*! Suppresses v_end so that no frame end can be detected by following instances. Note: The dma_ready interrupt is raised as usual, but the dma_frame_end interrupt will not be generated until v_end has been enabled again.*/
#define MRV_MI_DMA_FRAME_END_DISABLE
#define MRV_MI_DMA_FRAME_END_DISABLE_MASK 0x00000400U
#define MRV_MI_DMA_FRAME_END_DISABLE_SHIFT 10U
/*! Slice: dma_continuous_en:*/
/*! Enables continuous mode. If set the same frame is read back over and over. A start pulse on dma_start is needed only for the first time. To stop continuous mode reset this bit (takes effect after the next frame end) or execute a soft reset. This bit is intended to be used in conjunction with the Superimpose feature.*/
#define MRV_MI_DMA_CONTINUOUS_EN
#define MRV_MI_DMA_CONTINUOUS_EN_MASK 0x00000200U
#define MRV_MI_DMA_CONTINUOUS_EN_SHIFT 9U
/*! Slice: dma_byte_swap:*/
/*! Enables change of DMA byte order of the 32 bit input word at read port */
/* 1: byte order is mirrored but the bit order within one byte doesnt change */
/* 0: no byte mirroring */
#define MRV_MI_DMA_BYTE_SWAP
#define MRV_MI_DMA_BYTE_SWAP_MASK 0x00000100U
#define MRV_MI_DMA_BYTE_SWAP_SHIFT 8U
/*! Slice: dma_inout_format:*/
/*! Selects input/output format of DMA picture.*/
/* 11: YCbCr  4:4:4 */
/* 10: YCbCr  4:2:2 */
/* 01: YCbCr  4:2:0 */
/* 00: YCbCr  4:0:0 */
#define MRV_MI_DMA_INOUT_FORMAT
#define MRV_MI_DMA_INOUT_FORMAT_MASK 0x000000C0U
#define MRV_MI_DMA_INOUT_FORMAT_SHIFT 6U
/*! Slice: dma_read_format:*/
/*! Defines how YCbCr picture data is read from memory.*/
/* 00: planar */
/* 01: semi planar, for YCbCr 4:2:x */
/* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */
/* 11: reserved */
#define MRV_MI_DMA_READ_FORMAT
#define MRV_MI_DMA_READ_FORMAT_MASK 0x00000030U
#define MRV_MI_DMA_READ_FORMAT_SHIFT 4U
/*! Slice: dma_burst_len_chrom:*/
/*! Burst length for Cb or Cr data affecting DMA read port.*/
/* 00: 4-beat bursts */
/* 01: 8-beat bursts */
/* 10: 16-beat bursts */
/* 11: reserved */
/* Ignored if 8- or 16-beat bursts are not supported.*/
#define MRV_MI_DMA_BURST_LEN_CHROM
#define MRV_MI_DMA_BURST_LEN_CHROM_MASK 0x0000000CU
#define MRV_MI_DMA_BURST_LEN_CHROM_SHIFT 2U
/*! Slice: dma_burst_len_lum:*/
/*! Burst length for Y data affecting DMA read port.*/
/* 00: 4-beat bursts */
/* 01: 8-beat bursts */
/* 10: 16-beat bursts */
/* 11: reserved */
/* Ignored if 8- or 16-beat bursts are not supported.*/
#define MRV_MI_DMA_BURST_LEN_LUM
#define MRV_MI_DMA_BURST_LEN_LUM_MASK 0x00000003U
#define MRV_MI_DMA_BURST_LEN_LUM_SHIFT 0U
/*! Register: mi_dma_start: DMA start register (0x00000124)*/
/*! Slice: dma_start:*/
/*! Enables DMA access. Additionally main or self path has to be enabled separately.*/
#define MRV_MI_DMA_START
#define MRV_MI_DMA_START_MASK 0x00000001U
#define MRV_MI_DMA_START_SHIFT 0U
/*! Register: mi_dma_status: DMA status register (0x00000128)*/
/*! Slice: dma_active:*/
/*! If set DMA access is active.*/
#define MRV_MI_DMA_ACTIVE
#define MRV_MI_DMA_ACTIVE_MASK 0x00000001U
#define MRV_MI_DMA_ACTIVE_SHIFT 0U
/*! Register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)*/
/*! Slice: pix_cnt:*/
/*! Counter value specifies the number of pixels of the defect pixel list generated by DPCC of the last transmitted frame. Updated at frame end.*/
/* A soft reset will set the counter to zero.*/
#define MRV_MI_PIX_CNT
#define MRV_MI_PIX_CNT_MASK 0x0FFFFFFFU
#define MRV_MI_PIX_CNT_SHIFT 0U
/*! Register: mi_mp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x00000130)*/
/*! Slice: mp_y_base_ad_init2:*/
/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_MP_Y_BASE_AD_INIT2
#define MRV_MI_MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_MP_Y_BASE_AD_INIT2_SHIFT 3U
/*! Register: mi_mp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000134)*/
/*! Slice: mp_cb_base_ad_init2:*/
/*! 2nd ping pong base address of main picture Cb component buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_MP_CB_BASE_AD_INIT2
#define MRV_MI_MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CB_BASE_AD_INIT2_SHIFT 3U
/*! Register: mi_mp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000138)*/
/*! Slice: mp_cr_base_ad_init2:*/
/*! 2nd ping pong Base address of main picture Cr component buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_MP_CR_BASE_AD_INIT2
#define MRV_MI_MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_MP_CR_BASE_AD_INIT2_SHIFT 3U
/*! Register: mi_sp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x0000013c)*/
/*! Slice: sp_y_base_ad_init2:*/
/*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_Y_BASE_AD_INIT2
#define MRV_MI_SP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_SP_Y_BASE_AD_INIT2_SHIFT 3U
/*! Register: mi_sp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000140)*/
/*! Slice: sp_cb_base_ad_init2:*/
/*! 2nd ping pong base address of main picture Cb component buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CB_BASE_AD_INIT2
#define MRV_MI_SP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CB_BASE_AD_INIT2_SHIFT 3U
/*! Register: mi_sp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000144)*/
/*! Slice: sp_cr_base_ad_init2:*/
/*! 2nd ping pong Base address of main picture Cr component buffer.*/
/* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
/* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
#define MRV_MI_SP_CR_BASE_AD_INIT2
#define MRV_MI_SP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U
#define MRV_MI_SP_CR_BASE_AD_INIT2_SHIFT 3U
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Nano handshake */
/*! Register: isp_handshake_ctrl_0: IspNano handshake functions (0x0000014C)*/
/*! Slice: mp_handshake_en:*/
/*! Enable mp handshake function for MI MP */
#define MRV_MI_MP_HANDSHK_EN
#define MRV_MI_MP_HANDSHK_EN_MASK  0x00000001U
#define MRV_MI_MP_HANDSHK_EN_SHIFT 0U
/*! Slice: mp_handshk_storage_format */
/*! Define how YCbCr picture data is stored in memory */
/*! 00: Planar */
/*! 01: Semi planar, for YCbCr4:2:x */
/*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/
/*! 11: not support */
#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT
#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_MASK 0x00000006U
#define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SHIFT 1U
/*! Slice: mp_handshk_data_format */
/*! Defines the video format */
/*! 00: RAW format */
/*! 01: reserved */
/*! 10: YUV 422 */
/*! 11: YUV 420 */
#define MRV_MI_MP_HANDSHK_DATA_FORMAT
#define MRV_MI_MP_HANDSHK_DATA_FORMAT_MASK 0x00000018U
#define MRV_MI_MP_HANDSHK_DATA_FORMAT_SHIFT 3U
/*! Slice: mp_handshk_slice_size */
/*! Defines the slice size to generate handshake signals, minus 1 is used */
#define MRV_MI_MP_HANDSHK_SLICE_SIZE
#define MRV_MI_MP_HANDSHK_SLICE_SIZE_MASK 0x00001FE0U
#define MRV_MI_MP_HANDSHK_SLICE_SIZE_SHIFT 5U
/*! Slice: mp_handshk_slice_buf_size */
/*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */
#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE
#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_MASK 0x001FE000U
#define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_SHIFT 13U
/*! Slice: mp_handshk_ack_count */
/*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/
#define MRV_MI_MP_HANDSHK_ACK_COUNT
#define MRV_MI_MP_HANDSHK_ACK_COUNT_MASK 0x1FE00000U
#define MRV_MI_MP_HANDSHK_ACK_COUNT_SHIFT 21U
/*! Register: isp_handshake_mp_y_llength: IspNano handshake y_llength (0x00000150)*/
/*! Slice: mp_y_llength, line length of main picture Y component or RGB picture in pixel.*/
/*!     Also knows as line stride, if no line stride is used, the line length must match image width.*/
#define MRV_MI_MP_HANDSHK_Y_LLENGTH
#define MRV_MI_MP_HANDSHK_Y_LLENGTH_MASK 0x00007FFFU
#define MRV_MI_MP_HANDSHK_Y_LLENGTH_SHIFT 0U
/*! Register: isp_handshake_y_slice_offset: IspNano handshake y slice offset (0x00000154)*/
/*! Slice: mp_y_slice_offset defines the offset bewteen two successive Y slice input buffers in bytes.*/
#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET
#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_MASK 0xFFFFFFF8U
#define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_SHIFT 0U
/*! Register: isp_handshake_c_slice_offset: ISPNano handshake c slice offset (ox00000158)*/
/*! Slice: mp_c_slice_offset defines the offset between two successive Cb/Cr slice input buffers in bytes.*/
#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET
#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_MASK 0xFFFFFFF8U
#define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_SHIFT 0U
#endif
#ifdef ISP_MI_ALIGN_NANO
/*! Register mi_output_align_format for isp nano: (0x0000015C)*/
/*! Slice mp_lsb_alignment:*/
/*! msb/lsb align for raw 10 and raw 12 formats control */
/*! 0: MSB aligned for RAW10 and RAW12 formats */
/*! 1: LSB aligned for RAW10 and RAW12 formats */
#define MRV_MI_LSB_ALIGNMENT
#define MRV_MI_LSB_ALIGNMENT_MASK 0x00000001U
#define MRV_MI_LSB_ALIGNMENT_SHIFT 0U
#endif
#ifdef ISP_MI_BYTESWAP
/*! Slice mp_byte_swap:*/
/*! swap bytes for ISP Nano */
/*! bit 0 to swap bytes */
/*! bit 1 to swap words */
/*! bit 2 to swap dwords */
/*! 3'b001: ABCDEFGH => BADCFEHG */
/*! 3'b000: ABCDEFGH => ABCDEFGH */
/*! 3'b010: ABCDEFGH => CDABGHEF */
/*! 3'b011: ABCDEFGH => DCBAHGFE */
/*! 3'b100: ABCDEFGH => EFGHABCD */
/*! 3'b101: ABCDEFGH => FEHGBADC */
/*! 3'b110: ABCDEFGH => GHEFCDAB */
/*! 3'b111: ABCDEFGH => HGFEDCBA */
#define MRV_MI_MP_BYTE_SWAP
#define MRV_MI_MP_BYTE_SWAP_MASK 0x0000000EU
#define MRV_MI_MP_BYTE_SWAP_SHIFT 1U
#endif
#ifdef ISP_MI_FIFO_DEPTH_NANO
/*! Register mi_mp_output_fifo_size for isp nano: (0x00000160)*/
/*! Slice output_fifo_depth:*/
/*! Select output FIFO depth setting */
/*! 00: FULL(2KBytes)*/
/*! 01: HALF(1KBytes)*/
/*! 10: 1/4(512Bytes)*/
/*! 11: 1/8(256Bytes)*/
#define MRV_MI_OUTOUT_FIFO_DEPTH
#define MRV_MI_OUTOUT_FIFO_DEPTH_MASK 0x00000003U
#define MRV_MI_OUTOUT_FIFO_DEPTH_SHIFT 0U
#endif
#ifdef ISP_MI_HANDSHAKE_NANO
/*! Register mi_mp_y_pic_width: IspNano handshake mp_y_pic_width (0x00000164)*/
/*! Slice mi_mp_y_pic_width:*/
/*! Image width of the main picture Y component in pixel.*/
#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH
#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_SHIFT 0U
/*! Register mi_mp_y_pic_height: IspNano handshake mp_y_pic_height (0x00000168)*/
/*! Slice mi_mp_y_pic_height:*/
/*! Image height of the main picture Y component in pixel.*/
#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT
#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_SHIFT 0U
/*! Register mi_mp_y_pic_size: IspNano handshake mp_y_pic_size (0x0000016C)*/
/*! Slice mi_mp_y_pic_size */
/*! Image size of the Y component in pixel which has to be the Y line length multipled by */
/*! the Y image height(mp_y_llength*mp_y_pic_height)*/
#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE
#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_MASK 0xFFFFFFFFU
#define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_SHIFT 0U
#endif
/*! Register: jpe_gen_header: command to start stream header generation (0x00000000)*/
/*! Slice: gen_header:*/
/*! "1" = Start command to generate stream header;*/
/* auto reset to zero after one clock cycle */
#define MRV_JPE_GEN_HEADER
#define MRV_JPE_GEN_HEADER_MASK 0x00000001U
#define MRV_JPE_GEN_HEADER_SHIFT 0U
/*! Register: jpe_encode: Start command to start JFIF stream encoding (0x00000004)*/
/*! Slice: encode:*/
/*! "1" = Start command to start JFIF stream encoding;*/
/* auto reset to zero after one clock cycle.*/
/* This bit is write-only: reading result is always zero!*/
#define MRV_JPE_ENCODE
#define MRV_JPE_ENCODE_MASK 0x00000001U
#define MRV_JPE_ENCODE_SHIFT 0U
/*! Register: jpe_init: Automatic configuration update (INIT) (0x00000008)*/
/*! Slice: JP_INIT:*/
/*! "1" = Immediate start of JPEG encoder.*/
/* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode" command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/
/* auto reset to zero after one clock cycle !!!*/
#define MRV_JPE_JP_INIT
#define MRV_JPE_JP_INIT_MASK 0x00000001U
#define MRV_JPE_JP_INIT_SHIFT 0U
/*! Register: jpe_y_scale_en: Y value scaling control register (0x0000000c)*/
/*! Slice: y_scale_en:*/
/*! Y scale flag */
/* 1: scaling Y input from[16..235] to[0..255]*/
/* 0: no Y input scaling */
#define MRV_JPE_Y_SCALE_EN
#define MRV_JPE_Y_SCALE_EN_MASK 0x00000001U
#define MRV_JPE_Y_SCALE_EN_SHIFT 0U
/*! Register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)*/
/*! Slice: cbcr_scale_en:*/
/*! Cb/Cr scale flag */
/* 1: scaling Cb/Cr input from[16..240] to[0..255]*/
/* 0: no Cb/Cr input scaling */
#define MRV_JPE_CBCR_SCALE_EN
#define MRV_JPE_CBCR_SCALE_EN_MASK 0x00000001U
#define MRV_JPE_CBCR_SCALE_EN_SHIFT 0U
/*! Register: jpe_table_flush: header generation debug register (0x00000014)*/
/*! Slice: table_flush:*/
/*! header generation debug control flag */
/* (controls transmission of last header bytes if the 64 bit output buffer is not completely filled)*/
/* 1: immediately transmit last header bytes */
/* 0: wait for encoded image data to fill output buffer */
#define MRV_JPE_TABLE_FLUSH
#define MRV_JPE_TABLE_FLUSH_MASK 0x00000001U
#define MRV_JPE_TABLE_FLUSH_SHIFT 0U
/*! Register: jpe_enc_hsize: JPEG codec horizontal image size for encoding (0x00000018)*/
/*! Slice: enc_hsize:*/
/*! JPEG codec horizontal image size for R2B and SGEN blocks.*/
/* Note: If the active camerIC version does not support 64 megapixel only those bits will be used which are required and the respective most significant bits will be ignored. Example: 5MP camerIC uses only bits[12:0] and ignores bits[14:13].*/
#define MRV_JPE_ENC_HSIZE
#define MRV_JPE_ENC_HSIZE_MASK 0x00007FFFU
#define MRV_JPE_ENC_HSIZE_SHIFT 0U
/*! Register: jpe_enc_vsize: JPEG codec vertical image size for encoding (0x0000001c)*/
/*! Slice: enc_vsize:*/
/*! JPEG codec vertical image size for R2B and SGEN blocks */
#define MRV_JPE_ENC_VSIZE
#define MRV_JPE_ENC_VSIZE_MASK 0x00003FFFU
#define MRV_JPE_ENC_VSIZE_SHIFT 0U
/*! Register: jpe_pic_format: JPEG picture encoding format (0x00000020)*/
/*! Slice: enc_pic_format:*/
/*! "0:0:1"  = 4:2:2 format */
/* "1:x:x"  = 4:0:0 format */
#define MRV_JPE_ENC_PIC_FORMAT
#define MRV_JPE_ENC_PIC_FORMAT_MASK 0x00000007U
#define MRV_JPE_ENC_PIC_FORMAT_SHIFT 0U
/*! Register: jpe_restart_interval: restart marker insertion register (0x00000024)*/
/*! Slice: restart_interval:*/
/*! No of MCU in  reset interval via host */
#define MRV_JPE_RESTART_INTERVAL
#define MRV_JPE_RESTART_INTERVAL_MASK 0x0000FFFFU
#define MRV_JPE_RESTART_INTERVAL_SHIFT 0U
/*! Register: jpe_tq_y_select: Q- table selector 0, quant. table for Y component (0x00000028)*/
/*! Slice: tq0_select:*/
/*! "00" = qtable 0 */
/* "01" = qtable 1 */
/* "10" = qtable 2 */
/* "11" = qtable 3 */
#define MRV_JPE_TQ0_SELECT
#define MRV_JPE_TQ0_SELECT_MASK 0x00000003U
#define MRV_JPE_TQ0_SELECT_SHIFT 0U
/*! Register: jpe_tq_u_select: Q- table selector 1, quant. table for U component (0x0000002c)*/
/*! Slice: tq1_select:*/
/*! "00" = qtable 0 */
/* "01" = qtable 1 */
/* "10" = qtable 2 */
/* "11" = qtable 3 */
#define MRV_JPE_TQ1_SELECT
#define MRV_JPE_TQ1_SELECT_MASK 0x00000003U
#define MRV_JPE_TQ1_SELECT_SHIFT 0U
/*! Register: jpe_tq_v_select: Q- table selector 2, quant. table for V component (0x00000030)*/
/*! Slice: tq2_select:*/
/*! "00" = qtable 0 */
/* "01" = qtable 1 */
/* "10" = qtable 2 */
/* "11" = qtable 3 */
#define MRV_JPE_TQ2_SELECT
#define MRV_JPE_TQ2_SELECT_MASK 0x00000003U
#define MRV_JPE_TQ2_SELECT_SHIFT 0U
/*! Register: jpe_dc_table_select: Huffman table selector for DC values (0x00000034)*/
/*! Slice: dc_table_select_v:*/
/*! "0" = dc table 0; color component 2 (V)*/
/* "1" = dc table 1; color component 2 (V)*/
#define MRV_JPE_DC_TABLE_SELECT_V
#define MRV_JPE_DC_TABLE_SELECT_V_MASK 0x00000004U
#define MRV_JPE_DC_TABLE_SELECT_V_SHIFT 2U
/*! Slice: dc_table_select_u:*/
/*! "0" = dc table 0; color component 1 (U)*/
/* "1" = dc table 1; color component 1 (U)*/
#define MRV_JPE_DC_TABLE_SELECT_U
#define MRV_JPE_DC_TABLE_SELECT_U_MASK 0x00000002U
#define MRV_JPE_DC_TABLE_SELECT_U_SHIFT 1U
/*! Slice: dc_table_select_y:*/
/*! "0" = dc table 0; color component 0 (Y)*/
/* "1" = dc table 1; color component 0 (Y)*/
#define MRV_JPE_DC_TABLE_SELECT_Y
#define MRV_JPE_DC_TABLE_SELECT_Y_MASK 0x00000001U
#define MRV_JPE_DC_TABLE_SELECT_Y_SHIFT 0U
/*! Register: jpe_ac_table_select: Huffman table selector for AC values (0x00000038)*/
/*! Slice: ac_table_select_v:*/
/*! "0" = ac table 0; component 2 (V)*/
/* "1" = ac table 1; component 2 (V)*/
#define MRV_JPE_AC_TABLE_SELECT_V
#define MRV_JPE_AC_TABLE_SELECT_V_MASK 0x00000004U
#define MRV_JPE_AC_TABLE_SELECT_V_SHIFT 2U
/*! Slice: ac_table_select_u:*/
/*! "0" = ac table 0; component 1 (U)*/
/* "1" = ac table 1; component 1 (U)*/
#define MRV_JPE_AC_TABLE_SELECT_U
#define MRV_JPE_AC_TABLE_SELECT_U_MASK 0x00000002U
#define MRV_JPE_AC_TABLE_SELECT_U_SHIFT 1U
/*! Slice: ac_table_select_y:*/
/*! "0" = ac table 0; component 0 (Y)*/
/* "1" = ac table 1; component 0 (Y)*/
#define MRV_JPE_AC_TABLE_SELECT_Y
#define MRV_JPE_AC_TABLE_SELECT_Y_MASK 0x00000001U
#define MRV_JPE_AC_TABLE_SELECT_Y_SHIFT 0U
/*! Register: jpe_table_data: table programming register (0x0000003c)*/
/*! Slice: table_wdata_h:*/
/*! Table data MSB */
#define MRV_JPE_TABLE_WDATA_H
#define MRV_JPE_TABLE_WDATA_H_MASK 0x0000FF00U
#define MRV_JPE_TABLE_WDATA_H_SHIFT 8U
/*! Slice: table_wdata_l:*/
/*! Table data LSB */
#define MRV_JPE_TABLE_WDATA_L
#define MRV_JPE_TABLE_WDATA_L_MASK 0x000000FFU
#define MRV_JPE_TABLE_WDATA_L_SHIFT 0U
/*! Register: jpe_table_id: table programming select register (0x00000040)*/
/*! Slice: table_id:*/
/*! select table */
/* "0000" : Q-table 0 */
/* "0001" : Q-table 1 */
/* "0010" : Q-table 2 */
/* "0011" : Q-table 3 */
/* "0100" : VLC DC-table 0 */
/* "0101" : VLC AC-table 0 */
/* "0110" : VLC DC-table 1 */
/* "0111" : VLC AC-table 1 */
/* "1xxx" : reserved for debug */
#define MRV_JPE_TABLE_ID
#define MRV_JPE_TABLE_ID_MASK 0x0000000FU
#define MRV_JPE_TABLE_ID_SHIFT 0U
/*! Register: jpe_tac0_len: Huffman AC table 0 length (0x00000044)*/
/*! Slice: tac0_len:*/
/*! Huffman table length for ac0 table */
#define MRV_JPE_TAC0_LEN
#define MRV_JPE_TAC0_LEN_MASK 0x000000FFU
#define MRV_JPE_TAC0_LEN_SHIFT 0U
/*! Register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)*/
/*! Slice: tdc0_len:*/
/*! Huffman table length for dc0 table */
#define MRV_JPE_TDC0_LEN
#define MRV_JPE_TDC0_LEN_MASK 0x000000FFU
#define MRV_JPE_TDC0_LEN_SHIFT 0U
/*! Register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)*/
/*! Slice: tac1_len:*/
/*! Huffman table length for ac1 table */
#define MRV_JPE_TAC1_LEN
#define MRV_JPE_TAC1_LEN_MASK 0x000000FFU
#define MRV_JPE_TAC1_LEN_SHIFT 0U
/*! Register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)*/
/*! Slice: tdc1_len:*/
/*! Huffman table length for dc1 table */
#define MRV_JPE_TDC1_LEN
#define MRV_JPE_TDC1_LEN_MASK 0x000000FFU
#define MRV_JPE_TDC1_LEN_SHIFT 0U
/*! Register: jpe_encoder_busy: encoder status flag (0x00000058)*/
/*! Slice: codec_busy:*/
/*! Bit 0 = "1" : JPEG codec in process */
#define MRV_JPE_CODEC_BUSY
#define MRV_JPE_CODEC_BUSY_MASK 0x00000001U
#define MRV_JPE_CODEC_BUSY_SHIFT 0U
/*! Register: jpe_header_mode: header mode definition (0x0000005c)*/
/*! Slice: header_mode:*/
/*! "00" = no header */
/* "01" = reserved */
/* "10" = JFIF 1.02 header */
/* "11" = reserved */
#define MRV_JPE_HEADER_MODE
#define MRV_JPE_HEADER_MODE_MASK 0x00000003U
#define MRV_JPE_HEADER_MODE_SHIFT 0U
/*! Register: jpe_encode_mode: encode mode (0x00000060)*/
/*! Slice: encode_mode:*/
/*! Always  "1", because this is the encoder only edition */
#define MRV_JPE_ENCODE_MODE
#define MRV_JPE_ENCODE_MODE_MASK 0x00000001U
#define MRV_JPE_ENCODE_MODE_SHIFT 0U
/*! Register: jpe_debug: debug information register (0x00000064)*/
/*! Slice: deb_bad_table_access:*/
/*! Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID register is performed, when the JPEG_ENCODER is busy. In this case a default PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/
#define MRV_JPE_DEB_BAD_TABLE_ACCESS
#define MRV_JPE_DEB_BAD_TABLE_ACCESS_MASK 0x00000100U
#define MRV_JPE_DEB_BAD_TABLE_ACCESS_SHIFT 8U
/*! Slice: deb_vlc_table_busy:*/
/*! Debug signal only (vlc access to huff-tables)*/
#define MRV_JPE_DEB_VLC_TABLE_BUSY
#define MRV_JPE_DEB_VLC_TABLE_BUSY_MASK 0x00000020U
#define MRV_JPE_DEB_VLC_TABLE_BUSY_SHIFT 5U
/*! Slice: deb_r2b_memory_full:*/
/*! Debug signal only (line memory status of r2b)*/
#define MRV_JPE_DEB_R2B_MEMORY_FULL
#define MRV_JPE_DEB_R2B_MEMORY_FULL_MASK 0x00000010U
#define MRV_JPE_DEB_R2B_MEMORY_FULL_SHIFT 4U
/*! Slice: deb_vlc_encode_busy:*/
/*! Debug signal only (vlc encode processing active)*/
#define MRV_JPE_DEB_VLC_ENCODE_BUSY
#define MRV_JPE_DEB_VLC_ENCODE_BUSY_MASK 0x00000008U
#define MRV_JPE_DEB_VLC_ENCODE_BUSY_SHIFT 3U
/*! Slice: deb_qiq_table_acc:*/
/*! Debug signal only (QIQ table access)*/
#define MRV_JPE_DEB_QIQ_TABLE_ACC
#define MRV_JPE_DEB_QIQ_TABLE_ACC_MASK 0x00000004U
#define MRV_JPE_DEB_QIQ_TABLE_ACC_SHIFT 2U
/*! Register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)*/
/*! Slice: vlc_table_err:*/
/*! "1" = interrupt is  activated (masked in)*/
#define MRV_JPE_VLC_TABLE_ERR
#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
/*! Slice: r2b_IMG_size_err:*/
/*! "1" = interrupt is  activated (masked in)*/
#define MRV_JPE_R2B_IMG_SIZE_ERR
#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
/*! Slice: DCT_ERR:*/
/*! "1" = interrupt is  activated (masked in)*/
#define MRV_JPE_DCT_ERR
#define MRV_JPE_DCT_ERR_MASK 0x00000080U
#define MRV_JPE_DCT_ERR_SHIFT 7U
/*! Slice: vlc_symbol_err:*/
/*! "1" = interrupt is  activated (masked in)*/
#define MRV_JPE_VLC_SYMBOL_ERR
#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
/*! Register: jpe_error_ris: JPEG error raw  interrupt status register (0x0000006c)*/
/*! Slice: vlc_table_err:*/
/*! "1" = illegal table detected */
#define MRV_JPE_VLC_TABLE_ERR
#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
/*! Slice: r2b_IMG_size_err:*/
/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/
#define MRV_JPE_R2B_IMG_SIZE_ERR
#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
/*! Slice: DCT_ERR:*/
/*! "1" =  block start mismatch */
#define MRV_JPE_DCT_ERR
#define MRV_JPE_DCT_ERR_MASK 0x00000080U
#define MRV_JPE_DCT_ERR_SHIFT 7U
/*! Slice: vlc_symbol_err:*/
/*! "1" = illegal symbol detected (encoding)*/
#define MRV_JPE_VLC_SYMBOL_ERR
#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
/*! Register: jpe_error_mis: JPEG error masked interrupt status register (0x00000070)*/
/*! Slice: vlc_table_err:*/
/*! "1" = illegal table detected */
#define MRV_JPE_VLC_TABLE_ERR
#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
/*! Slice: r2b_IMG_size_err:*/
/*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/
#define MRV_JPE_R2B_IMG_SIZE_ERR
#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
/*! Slice: DCT_ERR:*/
/*! "1" =  block start mismatch */
#define MRV_JPE_DCT_ERR
#define MRV_JPE_DCT_ERR_MASK 0x00000080U
#define MRV_JPE_DCT_ERR_SHIFT 7U
/*! Slice: vlc_symbol_err:*/
/*! "1" = illegal symbol detected (encoding)*/
#define MRV_JPE_VLC_SYMBOL_ERR
#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
/*! Register: jpe_error_icr: JPEG error interrupt set register (0x00000074)*/
/*! Slice: vlc_table_err:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_VLC_TABLE_ERR
#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
/*! Slice: r2b_IMG_size_err:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_R2B_IMG_SIZE_ERR
#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
/*! Slice: DCT_ERR:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_DCT_ERR
#define MRV_JPE_DCT_ERR_MASK 0x00000080U
#define MRV_JPE_DCT_ERR_SHIFT 7U
/*! Slice: vlc_symbol_err:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_VLC_SYMBOL_ERR
#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
/*! Register: jpe_error_isr: JPEG error interrupt clear register (0x00000078)*/
/*! Slice: vlc_table_err:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_VLC_TABLE_ERR
#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
/*! Slice: r2b_IMG_size_err:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_R2B_IMG_SIZE_ERR
#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
/*! Slice: dct_err:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_DCT_ERR
#define MRV_JPE_DCT_ERR_MASK 0x00000080U
#define MRV_JPE_DCT_ERR_SHIFT 7U
/*! Slice: vlc_symbol_err:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_VLC_SYMBOL_ERR
#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
/*! Register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)*/
/*! Slice: gen_header_done:*/
/*! "1" = interrupt is activated (masked in)*/
#define MRV_JPE_GEN_HEADER_DONE
#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
/*! Slice: encode_done:*/
/*! "1" = interrupt is activated (masked in)*/
#define MRV_JPE_ENCODE_DONE
#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
#define MRV_JPE_ENCODE_DONE_SHIFT 4U
/*! Register: jpe_status_ris: JPEG status raw interrupt status register (0x00000080)*/
/*! Slice: gen_header_done:*/
/*! "1" = Stream header generation finished */
#define MRV_JPE_GEN_HEADER_DONE
#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
/*! Slice: encode_done:*/
/*! "1" = Encode processing finished */
#define MRV_JPE_ENCODE_DONE
#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
#define MRV_JPE_ENCODE_DONE_SHIFT 4U
/*! Register: jpe_status_mis: JPEG status masked interrupt status register (0x00000084)*/
/*! Slice: gen_header_done:*/
/*! "1" = Stream header generation finished */
#define MRV_JPE_GEN_HEADER_DONE
#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
/*! Slice: encode_done:*/
/*! "1" = Encode processing finished */
#define MRV_JPE_ENCODE_DONE
#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
#define MRV_JPE_ENCODE_DONE_SHIFT 4U
/*! Register: jpe_status_icr: JPEG status interrupt clear register (0x00000088)*/
/*! Slice: gen_header_done:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_GEN_HEADER_DONE
#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
/*! Slice: encode_done:*/
/*! "1" = clear status bit, bit is reset to zero after 1 clk */
#define MRV_JPE_ENCODE_DONE
#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
#define MRV_JPE_ENCODE_DONE_SHIFT 4U
/*! Register: jpe_status_isr: JPEG status interrupt set register (0x0000008c)*/
/*! Slice: gen_header_done:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_GEN_HEADER_DONE
#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
/*! Slice: encode_done:*/
/*! "1" = set error bit, bit is reset to zero after 1 clk */
#define MRV_JPE_ENCODE_DONE
#define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
#define MRV_JPE_ENCODE_DONE_SHIFT 4U
/*! Register: jpe_config: JPEG configuration register (0x00000090)*/
/*! Slice: speedview_en:*/
/*! 1: speed view enabled */
/* 0: speed view disabled */
#define MRV_JPE_SPEEDVIEW_EN
#define MRV_JPE_SPEEDVIEW_EN_MASK 0x00000010U
#define MRV_JPE_SPEEDVIEW_EN_SHIFT 4U
/*! Slice: cont_mode:*/
/*! Encoder continous mode */
/* "00": encoder stops at frame end (corresponds to former behavior)*/
/* "01": encoder starts automatically to encode the next frame */
/* "10": unused */
/* "11": encoder first generates next header and then encodes automatically the next frame */
/* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/
#define MRV_JPE_CONT_MODE
#define MRV_JPE_CONT_MODE_MASK 0x00000003U
#define MRV_JPE_CONT_MODE_SHIFT 0U
/*! Register: smia_ctrl: global control register (0x00000000)*/
/*! Slice: DMA_CHANNEL_SEL:*/
/*! DMA channel selector for image data output */
#define MRV_SMIA_DMA_CHANNEL_SEL
#define MRV_SMIA_DMA_CHANNEL_SEL_MASK 0x00000700U
#define MRV_SMIA_DMA_CHANNEL_SEL_SHIFT 8U
/*! Slice: SHUTDOWN_LANE:*/
/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown */
#define MRV_SMIA_SHUTDOWN_LANE
#define MRV_SMIA_SHUTDOWN_LANE_MASK 0x00000008U
#define MRV_SMIA_SHUTDOWN_LANE_SHIFT 3U
/*! Slice: CFG_UPD_ENA:*/
/*! enables generation of cfg_upd signal at frame end */
#define MRV_SMIA_CFG_UPD_ENA
#define MRV_SMIA_CFG_UPD_ENA_MASK 0x00000004U
#define MRV_SMIA_CFG_UPD_ENA_SHIFT 2U
/*! Slice: FLUSH_FIFO:*/
/*! writing '1' resets the write- and read pointers of the embedded data fifo.*/
#define MRV_SMIA_FLUSH_FIFO
#define MRV_SMIA_FLUSH_FIFO_MASK 0x00000002U
#define MRV_SMIA_FLUSH_FIFO_SHIFT 1U
/*! Slice: OUTPUT_ENA:*/
/*! '1': transmission to alomics output interface is enabled */
/* '0': transmission is disabled */
#define MRV_SMIA_OUTPUT_ENA
#define MRV_SMIA_OUTPUT_ENA_MASK 0x00000001U
#define MRV_SMIA_OUTPUT_ENA_SHIFT 0U
/*! Register: smia_status: global status register (0x00000004)*/
/*! Slice: DMA_CHANNEL:*/
/*! DMA channel of currently received packet */
#define MRV_SMIA_DMA_CHANNEL
#define MRV_SMIA_DMA_CHANNEL_MASK 0x00000700U
#define MRV_SMIA_DMA_CHANNEL_SHIFT 8U
/*! Slice: EMB_DATA_AVAIL:*/
/*! 1: embedded data fifo not empty */
#define MRV_SMIA_EMB_DATA_AVAIL
#define MRV_SMIA_EMB_DATA_AVAIL_MASK 0x00000001U
#define MRV_SMIA_EMB_DATA_AVAIL_SHIFT 0U
/*! Register: smia_imsc: Interrupt mask (0x00000008)*/
/*! Slice: IMSC_FIFO_FILL_LEVEL:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL
#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK 0x00000020U
#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_SHIFT 5U
/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW
#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK 0x00000010U
#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_SHIFT 4U
/*! Slice: IMSC_ERR_CS:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_ERR_CS
#define MRV_SMIA_IMSC_ERR_CS_MASK 0x00000008U
#define MRV_SMIA_IMSC_ERR_CS_SHIFT 3U
/*! Slice: IMSC_ERR_PROTOCOL:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_ERR_PROTOCOL
#define MRV_SMIA_IMSC_ERR_PROTOCOL_MASK 0x00000004U
#define MRV_SMIA_IMSC_ERR_PROTOCOL_SHIFT 2U
/*! Slice: IMSC_EMB_DATA_OVFLW:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_EMB_DATA_OVFLW
#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK 0x00000002U
#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_SHIFT 1U
/*! Slice: IMSC_FRAME_END:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_SMIA_IMSC_FRAME_END
#define MRV_SMIA_IMSC_FRAME_END_MASK 0x00000001U
#define MRV_SMIA_IMSC_FRAME_END_SHIFT 0U
/*! Register: smia_ris: Raw interrupt status (0x0000000c)*/
/*! Slice: RIS_FIFO_FILL_LEVEL:*/
/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
#define MRV_SMIA_RIS_FIFO_FILL_LEVEL
#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK 0x00000020U
#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_SHIFT 5U
/*! Slice: RIS_SYNC_FIFO_OVFLW:*/
/*! Sync fifo overflow error */
#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW
#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK 0x00000010U
#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_SHIFT 4U
/*! Slice: RIS_ERR_CS:*/
/*! Checksum error */
#define MRV_SMIA_RIS_ERR_CS
#define MRV_SMIA_RIS_ERR_CS_MASK 0x00000008U
#define MRV_SMIA_RIS_ERR_CS_SHIFT 3U
/*! Slice: RIS_ERR_PROTOCOL:*/
/*! Protocol error */
#define MRV_SMIA_RIS_ERR_PROTOCOL
#define MRV_SMIA_RIS_ERR_PROTOCOL_MASK 0x00000004U
#define MRV_SMIA_RIS_ERR_PROTOCOL_SHIFT 2U
/*! Slice: RIS_EMB_DATA_OVFLW:*/
/*! Embedded data fifo overflow error */
#define MRV_SMIA_RIS_EMB_DATA_OVFLW
#define MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK 0x00000002U
#define MRV_SMIA_RIS_EMB_DATA_OVFLW_SHIFT 1U
/*! Slice: RIS_FRAME_END:*/
/*! Frame end reached */
#define MRV_SMIA_RIS_FRAME_END
#define MRV_SMIA_RIS_FRAME_END_MASK 0x00000001U
#define MRV_SMIA_RIS_FRAME_END_SHIFT 0U
/*! Register: smia_mis: Masked interrupt status (0x00000010)*/
/*! Slice: MIS_FIFO_FILL_LEVEL:*/
/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
#define MRV_SMIA_MIS_FIFO_FILL_LEVEL
#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK 0x00000020U
#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_SHIFT 5U
/*! Slice: MIS_SYNC_FIFO_OVFLW:*/
/*! Sync fifo overflow error */
#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW
#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK 0x00000010U
#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_SHIFT 4U
/*! Slice: MIS_ERR_CS:*/
/*! Checksum error */
#define MRV_SMIA_MIS_ERR_CS
#define MRV_SMIA_MIS_ERR_CS_MASK 0x00000008U
#define MRV_SMIA_MIS_ERR_CS_SHIFT 3U
/*! Slice: MIS_ERR_PROTOCOL:*/
/*! Protocol error */
#define MRV_SMIA_MIS_ERR_PROTOCOL
#define MRV_SMIA_MIS_ERR_PROTOCOL_MASK 0x00000004U
#define MRV_SMIA_MIS_ERR_PROTOCOL_SHIFT 2U
/*! Slice: MIS_EMB_DATA_OVFLW:*/
/*! Embedded data fifo overflow error */
#define MRV_SMIA_MIS_EMB_DATA_OVFLW
#define MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK 0x00000002U
#define MRV_SMIA_MIS_EMB_DATA_OVFLW_SHIFT 1U
/*! Slice: MIS_FRAME_END:*/
/*! Frame end reached */
#define MRV_SMIA_MIS_FRAME_END
#define MRV_SMIA_MIS_FRAME_END_MASK 0x00000001U
#define MRV_SMIA_MIS_FRAME_END_SHIFT 0U
/*! Register: smia_icr: Interrupt clear register (0x00000014)*/
/*! Slice: ICR_FIFO_FILL_LEVEL:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_FIFO_FILL_LEVEL
#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK 0x00000020U
#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_SHIFT 5U
/*! Slice: ICR_SYNC_FIFO_OVFLW:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW
#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK 0x00000010U
#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_SHIFT 4U
/*! Slice: ICR_ERR_CS:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_ERR_CS
#define MRV_SMIA_ICR_ERR_CS_MASK 0x00000008U
#define MRV_SMIA_ICR_ERR_CS_SHIFT 3U
/*! Slice: ICR_ERR_PROTOCOL:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_ERR_PROTOCOL
#define MRV_SMIA_ICR_ERR_PROTOCOL_MASK 0x00000004U
#define MRV_SMIA_ICR_ERR_PROTOCOL_SHIFT 2U
/*! Slice: ICR_EMB_DATA_OVFLW:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_EMB_DATA_OVFLW
#define MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK 0x00000002U
#define MRV_SMIA_ICR_EMB_DATA_OVFLW_SHIFT 1U
/*! Slice: ICR_FRAME_END:*/
/*! Write '1': clear interrupt; Write '0': no effect */
#define MRV_SMIA_ICR_FRAME_END
#define MRV_SMIA_ICR_FRAME_END_MASK 0x00000001U
#define MRV_SMIA_ICR_FRAME_END_SHIFT 0U
/*! Register: smia_isr: Interrupt set register (0x00000018)*/
/*! Slice: ISR_FIFO_FILL_LEVEL:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_FIFO_FILL_LEVEL
#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK 0x00000020U
#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_SHIFT 5U
/*! Slice: ISR_SYNC_FIFO_OVFLW:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW
#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK 0x00000010U
#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_SHIFT 4U
/*! Slice: ISR_ERR_CS:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_ERR_CS
#define MRV_SMIA_ISR_ERR_CS_MASK 0x00000008U
#define MRV_SMIA_ISR_ERR_CS_SHIFT 3U
/*! Slice: ISR_ERR_PROTOCOL:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_ERR_PROTOCOL
#define MRV_SMIA_ISR_ERR_PROTOCOL_MASK 0x00000004U
#define MRV_SMIA_ISR_ERR_PROTOCOL_SHIFT 2U
/*! Slice: ISR_EMB_DATA_OVFLW:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_EMB_DATA_OVFLW
#define MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK 0x00000002U
#define MRV_SMIA_ISR_EMB_DATA_OVFLW_SHIFT 1U
/*! Slice: ISR_FRAME_END:*/
/*! Write '1': set interrupt; Write '0': no effect */
#define MRV_SMIA_ISR_FRAME_END
#define MRV_SMIA_ISR_FRAME_END_MASK 0x00000001U
#define MRV_SMIA_ISR_FRAME_END_SHIFT 0U
/*! Register: smia_data_format_sel: data format selector register (0x0000001c)*/
/*! Slice: DATA_FORMAT_SEL:*/
/*! data format selector:*/
/* 0x0: YUV 422 */
/* 0x1: YUV 420 */
/* 0x4: RGB 444 */
/* 0x5: RGB 565 */
/* 0x6: RGB 888 */
/* 0x8: RAW 6 */
/* 0x9: RAW 7 */
/* 0xA: RAW 8 */
/* 0xB: RAW 10 */
/* 0xC: RAW 12 */
/* 0xD: RAW 8-bit to 10-bit decompression */
/* 0xF: compressed */
/* 0x2, 0x3, 0x7, 0xE: reserved, no output */
#define MRV_SMIA_DATA_FORMAT_SEL
#define MRV_SMIA_DATA_FORMAT_SEL_MASK 0x0000000FU
#define MRV_SMIA_DATA_FORMAT_SEL_SHIFT 0U
/*! Register: smia_sof_emb_data_lines: start of frame embedded data lines register (0x00000020)*/
/*! Slice: SOF_EMB_DATA_LINES:*/
/*! number of embedded data lines at frame start */
#define MRV_SMIA_SOF_EMB_DATA_LINES
#define MRV_SMIA_SOF_EMB_DATA_LINES_MASK 0x00000007U
#define MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT 0U
/*! Register: smia_emb_hstart: embedded data hstart register (0x00000024)*/
/*! Slice: EMB_HSTART:*/
/*! horizontal start position of captured embedded data.*/
/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
#define MRV_SMIA_EMB_HSTART
#define MRV_SMIA_EMB_HSTART_MASK 0x00007FFCU
#define MRV_SMIA_EMB_HSTART_SHIFT 2U
/*! Register: smia_emb_hsize: embedded data hsize register (0x00000028)*/
/*! Slice: EMB_HSIZE:*/
/*! number of captured embedded data dwords per line */
/* '0' means no capturing of embedded data.*/
/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
#define MRV_SMIA_EMB_HSIZE
#define MRV_SMIA_EMB_HSIZE_MASK 0x00007FFCU
#define MRV_SMIA_EMB_HSIZE_SHIFT 2U
/*! Register: smia_emb_vstart: embedded data vstart register (0x0000002c)*/
/*! Slice: EMB_VSTART:*/
/*! start line of embedded data extraction.*/
/* '0' means no capturing of embedded data */
#define MRV_SMIA_EMB_VSTART
#define MRV_SMIA_EMB_VSTART_MASK 0x00003FFFU
#define MRV_SMIA_EMB_VSTART_SHIFT 0U
/*! Register: smia_num_lines: image data lines register (0x00000030)*/
/*! Slice: NUM_LINES:*/
/*! number of image data lines per frame */
#define MRV_SMIA_NUM_LINES
#define MRV_SMIA_NUM_LINES_MASK 0x00003FFFU
#define MRV_SMIA_NUM_LINES_SHIFT 0U
/*! Register: smia_emb_data_fifo: Embedded Data Fifo (0x00000034)*/
/*! Slice: EMB_DATA_FIFO:*/
/*! lowest 4 bytes in embedded data fifo;*/
/* reading increments fifo read pointer.*/
/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
#define MRV_SMIA_EMB_DATA_FIFO
#define MRV_SMIA_EMB_DATA_FIFO_MASK 0xFFFFFFFFU
#define MRV_SMIA_EMB_DATA_FIFO_SHIFT 0U
/*! Register: smia_fifo_fill_level: Embedded Data FIFO Fill Level (0x00000038)*/
/*! Slice: FIFO_FILL_LEVEL:*/
/*! FIFO level in dwords for triggering the fill level interrupt.*/
/* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
#define MRV_SMIA_FIFO_FILL_LEVEL
#define MRV_SMIA_FIFO_FILL_LEVEL_MASK 0x000003FFU
#define MRV_SMIA_FIFO_FILL_LEVEL_SHIFT 0U
/*! Register: mipi_ctrl: global control register (0x00000000)*/
/*! Slice: S_ENABLE_CLK:*/
/*! Sensor clock lane enable signal. This register is directly connected to the output port "s_enableclk".*/
/* '1': enable sensor clock lane (DEFAULT)*/
/* '0': disable sensor clock lane */
#define MRV_MIPI_S_ENABLE_CLK
#define MRV_MIPI_S_ENABLE_CLK_MASK 0x00040000U
#define MRV_MIPI_S_ENABLE_CLK_SHIFT 18U
/*! Slice: ERR_SOT_SYNC_HS_SKIP:*/
/*! 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/
/* 0: ErrSotSyncHS does not affect transmission */
#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP
#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_MASK 0x00020000U
#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_SHIFT 17U
/*! Slice: ERR_SOT_HS_SKIP:*/
/*! 1: data within the current transmission is skipped if ErrSotHS is detected */
/* 0: ErrSotHS does not affect transmission (default)*/
#define MRV_MIPI_ERR_SOT_HS_SKIP
#define MRV_MIPI_ERR_SOT_HS_SKIP_MASK 0x00010000U
#define MRV_MIPI_ERR_SOT_HS_SKIP_SHIFT 16U
/*! Slice: NUM_LANES:*/
/*! 00: Lane 1 is used */
/* 01: Lanes 1 and 2 are used */
/* 10: Lanes 1, 2 and 3 are used */
/* 11: Lanes 1, 2, 3 and 4 are used (default)*/
#define MRV_MIPI_NUM_LANES
#define MRV_MIPI_NUM_LANES_MASK 0x00003000U
#define MRV_MIPI_NUM_LANES_SHIFT 12U
/*! Slice: SHUTDOWN_LANE:*/
/*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0] where n denotes the lane number 1..4 */
#define MRV_MIPI_SHUTDOWN_LANE
#define MRV_MIPI_SHUTDOWN_LANE_MASK 0x00000F00U
#define MRV_MIPI_SHUTDOWN_LANE_SHIFT 8U
/*! Slice: FLUSH_FIFO:*/
/*! writing '1' resets the write- and read pointers of the additional data fifo, reading returns the status of the flush_fifo bit. This bit must be reset by software.*/
#define MRV_MIPI_FLUSH_FIFO
#define MRV_MIPI_FLUSH_FIFO_MASK 0x00000002U
#define MRV_MIPI_FLUSH_FIFO_SHIFT 1U
/*! Slice: OUTPUT_ENA:*/
/*! 1: output to add data fifo and to output interface is enabled */
/* 0: output is disabled */
#define MRV_MIPI_OUTPUT_ENA
#define MRV_MIPI_OUTPUT_ENA_MASK 0x00000001U
#define MRV_MIPI_OUTPUT_ENA_SHIFT 0U
/*! Register: mipi_status: global status register (0x00000004)*/
/*! Slice: S_ULP_ACTIVE_NOT_CLK:*/
/*! sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/
#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK
#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_MASK 0x00002000U
#define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_SHIFT 13U
/*! Slice: S_STOPSTATE_CLK:*/
/*! sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/
#define MRV_MIPI_S_STOPSTATE_CLK
#define MRV_MIPI_S_STOPSTATE_CLK_MASK 0x00001000U
#define MRV_MIPI_S_STOPSTATE_CLK_SHIFT 12U
/*! Slice: STOPSTATE:*/
/*! Data Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0] where n denotes the lane number 1..4 */
#define MRV_MIPI_STOPSTATE
#define MRV_MIPI_STOPSTATE_MASK 0x00000F00U
#define MRV_MIPI_STOPSTATE_SHIFT 8U
/*! Slice: ADD_DATA_AVAIL:*/
/*! 1: additional data fifo contains data */
/* 0: additional data fifo is empty */
#define MRV_MIPI_ADD_DATA_AVAIL
#define MRV_MIPI_ADD_DATA_AVAIL_MASK 0x00000001U
#define MRV_MIPI_ADD_DATA_AVAIL_SHIFT 0U
/*! Register: mipi_imsc: Interrupt mask (0x00000008)*/
/*! Slice: IMSC_GEN_SHORT_PACK:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_GEN_SHORT_PACK
#define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0x08000000U
#define MRV_MIPI_IMSC_GEN_SHORT_PACK_SHIFT 27U
/*! Slice: IMSC_ADD_DATA_FILL_LEVEL:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_SHIFT 26U
/*! Slice: IMSC_ADD_DATA_OVFLW:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ADD_DATA_OVFLW
#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK 0x02000000U
#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_SHIFT 25U
/*! Slice: IMSC_FRAME_END:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_FRAME_END
#define MRV_MIPI_IMSC_FRAME_END_MASK 0x01000000U
#define MRV_MIPI_IMSC_FRAME_END_SHIFT 24U
/*! Slice: IMSC_ERR_CS:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ERR_CS
#define MRV_MIPI_IMSC_ERR_CS_MASK 0x00800000U
#define MRV_MIPI_IMSC_ERR_CS_SHIFT 23U
/*! Slice: IMSC_ERR_ECC1:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ERR_ECC1
#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0x00400000U
#define MRV_MIPI_IMSC_ERR_ECC1_SHIFT 22U
/*! Slice: IMSC_ERR_ECC2:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ERR_ECC2
#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0x00200000U
#define MRV_MIPI_IMSC_ERR_ECC2_SHIFT 21U
/*! Slice: IMSC_ERR_PROTOCOL:*/
/*! enable interrupt (1) or mask out (0)*/
#define MRV_MIPI_IMSC_ERR_PROTOCOL
#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0x00100000U
#define MRV_MIPI_IMSC_ERR_PROTOCOL_SHIFT 20U
/*! Slice: IMSC_ERR_CONTROL:*/
/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
#define MRV_MIPI_IMSC_ERR_CONTROL
#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0x000F0000U
#define MRV_MIPI_IMSC_ERR_CONTROL_SHIFT 16U
/*! Slice: IMSC_ERR_EOT_SYNC:*/
/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
#define MRV_MIPI_IMSC_ERR_EOT_SYNC
#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0x0000F000U
#define MRV_MIPI_IMSC_ERR_EOT_SYNC_SHIFT 12U
/*! Slice: IMSC_ERR_SOT_SYNC:*/
/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
#define MRV_MIPI_IMSC_ERR_SOT_SYNC
#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0x00000F00U
#define MRV_MIPI_IMSC_ERR_SOT_SYNC_SHIFT 8U
/*! Slice: IMSC_ERR_SOT:*/
/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
#define MRV_MIPI_IMSC_ERR_SOT
#define MRV_MIPI_IMSC_ERR_SOT_MASK 0x000000F0U
#define MRV_MIPI_IMSC_ERR_SOT_SHIFT 4U
/*! Slice: IMSC_SYNC_FIFO_OVFLW:*/
/*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW
#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0x0000000FU
#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_SHIFT 0U
/*! Register: mipi_ris: Raw interrupt status (0x0000000c)*/
/*! Slice: RIS_GEN_SHORT_PACK:*/
/*! generic short packet was received (only available in version 2 of MIPI interface)*/
     /**/
/* When this interrupt is cleared, all the bits of the MIPI_GEN_SHORT_DT status register are cleared as well; Setting of this interrupt via MIPI_ISR register will set all the bits of the MIPI_GEN_SHORT_DT register.*/
#define MRV_MIPI_RIS_GEN_SHORT_PACK
#define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0x08000000U
#define MRV_MIPI_RIS_GEN_SHORT_PACK_SHIFT 27U
/*! Slice: RIS_ADD_DATA_FILL_LEVEL:*/
/*! Programmed fill level was reached; will be raised as long as the fill level is greater than the programmed value */
#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_SHIFT 26U
/*! Slice: RIS_ADD_DATA_OVFLW:*/
/*! additional data fifo overflow occurred */
#define MRV_MIPI_RIS_ADD_DATA_OVFLW
#define MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK 0x02000000U
#define MRV_MIPI_RIS_ADD_DATA_OVFLW_SHIFT 25U
/*! Slice: RIS_FRAME_END:*/
/*! frame end send to output interface */
#define MRV_MIPI_RIS_FRAME_END
#define MRV_MIPI_RIS_FRAME_END_MASK 0x01000000U
#define MRV_MIPI_RIS_FRAME_END_SHIFT 24U
/*! Slice: RIS_ERR_CS:*/
/*! checksum error occurred */
#define MRV_MIPI_RIS_ERR_CS
#define MRV_MIPI_RIS_ERR_CS_MASK 0x00800000U
#define MRV_MIPI_RIS_ERR_CS_SHIFT 23U
/*! Slice: RIS_ERR_ECC1:*/
/*! 1-bit ecc error occurred */
#define MRV_MIPI_RIS_ERR_ECC1
#define MRV_MIPI_RIS_ERR_ECC1_MASK 0x00400000U
#define MRV_MIPI_RIS_ERR_ECC1_SHIFT 22U
/*! Slice: RIS_ERR_ECC2:*/
/*! 2-bit ecc error occurred */
#define MRV_MIPI_RIS_ERR_ECC2
#define MRV_MIPI_RIS_ERR_ECC2_MASK 0x00200000U
#define MRV_MIPI_RIS_ERR_ECC2_SHIFT 21U
/*! Slice: RIS_ERR_PROTOCOL:*/
/*! packet start detected within current packet */
#define MRV_MIPI_RIS_ERR_PROTOCOL
#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0x00100000U
#define MRV_MIPI_RIS_ERR_PROTOCOL_SHIFT 20U
/*! Slice: RIS_ERR_CONTROL:*/
/*! PPI interface control error occured, one bit for each lane */
#define MRV_MIPI_RIS_ERR_CONTROL
#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0x000F0000U
#define MRV_MIPI_RIS_ERR_CONTROL_SHIFT 16U
/*! Slice: RIS_ERR_EOT_SYNC:*/
/*! PPI interface eot sync error occured, one bit for each lane */
#define MRV_MIPI_RIS_ERR_EOT_SYNC
#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0x0000F000U
#define MRV_MIPI_RIS_ERR_EOT_SYNC_SHIFT 12U
/*! Slice: RIS_ERR_SOT_SYNC:*/
/*! PPI interface sot sync error occured, one bit for each lane */
#define MRV_MIPI_RIS_ERR_SOT_SYNC
#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0x00000F00U
#define MRV_MIPI_RIS_ERR_SOT_SYNC_SHIFT 8U
/*! Slice: RIS_ERR_SOT:*/
/*! PPI interface sot error occured, one bit for each lane */
#define MRV_MIPI_RIS_ERR_SOT
#define MRV_MIPI_RIS_ERR_SOT_MASK 0x000000F0U
#define MRV_MIPI_RIS_ERR_SOT_SHIFT 4U
/*! Slice: RIS_SYNC_FIFO_OVFLW:*/
/*! synchronization fifo overflow occurred, one bit for each lane */
#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW
#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU
#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_SHIFT 0U
/*! Register: mipi_mis: Masked interrupt status (0x00000010)*/
/*! Slice: MIS_GEN_SHORT_PACK:*/
/*! generic short packet was received (only available in version 2 of MIPI interface)*/
#define MRV_MIPI_MIS_GEN_SHORT_PACK
#define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0x08000000U
#define MRV_MIPI_MIS_GEN_SHORT_PACK_SHIFT 27U
/*! Slice: MIS_ADD_DATA_FILL_LEVEL:*/
/*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_SHIFT 26U
/*! Slice: MIS_ADD_DATA_OVFLW:*/
/*! additional data fifo overflow */
#define MRV_MIPI_MIS_ADD_DATA_OVFLW
#define MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK 0x02000000U
#define MRV_MIPI_MIS_ADD_DATA_OVFLW_SHIFT 25U
/*! Slice: MIS_FRAME_END:*/
/*! frame end send to output interface */
#define MRV_MIPI_MIS_FRAME_END
#define MRV_MIPI_MIS_FRAME_END_MASK 0x01000000U
#define MRV_MIPI_MIS_FRAME_END_SHIFT 24U
/*! Slice: MIS_ERR_CS:*/
/*! checksum error occurred */
#define MRV_MIPI_MIS_ERR_CS
#define MRV_MIPI_MIS_ERR_CS_MASK 0x00800000U
#define MRV_MIPI_MIS_ERR_CS_SHIFT 23U
/*! Slice: MIS_ERR_ECC1:*/
/*! 1-bit ecc error occurred */
#define MRV_MIPI_MIS_ERR_ECC1
#define MRV_MIPI_MIS_ERR_ECC1_MASK 0x00400000U
#define MRV_MIPI_MIS_ERR_ECC1_SHIFT 22U
/*! Slice: MIS_ERR_ECC2:*/
/*! 2-bit ecc error occurred */
#define MRV_MIPI_MIS_ERR_ECC2
#define MRV_MIPI_MIS_ERR_ECC2_MASK 0x00200000U
#define MRV_MIPI_MIS_ERR_ECC2_SHIFT 21U
/*! Slice: MIS_ERR_PROTOCOL:*/
/*! packet start detected within current packet */
#define MRV_MIPI_MIS_ERR_PROTOCOL
#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0x00100000U
#define MRV_MIPI_MIS_ERR_PROTOCOL_SHIFT 20U
/*! Slice: MIS_ERR_CONTROL:*/
/*! PPI interface control error occured, one bit for each lane */
#define MRV_MIPI_MIS_ERR_CONTROL
#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0x000F0000U
#define MRV_MIPI_MIS_ERR_CONTROL_SHIFT 16U
/*! Slice: MIS_ERR_EOT_SYNC:*/
/*! PPI interface eot sync error occured, one bit for each lane */
#define MRV_MIPI_MIS_ERR_EOT_SYNC
#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0x0000F000U
#define MRV_MIPI_MIS_ERR_EOT_SYNC_SHIFT 12U
/*! Slice: MIS_ERR_SOT_SYNC:*/
/*! PPI interface sot sync error occured, one bit for each lane */
#define MRV_MIPI_MIS_ERR_SOT_SYNC
#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0x00000F00U
#define MRV_MIPI_MIS_ERR_SOT_SYNC_SHIFT 8U
/*! Slice: MIS_ERR_SOT:*/
/*! PPI interface sot error occured, one bit for each lane */
#define MRV_MIPI_MIS_ERR_SOT
#define MRV_MIPI_MIS_ERR_SOT_MASK 0x000000F0U
#define MRV_MIPI_MIS_ERR_SOT_SHIFT 4U
/*! Slice: MIS_SYNC_FIFO_OVFLW:*/
/*! synchronization fifo overflow occurred, one bit for each lane */
#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW
#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU
#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_SHIFT 0U
/*! Register: mipi_icr: Interrupt clear register (0x00000014)*/
/*! Slice: ICR_GEN_SHORT_PACK:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_GEN_SHORT_PACK
#define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0x08000000U
#define MRV_MIPI_ICR_GEN_SHORT_PACK_SHIFT 27U
/*! Slice: ICR_ADD_DATA_FILL_LEVEL:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_SHIFT 26U
/*! Slice: ICR_ADD_DATA_OVFLW:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ADD_DATA_OVFLW
#define MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK 0x02000000U
#define MRV_MIPI_ICR_ADD_DATA_OVFLW_SHIFT 25U
/*! Slice: ICR_FRAME_END:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_FRAME_END
#define MRV_MIPI_ICR_FRAME_END_MASK 0x01000000U
#define MRV_MIPI_ICR_FRAME_END_SHIFT 24U
/*! Slice: ICR_ERR_CS:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ERR_CS
#define MRV_MIPI_ICR_ERR_CS_MASK 0x00800000U
#define MRV_MIPI_ICR_ERR_CS_SHIFT 23U
/*! Slice: ICR_ERR_ECC1:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ERR_ECC1
#define MRV_MIPI_ICR_ERR_ECC1_MASK 0x00400000U
#define MRV_MIPI_ICR_ERR_ECC1_SHIFT 22U
/*! Slice: ICR_ERR_ECC2:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ERR_ECC2
#define MRV_MIPI_ICR_ERR_ECC2_MASK 0x00200000U
#define MRV_MIPI_ICR_ERR_ECC2_SHIFT 21U
/*! Slice: ICR_ERR_PROTOCOL:*/
/*! 1: clear register; 0: nothing happens */
#define MRV_MIPI_ICR_ERR_PROTOCOL
#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0x00100000U
#define MRV_MIPI_ICR_ERR_PROTOCOL_SHIFT 20U
/*! Slice: ICR_ERR_CONTROL:*/
/*! 1: clear register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ICR_ERR_CONTROL
#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0x000F0000U
#define MRV_MIPI_ICR_ERR_CONTROL_SHIFT 16U
/*! Slice: ICR_ERR_EOT_SYNC:*/
/*! 1: clear register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ICR_ERR_EOT_SYNC
#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0x0000F000U
#define MRV_MIPI_ICR_ERR_EOT_SYNC_SHIFT 12U
/*! Slice: ICR_ERR_SOT_SYNC:*/
/*! 1: clear register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ICR_ERR_SOT_SYNC
#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0x00000F00U
#define MRV_MIPI_ICR_ERR_SOT_SYNC_SHIFT 8U
/*! Slice: ICR_ERR_SOT:*/
/*! 1: clear register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ICR_ERR_SOT
#define MRV_MIPI_ICR_ERR_SOT_MASK 0x000000F0U
#define MRV_MIPI_ICR_ERR_SOT_SHIFT 4U
/*! Slice: ICR_SYNC_FIFO_OVFLW:*/
/*! 1: clear register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW
#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0x0000000FU
#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_SHIFT 0U
/*! Register: mipi_isr: Interrupt set register (0x00000018)*/
/*! Slice: ISR_GEN_SHORT_PACK:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_GEN_SHORT_PACK
#define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0x08000000U
#define MRV_MIPI_ISR_GEN_SHORT_PACK_SHIFT 27U
/*! Slice: ISR_ADD_DATA_FILL_LEVEL:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_SHIFT 26U
/*! Slice: ISR_ADD_DATA_OVFLW:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ADD_DATA_OVFLW
#define MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK 0x02000000U
#define MRV_MIPI_ISR_ADD_DATA_OVFLW_SHIFT 25U
/*! Slice: ISR_FRAME_END:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_FRAME_END
#define MRV_MIPI_ISR_FRAME_END_MASK 0x01000000U
#define MRV_MIPI_ISR_FRAME_END_SHIFT 24U
/*! Slice: ISR_ERR_CS:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ERR_CS
#define MRV_MIPI_ISR_ERR_CS_MASK 0x00800000U
#define MRV_MIPI_ISR_ERR_CS_SHIFT 23U
/*! Slice: ISR_ERR_ECC1:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ERR_ECC1
#define MRV_MIPI_ISR_ERR_ECC1_MASK 0x00400000U
#define MRV_MIPI_ISR_ERR_ECC1_SHIFT 22U
/*! Slice: ISR_ERR_ECC2:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ERR_ECC2
#define MRV_MIPI_ISR_ERR_ECC2_MASK 0x00200000U
#define MRV_MIPI_ISR_ERR_ECC2_SHIFT 21U
/*! Slice: ISR_ERR_PROTOCOL:*/
/*! 1: set register; 0: nothing happens */
#define MRV_MIPI_ISR_ERR_PROTOCOL
#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0x00100000U
#define MRV_MIPI_ISR_ERR_PROTOCOL_SHIFT 20U
/*! Slice: ISR_ERR_CONTROL:*/
/*! 1: set register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ISR_ERR_CONTROL
#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0x000F0000U
#define MRV_MIPI_ISR_ERR_CONTROL_SHIFT 16U
/*! Slice: ISR_ERR_EOT_SYNC:*/
/*! 1: set register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ISR_ERR_EOT_SYNC
#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0x0000F000U
#define MRV_MIPI_ISR_ERR_EOT_SYNC_SHIFT 12U
/*! Slice: ISR_ERR_SOT_SYNC:*/
/*! 1: set register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ISR_ERR_SOT_SYNC
#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0x00000F00U
#define MRV_MIPI_ISR_ERR_SOT_SYNC_SHIFT 8U
/*! Slice: ISR_ERR_SOT:*/
/*! 1: set register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ISR_ERR_SOT
#define MRV_MIPI_ISR_ERR_SOT_MASK 0x000000F0U
#define MRV_MIPI_ISR_ERR_SOT_SHIFT 4U
/*! Slice: ISR_SYNC_FIFO_OVFLW:*/
/*! 1: set register; 0: nothing happens (one bit for each lane)*/
#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW
#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0x0000000FU
#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_SHIFT 0U
/*! Register: mipi_cur_data_id: Current Data Identifier (0x0000001c)*/
/*! Slice: VIRTUAL_CHANNEL:*/
/*! virtual channel of currently received packet */
#define MRV_MIPI_VIRTUAL_CHANNEL
#define MRV_MIPI_VIRTUAL_CHANNEL_MASK 0x000000C0U
#define MRV_MIPI_VIRTUAL_CHANNEL_SHIFT 6U
/*! Slice: DATA_TYPE:*/
/*! data type of currently received packet */
#define MRV_MIPI_DATA_TYPE
#define MRV_MIPI_DATA_TYPE_MASK 0x0000003FU
#define MRV_MIPI_DATA_TYPE_SHIFT 0U
/*! Register: mipi_img_data_sel: Image Data Selector (0x00000020)*/
/*! Slice: VIRTUAL_CHANNEL_SEL:*/
/*! virtual channel selector for image data output */
#define MRV_MIPI_VIRTUAL_CHANNEL_SEL
#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_MASK 0x000000C0U
#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_SHIFT 6U
/*! Slice: DATA_TYPE_SEL:*/
/*! data type selector for image data output:*/
/* 0x08...0x0F generic short packets */
/* 0x12	embedded 8-bit data */
/* 0x18	YUV 420 8-bit */
/* 0x19	YUV 420 10-bit */
/* 0x1A	Legacy YUV 420 8-bit */
/* 0x1C	YUV 420 8-bit (CSPS)*/
/* 0x1D	YUV 420 10-bit (CSPS)*/
/* 0x1E	YUV 422 8-bit */
/* 0x1F	YUV 422 10-bit */
/* 0x20	RGB 444 */
/* 0x21	RGB 555 */
/* 0x22	RGB 565 */
/* 0x23	RGB 666 */
/* 0x24	RGB 888 */
/* 0x28	RAW 6 */
/* 0x29	RAW 7 */
/* 0x2A	RAW 8 */
/* 0x2B	RAW 10 */
/* 0x2C	RAW 12 */
/* 0x30...0x37 User Defined Byte-based data */
#define MRV_MIPI_DATA_TYPE_SEL
#define MRV_MIPI_DATA_TYPE_SEL_MASK 0x0000003FU
#define MRV_MIPI_DATA_TYPE_SEL_SHIFT 0U
/*! Register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)*/
/*! Slice: ADD_DATA_VC_1:*/
/*! virtual channel selector for additional data output */
#define MRV_MIPI_ADD_DATA_VC_1
#define MRV_MIPI_ADD_DATA_VC_1_MASK 0x000000C0U
#define MRV_MIPI_ADD_DATA_VC_1_SHIFT 6U
/*! Slice: ADD_DATA_TYPE_1:*/
/*! data type selector for additional data output */
#define MRV_MIPI_ADD_DATA_TYPE_1
#define MRV_MIPI_ADD_DATA_TYPE_1_MASK 0x0000003FU
#define MRV_MIPI_ADD_DATA_TYPE_1_SHIFT 0U
/*! Register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)*/
/*! Slice: ADD_DATA_VC_2:*/
/*! virtual channel selector for additional data output */
#define MRV_MIPI_ADD_DATA_VC_2
#define MRV_MIPI_ADD_DATA_VC_2_MASK 0x000000C0U
#define MRV_MIPI_ADD_DATA_VC_2_SHIFT 6U
/*! Slice: ADD_DATA_TYPE_2:*/
/*! data type selector for additional data output */
#define MRV_MIPI_ADD_DATA_TYPE_2
#define MRV_MIPI_ADD_DATA_TYPE_2_MASK 0x0000003FU
#define MRV_MIPI_ADD_DATA_TYPE_2_SHIFT 0U
/*! Register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)*/
/*! Slice: ADD_DATA_VC_3:*/
/*! virtual channel selector for additional data output */
#define MRV_MIPI_ADD_DATA_VC_3
#define MRV_MIPI_ADD_DATA_VC_3_MASK 0x000000C0U
#define MRV_MIPI_ADD_DATA_VC_3_SHIFT 6U
/*! Slice: ADD_DATA_TYPE_3:*/
/*! data type selector for additional data output */
#define MRV_MIPI_ADD_DATA_TYPE_3
#define MRV_MIPI_ADD_DATA_TYPE_3_MASK 0x0000003FU
#define MRV_MIPI_ADD_DATA_TYPE_3_SHIFT 0U
/*! Register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)*/
/*! Slice: ADD_DATA_VC_4:*/
/*! virtual channel selector for additional data output */
#define MRV_MIPI_ADD_DATA_VC_4
#define MRV_MIPI_ADD_DATA_VC_4_MASK 0x000000C0U
#define MRV_MIPI_ADD_DATA_VC_4_SHIFT 6U
/*! Slice: ADD_DATA_TYPE_4:*/
/*! data type selector for additional data output */
#define MRV_MIPI_ADD_DATA_TYPE_4
#define MRV_MIPI_ADD_DATA_TYPE_4_MASK 0x0000003FU
#define MRV_MIPI_ADD_DATA_TYPE_4_SHIFT 0U
/*! Register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)*/
/*! Slice: ADD_DATA_FIFO:*/
/*! lowest 4 bytes in additional data fifo;*/
/* reading increments fifo read pointer.*/
/* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
#define MRV_MIPI_ADD_DATA_FIFO
#define MRV_MIPI_ADD_DATA_FIFO_MASK 0xFFFFFFFFU
#define MRV_MIPI_ADD_DATA_FIFO_SHIFT 0U
/*! Register: mipi_add_data_fill_level: Additional Data FIFO Fill Level (0x00000038)*/
/*! Slice: ADD_DATA_FILL_LEVEL:*/
/*! FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/
/* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
#define MRV_MIPI_ADD_DATA_FILL_LEVEL
#define MRV_MIPI_ADD_DATA_FILL_LEVEL_MASK 0x00001FFFU
#define MRV_MIPI_ADD_DATA_FILL_LEVEL_SHIFT 0U
/*! Register: mipi_compressed_mode: controls processing of compressed raw data types (0x0000003c)*/
/*! Slice: predictor_sel:*/
/*! predictor to be used:*/
/* 0: predictor 1 */
/* 1: predictor 2 */
#define MRV_MIPI_PREDICTOR_SEL
#define MRV_MIPI_PREDICTOR_SEL_MASK 0x00000100U
#define MRV_MIPI_PREDICTOR_SEL_SHIFT 8U
/*! Slice: comp_scheme:*/
/*! data compression scheme:*/
/* 0: 12812 */
/* 1: 12712 */
/* 2: 12612 */
/* 3: 10810 */
/* 4: 10710 */
/* 5: 10610 */
/* 6..7: reserved */
#define MRV_MIPI_COMP_SCHEME
#define MRV_MIPI_COMP_SCHEME_MASK 0x00000070U
#define MRV_MIPI_COMP_SCHEME_SHIFT 4U
/*! Slice: compress_en:*/
/*! 1: enable compressed mode processing */
/* 0: disable compressed mode */
#define MRV_MIPI_COMPRESS_EN
#define MRV_MIPI_COMPRESS_EN_MASK 0x00000001U
#define MRV_MIPI_COMPRESS_EN_SHIFT 0U
/*! Register: mipi_frame: frame number from frame start and frame end short packets (0x00000040)*/
/*! Slice: frame_number_fe:*/
/*! 16 bit frame number from Frame End (FE) short packet */
#define MRV_MIPI_FRAME_NUMBER_FE
#define MRV_MIPI_FRAME_NUMBER_FE_MASK 0xFFFF0000U
#define MRV_MIPI_FRAME_NUMBER_FE_SHIFT 16U
/*! Slice: frame_number_fs:*/
/*! 16 bit frame number from Frame Start (FS) short packet */
#define MRV_MIPI_FRAME_NUMBER_FS
#define MRV_MIPI_FRAME_NUMBER_FS_MASK 0x0000FFFFU
#define MRV_MIPI_FRAME_NUMBER_FS_SHIFT 0U
/*! Register: mipi_gen_short_dt: data type flags for received generic short packets (0x00000044)*/
/*! Slice: GEN_SHORT_DT_0xF:*/
/*! 1: generic short packet of data type 0xF received */
/* 0: data type 0xF not received */
#define MRV_MIPI_GEN_SHORT_DT_0XF
#define MRV_MIPI_GEN_SHORT_DT_0XF_MASK 0x00000080U
#define MRV_MIPI_GEN_SHORT_DT_0XF_SHIFT 7U
/*! Slice: GEN_SHORT_DT_0xE:*/
/*! 1: generic short packet of data type 0xE received */
/* 0: data type 0xE not received */
#define MRV_MIPI_GEN_SHORT_DT_0XE
#define MRV_MIPI_GEN_SHORT_DT_0XE_MASK 0x00000040U
#define MRV_MIPI_GEN_SHORT_DT_0XE_SHIFT 6U
/*! Slice: GEN_SHORT_DT_0xD:*/
/*! 1: generic short packet of data type 0xD received */
/* 0: data type 0xD not received */
#define MRV_MIPI_GEN_SHORT_DT_0XD
#define MRV_MIPI_GEN_SHORT_DT_0XD_MASK 0x00000020U
#define MRV_MIPI_GEN_SHORT_DT_0XD_SHIFT 5U
/*! Slice: GEN_SHORT_DT_0xC:*/
/*! 1: generic short packet of data type 0xC received */
/* 0: data type 0xC not received */
#define MRV_MIPI_GEN_SHORT_DT_0XC
#define MRV_MIPI_GEN_SHORT_DT_0XC_MASK 0x00000010U
#define MRV_MIPI_GEN_SHORT_DT_0XC_SHIFT 4U
/*! Slice: GEN_SHORT_DT_0xB:*/
/*! 1: generic short packet of data type 0xB received */
/* 0: data type 0xB not received */
#define MRV_MIPI_GEN_SHORT_DT_0XB
#define MRV_MIPI_GEN_SHORT_DT_0XB_MASK 0x00000008U
#define MRV_MIPI_GEN_SHORT_DT_0XB_SHIFT 3U
/*! Slice: GEN_SHORT_DT_0xA:*/
/*! 1: generic short packet of data type 0xA received */
/* 0: data type 0xA not received */
#define MRV_MIPI_GEN_SHORT_DT_0XA
#define MRV_MIPI_GEN_SHORT_DT_0XA_MASK 0x00000004U
#define MRV_MIPI_GEN_SHORT_DT_0XA_SHIFT 2U
/*! Slice: GEN_SHORT_DT_0x9:*/
/*! 1: generic short packet of data type 0x9 received */
/* 0: data type 0x9 not received */
#define MRV_MIPI_GEN_SHORT_DT_0X9
#define MRV_MIPI_GEN_SHORT_DT_0X9_MASK 0x00000002U
#define MRV_MIPI_GEN_SHORT_DT_0X9_SHIFT 1U
/*! Slice: GEN_SHORT_DT_0x8:*/
/*! 1: generic short packet of data type 0x8 received */
/* 0: data type 0x8 not received */
#define MRV_MIPI_GEN_SHORT_DT_0X8
#define MRV_MIPI_GEN_SHORT_DT_0X8_MASK 0x00000001U
#define MRV_MIPI_GEN_SHORT_DT_0X8_SHIFT 0U
/*! Register: mipi_gen_short_8_9: data field for generic short packets of data type 0x8 and 0x9 (0x00000048)*/
/*! Slice: data_field_9:*/
/*! 16 bit user defined data field from last generic short packet of data type 0x9 */
#define MRV_MIPI_DATA_FIELD_9
#define MRV_MIPI_DATA_FIELD_9_MASK 0xFFFF0000U
#define MRV_MIPI_DATA_FIELD_9_SHIFT 16U
/*! Slice: data_field_8:*/
/*! 16 bit user defined data field from last generic short packet of data type 0x8 */
#define MRV_MIPI_DATA_FIELD_8
#define MRV_MIPI_DATA_FIELD_8_MASK 0x0000FFFFU
#define MRV_MIPI_DATA_FIELD_8_SHIFT 0U
/*! Register: mipi_gen_short_a_b: data field for generic short packets of data type 0xA and 0xB (0x0000004c)*/
/*! Slice: data_field_B:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xB */
#define MRV_MIPI_DATA_FIELD_B
#define MRV_MIPI_DATA_FIELD_B_MASK 0xFFFF0000U
#define MRV_MIPI_DATA_FIELD_B_SHIFT 16U
/*! Slice: data_field_A:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xA */
#define MRV_MIPI_DATA_FIELD_A
#define MRV_MIPI_DATA_FIELD_A_MASK 0x0000FFFFU
#define MRV_MIPI_DATA_FIELD_A_SHIFT 0U
/*! Register: mipi_gen_short_c_d: data field for generic short packets of data type 0xC and 0xD (0x00000050)*/
/*! Slice: data_field_D:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xD */
#define MRV_MIPI_DATA_FIELD_D
#define MRV_MIPI_DATA_FIELD_D_MASK 0xFFFF0000U
#define MRV_MIPI_DATA_FIELD_D_SHIFT 16U
/*! Slice: data_field_C:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xC */
#define MRV_MIPI_DATA_FIELD_C
#define MRV_MIPI_DATA_FIELD_C_MASK 0x0000FFFFU
#define MRV_MIPI_DATA_FIELD_C_SHIFT 0U
/*! Register: mipi_gen_short_e_f: data field for generic short packets of data type 0xE and 0xF (0x00000054)*/
/*! Slice: data_field_F:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xF */
#define MRV_MIPI_DATA_FIELD_F
#define MRV_MIPI_DATA_FIELD_F_MASK 0xFFFF0000U
#define MRV_MIPI_DATA_FIELD_F_SHIFT 16U
/*! Slice: data_field_E:*/
/*! 16 bit user defined data field from last generic short packet of data type 0xE */
#define MRV_MIPI_DATA_FIELD_E
#define MRV_MIPI_DATA_FIELD_E_MASK 0x0000FFFFU
#define MRV_MIPI_DATA_FIELD_E_SHIFT 0U
/*! Register: isp_afm_ctrl: This is the control register for AF measurement unit (0x00000000)*/
/*! Slice: afm_en:*/
/*! AF measurement enable */
/* 0: AF measurement is disabled */
/* 1: AF measurement is enabled */
/* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/
/* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/
#define MRV_AFM_AFM_EN
#define MRV_AFM_AFM_EN_MASK 0x00000001U
#define MRV_AFM_AFM_EN_SHIFT 0U
/*! Register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)*/
/*! Slice: a_h_l:*/
/*! first pixel of window A (horizontal left row), value must be greater or equal 5 */
#define MRV_AFM_A_H_L
#define MRV_AFM_A_H_L_MASK 0x1FFF0000U
#define MRV_AFM_A_H_L_SHIFT 16U
/*! Slice: a_v_t:*/
/*! first line of window A (vertical top line), value must be greater or equal 2 */
#define MRV_AFM_A_V_T
#define MRV_AFM_A_V_T_MASK 0x00001FFFU
#define MRV_AFM_A_V_T_SHIFT 0U
/*! Register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)*/
/*! Slice: a_h_r:*/
/*! last pixel of window A (horizontal right row)*/
#define MRV_AFM_A_H_R
#define MRV_AFM_A_H_R_MASK 0x1FFF0000U
#define MRV_AFM_A_H_R_SHIFT 16U
/*! Slice: a_v_b:*/
/*! last line of window A (vertical bottom line), value must be lower than (number of lines  2)*/
#define MRV_AFM_A_V_B
#define MRV_AFM_A_V_B_MASK 0x00001FFFU
#define MRV_AFM_A_V_B_SHIFT 0U
/*! Register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)*/
/*! Slice: b_h_l:*/
/*! first pixel of window B (horizontal left row), value must be greater or equal 5 */
#define MRV_AFM_B_H_L
#define MRV_AFM_B_H_L_MASK 0x1FFF0000U
#define MRV_AFM_B_H_L_SHIFT 16U
/*! Slice: b_v_t:*/
/*! first line of window B (vertical top line), value must be greater or equal 2 */
#define MRV_AFM_B_V_T
#define MRV_AFM_B_V_T_MASK 0x00001FFFU
#define MRV_AFM_B_V_T_SHIFT 0U
/*! Register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)*/
/*! Slice: b_h_r:*/
/*! last pixel of window B (horizontal right row)*/
#define MRV_AFM_B_H_R
#define MRV_AFM_B_H_R_MASK 0x1FFF0000U
#define MRV_AFM_B_H_R_SHIFT 16U
/*! Slice: b_v_b:*/
/*! last line of window B (vertical bottom line), value must be lower than (number of lines  2)*/
#define MRV_AFM_B_V_B
#define MRV_AFM_B_V_B_MASK 0x00001FFFU
#define MRV_AFM_B_V_B_SHIFT 0U
/*! Register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)*/
/*! Slice: c_h_l:*/
/*! first pixel of window C (horizontal left row), value must be greater or equal 5 */
#define MRV_AFM_C_H_L
#define MRV_AFM_C_H_L_MASK 0x1FFF0000U
#define MRV_AFM_C_H_L_SHIFT 16U
/*! Slice: c_v_t:*/
/*! first line of window C (vertical top line), value must be greater or equal 2 */
#define MRV_AFM_C_V_T
#define MRV_AFM_C_V_T_MASK 0x00001FFFU
#define MRV_AFM_C_V_T_SHIFT 0U
/*! Register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)*/
/*! Slice: c_h_r:*/
/*! last pixel of window C (horizontal right row)*/
#define MRV_AFM_C_H_R
#define MRV_AFM_C_H_R_MASK 0x1FFF0000U
#define MRV_AFM_C_H_R_SHIFT 16U
/*! Slice: c_v_b:*/
/*! last line of window C (vertical bottom line), value must be lower than (number of lines  2)*/
#define MRV_AFM_C_V_B
#define MRV_AFM_C_V_B_MASK 0x00001FFFU
#define MRV_AFM_C_V_B_SHIFT 0U
/*! Register: isp_afm_thres: Threshold register (0x0000001c)*/
/*! Slice: afm_thres:*/
/*! AF measurement threshold */
/* This register defines a threshold which can be used for minimizing the influence of noise in the measurement result.*/
#define MRV_AFM_AFM_THRES
#define MRV_AFM_AFM_THRES_MASK 0x0000FFFFU
#define MRV_AFM_AFM_THRES_SHIFT 0U
/*! Register: isp_afm_var_shift: Variable shift register (0x00000020)*/
/*! Slice: lum_var_shift:*/
/*! variable shift for luminance summation */
/* The lum_var_shift defines the number of bits for the shift operation of the value of the current pixel before summation. The shift operation is used to avoid a luminance sum overflow.*/
#define MRV_AFM_LUM_VAR_SHIFT
#define MRV_AFM_LUM_VAR_SHIFT_MASK 0x00070000U
#define MRV_AFM_LUM_VAR_SHIFT_SHIFT 16U
/*! Slice: afm_var_shift:*/
/*! variable shift for AF measurement */
/* The afm_var_shift defines the number of bits for the shift operation at the end of the calculation chain. The shift operation is used to avoid an AF measurement sum overflow.*/
#define MRV_AFM_AFM_VAR_SHIFT
#define MRV_AFM_AFM_VAR_SHIFT_MASK 0x00000007U
#define MRV_AFM_AFM_VAR_SHIFT_SHIFT 0U
/*! Register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x00000024)*/
/*! Slice: afm_sum_a:*/
/*! sharpness value of window A */
#define MRV_AFM_AFM_SUM_A
#define MRV_AFM_AFM_SUM_A_MASK 0xFFFFFFFFU
#define MRV_AFM_AFM_SUM_A_SHIFT 0U
/*! Register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x00000028)*/
/*! Slice: afm_sum_b:*/
/*! sharpness value of window B */
#define MRV_AFM_AFM_SUM_B
#define MRV_AFM_AFM_SUM_B_MASK 0xFFFFFFFFU
#define MRV_AFM_AFM_SUM_B_SHIFT 0U
/*! Register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x0000002c)*/
/*! Slice: afm_sum_c:*/
/*! sharpness value of window C */
#define MRV_AFM_AFM_SUM_C
#define MRV_AFM_AFM_SUM_C_MASK 0xFFFFFFFFU
#define MRV_AFM_AFM_SUM_C_SHIFT 0U
/*! Register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x00000030)*/
/*! Slice: afm_lum_a:*/
/*! luminance value of window A */
#define MRV_AFM_AFM_LUM_A
#define MRV_AFM_AFM_LUM_A_MASK 0x00FFFFFFU
#define MRV_AFM_AFM_LUM_A_SHIFT 0U
/*! Register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x00000034)*/
/*! Slice: afm_lum_b:*/
/*! luminance value of window B */
#define MRV_AFM_AFM_LUM_B
#define MRV_AFM_AFM_LUM_B_MASK 0x00FFFFFFU
#define MRV_AFM_AFM_LUM_B_SHIFT 0U
/*! Register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x00000038)*/
/*! Slice: afm_lum_c:*/
/*! luminance value of window C */
#define MRV_AFM_AFM_LUM_C
#define MRV_AFM_AFM_LUM_C_MASK 0x00FFFFFFU
#define MRV_AFM_AFM_LUM_C_SHIFT 0U
/*! Register: isp_lsc_ctrl: Lens shade control (0x00000000)*/
/*! Slice: lsc_en:*/
/*! 0: activation request for lens shading correction */
/* 1: deactivation reqeust for lens shading correction */
/* Activation/Deactivation is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::lsc_enable_status */
#define MRV_LSC_LSC_EN
#define MRV_LSC_LSC_EN_MASK 0x00000001U
#define MRV_LSC_LSC_EN_SHIFT 0U
/*! Register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)*/
/*! Slice: r_ram_addr:*/
/*! table address in RAM for samples of the R color component.*/
/* Will be automatically incremented by each read or write access to the table.*/
/* Valid addresses are in the range 0 to 152.*/
#define MRV_LSC_R_RAM_ADDR
#define MRV_LSC_R_RAM_ADDR_MASK 0x000001FFU
#define MRV_LSC_R_RAM_ADDR_SHIFT 0U
/*! Register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component (0x00000008)*/
/*! Slice: gr_ram_addr:*/
/*! table address in RAM for samples of the G_R color component.*/
/* Will be automatically incremented by each read or write access to the table.*/
#define MRV_LSC_GR_RAM_ADDR
#define MRV_LSC_GR_RAM_ADDR_MASK 0x000001FFU
#define MRV_LSC_GR_RAM_ADDR_SHIFT 0U
/*! Register: isp_lsc_b_table_addr: Table RAM Address for blue component (0x0000000c)*/
/*! Slice: b_ram_addr:*/
/*! table address in RAM for samples of the B color component.*/
/* Will be automatically incremented by each read or write access to the table.*/
#define MRV_LSC_B_RAM_ADDR
#define MRV_LSC_B_RAM_ADDR_MASK 0x000001FFU
#define MRV_LSC_B_RAM_ADDR_SHIFT 0U
/*! Register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component (0x00000010)*/
/*! Slice: gb_ram_addr:*/
/*! table address in RAM for samples of the G_B color component.*/
/* Will be automatically incremented by each read or write access to the table.*/
#define MRV_LSC_GB_RAM_ADDR
#define MRV_LSC_GB_RAM_ADDR_MASK 0x000001FFU
#define MRV_LSC_GB_RAM_ADDR_SHIFT 0U
/*! Register: isp_lsc_r_table_data: Sample table red (0x00000014)*/
/*! Slice: r_sample_1:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_R_SAMPLE_1
#define MRV_LSC_R_SAMPLE_1_MASK 0x00FFF000U
#define MRV_LSC_R_SAMPLE_1_SHIFT 12U
/*! Slice: r_sample_0:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_R_SAMPLE_0
#define MRV_LSC_R_SAMPLE_0_MASK 0x00000FFFU
#define MRV_LSC_R_SAMPLE_0_SHIFT 0U
/*! Register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)*/
/*! Slice: gr_sample_1:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_GR_SAMPLE_1
#define MRV_LSC_GR_SAMPLE_1_MASK 0x00FFF000U
#define MRV_LSC_GR_SAMPLE_1_SHIFT 12U
/*! Slice: gr_sample_0:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_GR_SAMPLE_0
#define MRV_LSC_GR_SAMPLE_0_MASK 0x00000FFFU
#define MRV_LSC_GR_SAMPLE_0_SHIFT 0U
/*! Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)*/
/*! Slice: b_sample_1:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_B_SAMPLE_1
#define MRV_LSC_B_SAMPLE_1_MASK 0x00FFF000U
#define MRV_LSC_B_SAMPLE_1_SHIFT 12U
/*! Slice: b_sample_0:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_B_SAMPLE_0
#define MRV_LSC_B_SAMPLE_0_MASK 0x00000FFFU
#define MRV_LSC_B_SAMPLE_0_SHIFT 0U
/*! Register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)*/
/*! Slice: gb_sample_1:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_GB_SAMPLE_1
#define MRV_LSC_GB_SAMPLE_1_MASK 0x00FFF000U
#define MRV_LSC_GB_SAMPLE_1_SHIFT 12U
/*! Slice: gb_sample_0:*/
/*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
#define MRV_LSC_GB_SAMPLE_0
#define MRV_LSC_GB_SAMPLE_0_MASK 0x00000FFFU
#define MRV_LSC_GB_SAMPLE_0_SHIFT 0U
/*! Register: isp_lsc_xgrad_01: Gradient table x (0x00000024)*/
/*! Slice: xgrad_1:*/
/*! factor for x-gradient calculation of sector 1 */
#define MRV_LSC_XGRAD_1
#define MRV_LSC_XGRAD_1_MASK 0x0FFF0000U
#define MRV_LSC_XGRAD_1_SHIFT 16U
/*! Slice: xgrad_0:*/
/*! factor for x-gradient calculation of sector 0 */
#define MRV_LSC_XGRAD_0
#define MRV_LSC_XGRAD_0_MASK 0x00000FFFU
#define MRV_LSC_XGRAD_0_SHIFT 0U
/*! Register: isp_lsc_xgrad_23: Gradient table x (0x00000028)*/
/*! Slice: xgrad_3:*/
/*! factor for x-gradient calculation of sector 3 */
#define MRV_LSC_XGRAD_3
#define MRV_LSC_XGRAD_3_MASK 0x0FFF0000U
#define MRV_LSC_XGRAD_3_SHIFT 16U
/*! Slice: xgrad_2:*/
/*! factor for x-gradient calculation of sector 2 */
#define MRV_LSC_XGRAD_2
#define MRV_LSC_XGRAD_2_MASK 0x00000FFFU
#define MRV_LSC_XGRAD_2_SHIFT 0U
/*! Register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)*/
/*! Slice: xgrad_5:*/
/*! factor for x-gradient calculation of sector 5 */
#define MRV_LSC_XGRAD_5
#define MRV_LSC_XGRAD_5_MASK 0x0FFF0000U
#define MRV_LSC_XGRAD_5_SHIFT 16U
/*! Slice: xgrad_4:*/
/*! factor for x-gradient calculation of sector 4 */
#define MRV_LSC_XGRAD_4
#define MRV_LSC_XGRAD_4_MASK 0x00000FFFU
#define MRV_LSC_XGRAD_4_SHIFT 0U
/*! Register: isp_lsc_xgrad_67: Gradient table x (0x00000030)*/
/*! Slice: xgrad_7:*/
/*! factor for x-gradient calculation of sector 7 */
#define MRV_LSC_XGRAD_7
#define MRV_LSC_XGRAD_7_MASK 0x0FFF0000U
#define MRV_LSC_XGRAD_7_SHIFT 16U
/*! Slice: xgrad_6:*/
/*! factor for x-gradient calculation of sector 6 */
#define MRV_LSC_XGRAD_6
#define MRV_LSC_XGRAD_6_MASK 0x00000FFFU
#define MRV_LSC_XGRAD_6_SHIFT 0U
/*! Register: isp_lsc_ygrad_01: Gradient table y (0x00000034)*/
/*! Slice: ygrad_1:*/
/*! factor for y-gradient calculation of sector 1 */
#define MRV_LSC_YGRAD_1
#define MRV_LSC_YGRAD_1_MASK 0x0FFF0000U
#define MRV_LSC_YGRAD_1_SHIFT 16U
/*! Slice: ygrad_0:*/
/*! factor for y-gradient calculation of sector 0 */
#define MRV_LSC_YGRAD_0
#define MRV_LSC_YGRAD_0_MASK 0x00000FFFU
#define MRV_LSC_YGRAD_0_SHIFT 0U
/*! Register: isp_lsc_ygrad_23: Gradient table y (0x00000038)*/
/*! Slice: ygrad_3:*/
/*! factor for y-gradient calculation of sector 3 */
#define MRV_LSC_YGRAD_3
#define MRV_LSC_YGRAD_3_MASK 0x0FFF0000U
#define MRV_LSC_YGRAD_3_SHIFT 16U
/*! Slice: ygrad_2:*/
/*! factor for y-gradient calculation of sector 2 */
#define MRV_LSC_YGRAD_2
#define MRV_LSC_YGRAD_2_MASK 0x00000FFFU
#define MRV_LSC_YGRAD_2_SHIFT 0U
/*! Register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)*/
/*! Slice: ygrad_5:*/
/*! factor for y-gradient calculation of sector 5 */
#define MRV_LSC_YGRAD_5
#define MRV_LSC_YGRAD_5_MASK 0x0FFF0000U
#define MRV_LSC_YGRAD_5_SHIFT 16U
/*! Slice: ygrad_4:*/
/*! factor for y-gradient calculation of sector 4 */
#define MRV_LSC_YGRAD_4
#define MRV_LSC_YGRAD_4_MASK 0x00000FFFU
#define MRV_LSC_YGRAD_4_SHIFT 0U
/*! Register: isp_lsc_ygrad_67: Gradient table y (0x00000040)*/
/*! Slice: ygrad_7:*/
/*! factor for y-gradient calculation of sector 7 */
#define MRV_LSC_YGRAD_7
#define MRV_LSC_YGRAD_7_MASK 0x0FFF0000U
#define MRV_LSC_YGRAD_7_SHIFT 16U
/*! Slice: ygrad_6:*/
/*! factor for y-gradient calculation of sector 6 */
#define MRV_LSC_YGRAD_6
#define MRV_LSC_YGRAD_6_MASK 0x00000FFFU
#define MRV_LSC_YGRAD_6_SHIFT 0U
/*! Register: isp_lsc_xsize_01: Size table (0x00000044)*/
/*! Slice: x_sect_size_1:*/
/*! sector size 1 in x-direction */
#define MRV_LSC_X_SECT_SIZE_1
#define MRV_LSC_X_SECT_SIZE_1_MASK 0x03FF0000U
#define MRV_LSC_X_SECT_SIZE_1_SHIFT 16U
/*! Slice: x_sect_size_0:*/
/*! sector size 0 in x-direction */
#define MRV_LSC_X_SECT_SIZE_0
#define MRV_LSC_X_SECT_SIZE_0_MASK 0x000003FFU
#define MRV_LSC_X_SECT_SIZE_0_SHIFT 0U
/*! Register: isp_lsc_xsize_23: Size table (0x00000048)*/
/*! Slice: x_sect_size_3:*/
/*! sector size 3 in x-direction */
#define MRV_LSC_X_SECT_SIZE_3
#define MRV_LSC_X_SECT_SIZE_3_MASK 0x03FF0000U
#define MRV_LSC_X_SECT_SIZE_3_SHIFT 16U
/*! Slice: x_sect_size_2:*/
/*! sector size 2 in x-direction */
#define MRV_LSC_X_SECT_SIZE_2
#define MRV_LSC_X_SECT_SIZE_2_MASK 0x000003FFU
#define MRV_LSC_X_SECT_SIZE_2_SHIFT 0U
/*! Register: isp_lsc_xsize_45: Size table (0x0000004c)*/
/*! Slice: x_sect_size_5:*/
/*! sector size 5 in x-direction */
#define MRV_LSC_X_SECT_SIZE_5
#define MRV_LSC_X_SECT_SIZE_5_MASK 0x03FF0000U
#define MRV_LSC_X_SECT_SIZE_5_SHIFT 16U
/*! Slice: x_sect_size_4:*/
/*! sector size 4in x-direction */
#define MRV_LSC_X_SECT_SIZE_4
#define MRV_LSC_X_SECT_SIZE_4_MASK 0x000003FFU
#define MRV_LSC_X_SECT_SIZE_4_SHIFT 0U
/*! Register: isp_lsc_xsize_67: Size table (0x00000050)*/
/*! Slice: x_sect_size_7:*/
/*! sector size 7 in x-direction */
#define MRV_LSC_X_SECT_SIZE_7
#define MRV_LSC_X_SECT_SIZE_7_MASK 0x03FF0000U
#define MRV_LSC_X_SECT_SIZE_7_SHIFT 16U
/*! Slice: x_sect_size_6:*/
/*! sector size 6 in x-direction */
#define MRV_LSC_X_SECT_SIZE_6
#define MRV_LSC_X_SECT_SIZE_6_MASK 0x000003FFU
#define MRV_LSC_X_SECT_SIZE_6_SHIFT 0U
/*! Register: isp_lsc_ysize_01: Size table (0x00000054)*/
/*! Slice: y_sect_size_1:*/
/*! sector size 1 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_1
#define MRV_LSC_Y_SECT_SIZE_1_MASK 0x03FF0000U
#define MRV_LSC_Y_SECT_SIZE_1_SHIFT 16U
/*! Slice: y_sect_size_0:*/
/*! sector size 0 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_0
#define MRV_LSC_Y_SECT_SIZE_0_MASK 0x000003FFU
#define MRV_LSC_Y_SECT_SIZE_0_SHIFT 0U
/*! Register: isp_lsc_ysize_23: Size table (0x00000058)*/
/*! Slice: y_sect_size_3:*/
/*! sector size 3 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_3
#define MRV_LSC_Y_SECT_SIZE_3_MASK 0x03FF0000U
#define MRV_LSC_Y_SECT_SIZE_3_SHIFT 16U
/*! Slice: y_sect_size_2:*/
/*! sector size 2 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_2
#define MRV_LSC_Y_SECT_SIZE_2_MASK 0x000003FFU
#define MRV_LSC_Y_SECT_SIZE_2_SHIFT 0U
/*! Register: isp_lsc_ysize_45: Size table (0x0000005c)*/
/*! Slice: y_sect_size_5:*/
/*! sector size 5 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_5
#define MRV_LSC_Y_SECT_SIZE_5_MASK 0x03FF0000U
#define MRV_LSC_Y_SECT_SIZE_5_SHIFT 16U
/*! Slice: y_sect_size_4:*/
/*! sector size 4 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_4
#define MRV_LSC_Y_SECT_SIZE_4_MASK 0x000003FFU
#define MRV_LSC_Y_SECT_SIZE_4_SHIFT 0U
/*! Register: isp_lsc_ysize_67: Size table (0x00000060)*/
/*! Slice: y_sect_size_7:*/
/*! sector size 7 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_7
#define MRV_LSC_Y_SECT_SIZE_7_MASK 0x03FF0000U
#define MRV_LSC_Y_SECT_SIZE_7_SHIFT 16U
/*! Slice: y_sect_size_6:*/
/*! sector size 6 in y-direction */
#define MRV_LSC_Y_SECT_SIZE_6
#define MRV_LSC_Y_SECT_SIZE_6_MASK 0x000003FFU
#define MRV_LSC_Y_SECT_SIZE_6_SHIFT 0U
/*! Register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)*/
/*! Slice: table_sel:*/
/*! 0: next active tables set is table set 0.*/
/* 1: next active tables set is table set 1.*/
/* Table selection is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::active_table.*/
#define MRV_LSC_TABLE_SEL
#define MRV_LSC_TABLE_SEL_MASK 0x00000001U
#define MRV_LSC_TABLE_SEL_SHIFT 0U
/*! Register: isp_lsc_status: Lens shade status (0x00000068)*/
/*! Slice: active_table:*/
/*! 0: currently active tables set is table set 0 */
/* 1: currently active tables set is table set 1 */
#define MRV_LSC_ACTIVE_TABLE
#define MRV_LSC_ACTIVE_TABLE_MASK 0x00000002U
#define MRV_LSC_ACTIVE_TABLE_SHIFT 1U
/*! Slice: lsc_en_status:*/
/*! 0: lens shading correction is currently off */
/* 1: lens shading correction is currently on */
#define MRV_LSC_LSC_EN_STATUS
#define MRV_LSC_LSC_EN_STATUS_MASK 0x00000001U
#define MRV_LSC_LSC_EN_STATUS_SHIFT 0U
/*! Register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)*/
/*! Slice: is_en:*/
/*! 1: image stabilization switched on */
/* 0: image stabilization switched off */
#define MRV_IS_IS_EN
#define MRV_IS_IS_EN_MASK 0x00000001U
#define MRV_IS_IS_EN_SHIFT 0U
/*! Register: isp_is_recenter: Recenter register (0x00000004)*/
/*! Slice: is_recenter:*/
/*! 000: recenter feature switched off */
/* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
#define MRV_IS_IS_RECENTER
#define MRV_IS_IS_RECENTER_MASK 0x00000007U
#define MRV_IS_IS_RECENTER_SHIFT 0U
/*! Register: isp_is_h_offs: Horizontal offset of output window (0x00000008)*/
/*! Slice: is_h_offs:*/
/*! horizontal picture offset in pixel */
#define MRV_IS_IS_H_OFFS
#define MRV_IS_IS_H_OFFS_MASK 0x00003FFFU
#define MRV_IS_IS_H_OFFS_SHIFT 0U
/*! Register: isp_is_v_offs: Vertical offset of output window (0x0000000c)*/
/*! Slice: is_v_offs:*/
/*! vertical picture offset in lines */
#define MRV_IS_IS_V_OFFS
#define MRV_IS_IS_V_OFFS_MASK 0x00003FFFU
#define MRV_IS_IS_V_OFFS_SHIFT 0U
/*! Register: isp_is_h_size: Output horizontal picture size (0x00000010)*/
/*! Slice: is_h_size:*/
/*! horizontal picture size in pixel */
/* if ISP_MODE is set to */
/* 001-(ITU-R BT.656 YUV),*/
/* 010-( ITU-R BT.601 YUV),*/
/* 011-( ITU-R BT.601 Bayer RGB),*/
/* 101-( ITU-R BT.656 Bayer RGB)*/
/* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/
#define MRV_IS_IS_H_SIZE
#define MRV_IS_IS_H_SIZE_MASK 0x00003FFFU
#define MRV_IS_IS_H_SIZE_SHIFT 0U
/*! Register: isp_is_v_size: Output vertical picture size (0x00000014)*/
/*! Slice: is_v_size:*/
/*! vertical picture size in lines */
#define MRV_IS_IS_V_SIZE
#define MRV_IS_IS_V_SIZE_MASK 0x00003FFFU
#define MRV_IS_IS_V_SIZE_SHIFT 0U
/*! Register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/
/*! Slice: is_max_dx:*/
/*! maximum allowed accumulated horizontal displacement in pixels */
#define MRV_IS_IS_MAX_DX
#define MRV_IS_IS_MAX_DX_MASK 0x00001FFFU
#define MRV_IS_IS_MAX_DX_SHIFT 0U
/*! Register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/
/*! Slice: is_max_dy:*/
/*! maximum allowed accumulated vertical displacement in lines */
#define MRV_IS_IS_MAX_DY
#define MRV_IS_IS_MAX_DY_MASK 0x00001FFFU
#define MRV_IS_IS_MAX_DY_SHIFT 0U
/*! Register: isp_is_displace: Camera displacement (0x00000020)*/
/*! Slice: dy:*/
/*! ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */
#define MRV_IS_DY
#define MRV_IS_DY_MASK 0x1FFF0000U
#define MRV_IS_DY_SHIFT 16U
/*! Slice: dx:*/
/*! ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
#define MRV_IS_DX
#define MRV_IS_DX_MASK 0x00001FFFU
#define MRV_IS_DX_SHIFT 0U
/*! Register: isp_is_h_offs_shd: current horizontal offset of output window (shadow register) (0x00000024)*/
/*! Slice: is_h_offs_shd:*/
/*! current horizonatl picture offset in lines */
#define MRV_IS_IS_H_OFFS_SHD
#define MRV_IS_IS_H_OFFS_SHD_MASK 0x00003FFFU
#define MRV_IS_IS_H_OFFS_SHD_SHIFT 0U
/*! Register: isp_is_v_offs_shd: current vertical offset of output window (shadow register) (0x00000028)*/
/*! Slice: is_v_offs_shd:*/
/*! current vertical picture offset in lines */
#define MRV_IS_IS_V_OFFS_SHD
#define MRV_IS_IS_V_OFFS_SHD_MASK 0x00003FFFU
#define MRV_IS_IS_V_OFFS_SHD_SHIFT 0U
/*! Register: isp_is_h_size_shd: current output horizontal picture size (shadow register) (0x0000002c)*/
/*! Slice: isp_h_size_shd:*/
/*! current horizontal picture size in pixel */
#define MRV_IS_ISP_H_SIZE_SHD
#define MRV_IS_ISP_H_SIZE_SHD_MASK 0x00003FFFU
#define MRV_IS_ISP_H_SIZE_SHD_SHIFT 0U
/*! Register: isp_is_v_size_shd: current output vertical picture size (shadow register) (0x00000030)*/
/*! Slice: isp_v_size_shd:*/
/*! vertical picture size in lines */
#define MRV_IS_ISP_V_SIZE_SHD
#define MRV_IS_ISP_V_SIZE_SHD_MASK 0x00003FFFU
#define MRV_IS_ISP_V_SIZE_SHD_SHIFT 0U
/*! Register: isp_hist_prop: Histogram properties (0x00000000)*/
/*! Slice: stepsize:*/
/*! histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */
/* 0,1,2: not allowed */
/* 3: process every third input pixel */
/* 4: process every fourth input pixel */
/* ...*/
/* 7FH: process every 127th pixel */
#define MRV_HIST_STEPSIZE
#define MRV_HIST_STEPSIZE_MASK 0x000003F8U
#define MRV_HIST_STEPSIZE_SHIFT 3U
/*! Slice: hist_mode:*/
/*! histogram mode, luminance is taken at ISP output before output formatter, RGB is taken at xtalk output */
/* 7, 6: must not be used */
/* 5: Y (luminance) histogram */
/* 4: B histogram */
/* 3: G histogram */
/* 2: R histogram */
/* 1: RGB combined histogram */
/* 0: disable, no measurements */
#define MRV_HIST_MODE
#define MRV_HIST_MODE_MASK 0x00000007U
#define MRV_HIST_MODE_SHIFT 0U
/*! Register: isp_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000004)*/
/*! Slice: hist_h_offset:*/
/*! Horizontal offset of first window in pixels.*/
#define MRV_HIST_H_OFFSET
#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU
#define MRV_HIST_H_OFFSET_SHIFT 0U
/*! Register: isp_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x00000008)*/
/*! Slice: hist_v_offset:*/
/*! Vertical offset of first window in pixels.*/
#define MRV_HIST_V_OFFSET
#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU
#define MRV_HIST_V_OFFSET_SHIFT 0U
/*! Register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)*/
/*! Slice: hist_h_size:*/
/*! Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/
#define MRV_HIST_H_SIZE
#define MRV_HIST_H_SIZE_MASK 0x000007FFU
#define MRV_HIST_H_SIZE_SHIFT 0U
/*! Register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)*/
/*! Slice: hist_v_size:*/
/*! Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/
#define MRV_HIST_V_SIZE
#define MRV_HIST_V_SIZE_MASK 0x000007FFU
#define MRV_HIST_V_SIZE_SHIFT 0U
#ifndef ISP_HIST256
/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/
/*! Slice: hist_bin_n:*/
/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
#define MRV_HIST_BIN_N
#define MRV_HIST_BIN_N_MASK 0x000FFFFFU
#define MRV_HIST_BIN_N_SHIFT 0U
#else
/*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/
/*! Slice: hist_bin_n:*/
/* measured bin count as 26-bit unsigned integer value plus 4 bit fractional part */
#define MRV_HIST_BIN_N
#define MRV_HIST_BIN_N_MASK 0x3FFFFFFFU
#define MRV_HIST_BIN_N_SHIFT 0U
#endif
/*! Register: isp_hist_weight_00to30: Weighting factor for sub-windows (0x00000054)*/
/*! Slice: hist_weight_30:*/
/*! weighting factor for sub-window 30 */
#define MRV_HIST_WEIGHT_30
#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_30_SHIFT 24U
/*! Slice: hist_weight_20:*/
/*! weighting factor for sub-window 20 */
#define MRV_HIST_WEIGHT_20
#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_20_SHIFT 16U
/*! Slice: hist_weight_10:*/
/*! weighting factor for sub-window 10 */
#define MRV_HIST_WEIGHT_10
#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_10_SHIFT 8U
/*! Slice: hist_weight_00:*/
/*! weighting factor for sub-window 00 */
#define MRV_HIST_WEIGHT_00
#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_00_SHIFT 0U
/*! Register: isp_hist_weight_40to21: Weighting factor for sub-windows (0x00000058)*/
/*! Slice: hist_weight_21:*/
/*! weighting factor for sub-window 21 */
#define MRV_HIST_WEIGHT_21
#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_21_SHIFT 24U
/*! Slice: hist_weight_11:*/
/*! weighting factor for sub-window 11 */
#define MRV_HIST_WEIGHT_11
#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_11_SHIFT 16U
/*! Slice: hist_weight_01:*/
/*! weighting factor for sub-window 01 */
#define MRV_HIST_WEIGHT_01
#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_01_SHIFT 8U
/*! Slice: hist_weight_40:*/
/*! weighting factor for sub-window 40 */
#define MRV_HIST_WEIGHT_40
#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_40_SHIFT 0U
/*! Register: isp_hist_weight_31to12: Weighting factor for sub-windows (0x0000005c)*/
/*! Slice: hist_weight_12:*/
/*! weighting factor for sub-window 12 */
#define MRV_HIST_WEIGHT_12
#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_12_SHIFT 24U
/*! Slice: hist_weight_02:*/
/*! weighting factor for sub-window 02 */
#define MRV_HIST_WEIGHT_02
#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_02_SHIFT 16U
/*! Slice: hist_weight_41:*/
/*! weighting factor for sub-window 41 */
#define MRV_HIST_WEIGHT_41
#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_41_SHIFT 8U
/*! Slice: hist_weight_31:*/
/*! weighting factor for sub-window 31 */
#define MRV_HIST_WEIGHT_31
#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_31_SHIFT 0U
/*! Register: isp_hist_weight_22to03: Weighting factor for sub-windows (0x00000060)*/
/*! Slice: hist_weight_03:*/
/*! weighting factor for sub-window 03 */
#define MRV_HIST_WEIGHT_03
#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_03_SHIFT 24U
/*! Slice: hist_weight_42:*/
/*! weighting factor for sub-window 42 */
#define MRV_HIST_WEIGHT_42
#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_42_SHIFT 16U
/*! Slice: hist_weight_32:*/
/*! weighting factor for sub-window 32 */
#define MRV_HIST_WEIGHT_32
#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_32_SHIFT 8U
/*! Slice: hist_weight_22:*/
/*! weighting factor for sub-window 22 */
#define MRV_HIST_WEIGHT_22
#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_22_SHIFT 0U
/*! Register: isp_hist_weight_13to43: Weighting factor for sub-windows (0x00000064)*/
/*! Slice: hist_weight_43:*/
/*! weighting factor for sub-window 43 */
#define MRV_HIST_WEIGHT_43
#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_43_SHIFT 24U
/*! Slice: hist_weight_33:*/
/*! weighting factor for sub-window 33 */
#define MRV_HIST_WEIGHT_33
#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_33_SHIFT 16U
/*! Slice: hist_weight_23:*/
/*! weighting factor for sub-window 23 */
#define MRV_HIST_WEIGHT_23
#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_23_SHIFT 8U
/*! Slice: hist_weight_13:*/
/*! weighting factor for sub-window 13 */
#define MRV_HIST_WEIGHT_13
#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_13_SHIFT 0U
/*! Register: isp_hist_weight_04to34: Weighting factor for sub-windows (0x00000068)*/
/*! Slice: hist_weight_34:*/
/*! weighting factor for sub-window 34 */
#define MRV_HIST_WEIGHT_34
#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_34_SHIFT 24U
/*! Slice: hist_weight_24:*/
/*! weighting factor for sub-window 24 */
#define MRV_HIST_WEIGHT_24
#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_24_SHIFT 16U
/*! Slice: hist_weight_14:*/
/*! weighting factor for sub-window 14 */
#define MRV_HIST_WEIGHT_14
#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_14_SHIFT 8U
/*! Slice: hist_weight_04:*/
/*! weighting factor for sub-window 04 */
#define MRV_HIST_WEIGHT_04
#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_04_SHIFT 0U
/*! Register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)*/
/*! Slice: hist_weight_44:*/
/*! weighting factor for sub-window 44 */
#define MRV_HIST_WEIGHT_44
#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_44_SHIFT 0U
/*! Register: isp_filt_mode: mode control register for the filter block (0x00000000)*/
/*! Slice: stage1_select:*/
/*! Green filter stage 1 select (range 0x0...0x8)*/
/* 0x0 maximum blurring */
/* 0x4 Default */
/* 0x7 minimum blurring */
/* 0x8 filter stage1 bypass */
/* For a detailed description refer to chapter "ISP Filter Programming" of user manual */
#define MRV_FILT_STAGE1_SELECT
#define MRV_FILT_STAGE1_SELECT_MASK 0x00000F00U
#define MRV_FILT_STAGE1_SELECT_SHIFT 8U
/*! Slice: filt_chr_h_mode:*/
/*! Chroma filter horizontal mode */
/* 00 horizontal chroma filter bypass */
/* 01 horizontal chroma filter 1 static mask =[10 12 10]*/
/* 10 horizontal chroma filter 2 (dynamic blur1)*/
/* 11 horizontal chroma filter 3 (dynamic blur2) Default */
#define MRV_FILT_FILT_CHR_H_MODE
#define MRV_FILT_FILT_CHR_H_MODE_MASK 0x000000C0U
#define MRV_FILT_FILT_CHR_H_MODE_SHIFT 6U
/*! Slice: filt_chr_v_mode:*/
/*! Chroma filter vertical mode */
/* 00 vertical chroma filter bypass */
/* 01 vertical chroma filter 1 static[8 16 8]*/
/* 10 vertical chroma filter 2 static[10 12 10]*/
/* 11 vertical chroma filter 3 static[12 8 12] Default */
#define MRV_FILT_FILT_CHR_V_MODE
#define MRV_FILT_FILT_CHR_V_MODE_MASK 0x00000030U
#define MRV_FILT_FILT_CHR_V_MODE_SHIFT 4U
/*! Slice: filt_mode:*/
/*! 0 green filter static mode (active filter factor = FILT_FAC_MID)*/
/* 1 dynamic noise reduction/sharpen Default */
#define MRV_FILT_FILT_MODE
#define MRV_FILT_FILT_MODE_MASK 0x00000002U
#define MRV_FILT_FILT_MODE_SHIFT 1U
/*! Slice: filt_enable:*/
/*! 1 enable filter */
/* 0 bypass filter Default */
#define MRV_FILT_FILT_ENABLE
#define MRV_FILT_FILT_ENABLE_MASK 0x00000001U
#define MRV_FILT_FILT_ENABLE_SHIFT 0U
/*! Register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)*/
/*! Slice: filt_thresh_bl0:*/
/*! If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */
#define MRV_FILT_FILT_THRESH_BL0
#define MRV_FILT_FILT_THRESH_BL0_MASK 0x000003FFU
#define MRV_FILT_FILT_THRESH_BL0_SHIFT 0U
/*! Register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)*/
/*! Slice: filt_thresh_bl1:*/
/*! If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */
#define MRV_FILT_FILT_THRESH_BL1
#define MRV_FILT_FILT_THRESH_BL1_MASK 0x000003FFU
#define MRV_FILT_FILT_THRESH_BL1_SHIFT 0U
/*! Register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)*/
/*! Slice: filt_thresh_sh0:*/
/*! If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */
#define MRV_FILT_FILT_THRESH_SH0
#define MRV_FILT_FILT_THRESH_SH0_MASK 0x000003FFU
#define MRV_FILT_FILT_THRESH_SH0_SHIFT 0U
/*! Register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)*/
/*! Slice: filt_thresh_sh1:*/
/*! If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */
#define MRV_FILT_FILT_THRESH_SH1
#define MRV_FILT_FILT_THRESH_SH1_MASK 0x000003FFU
#define MRV_FILT_FILT_THRESH_SH1_SHIFT 0U
/*! Register: isp_filt_lum_weight: Parameters for luminance weight function (0x00000038)*/
/*! Slice: lum_weight_gain:*/
/*! Gain select of luminance weight function */
#define MRV_FILT_LUM_WEIGHT_GAIN
#define MRV_FILT_LUM_WEIGHT_GAIN_MASK 0x00070000U
#define MRV_FILT_LUM_WEIGHT_GAIN_SHIFT 16U
/*! Slice: lum_weight_kink:*/
/*! Kink position of luminance weight function */
#define MRV_FILT_LUM_WEIGHT_KINK
#define MRV_FILT_LUM_WEIGHT_KINK_MASK 0x0000FF00U
#define MRV_FILT_LUM_WEIGHT_KINK_SHIFT 8U
/*! Slice: lum_weight_min:*/
/*! Minimum value of luminance weight function */
#define MRV_FILT_LUM_WEIGHT_MIN
#define MRV_FILT_LUM_WEIGHT_MIN_MASK 0x000000FFU
#define MRV_FILT_LUM_WEIGHT_MIN_SHIFT 0U
/*! Register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)*/
/*! Slice: filt_fac_sh1:*/
/*! Filter factor for sharp1 level */
#define MRV_FILT_FILT_FAC_SH1
#define MRV_FILT_FILT_FAC_SH1_MASK 0x0000003FU
#define MRV_FILT_FILT_FAC_SH1_SHIFT 0U
/*! Register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)*/
/*! Slice: filt_fac_sh0:*/
/*! Filter factor for sharp0 level */
#define MRV_FILT_FILT_FAC_SH0
#define MRV_FILT_FILT_FAC_SH0_MASK 0x0000003FU
#define MRV_FILT_FILT_FAC_SH0_SHIFT 0U
/*! Register: isp_filt_fac_mid: filter factor middle (0x00000044)*/
/*! Slice: filt_fac_mid:*/
/*! Filter factor for mid level and for static filter mode */
#define MRV_FILT_FILT_FAC_MID
#define MRV_FILT_FILT_FAC_MID_MASK 0x0000003FU
#define MRV_FILT_FILT_FAC_MID_SHIFT 0U
/*! Register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)*/
/*! Slice: filt_fac_bl0:*/
/*! Filter factor for blur 0 level */
#define MRV_FILT_FILT_FAC_BL0
#define MRV_FILT_FILT_FAC_BL0_MASK 0x0000003FU
#define MRV_FILT_FILT_FAC_BL0_SHIFT 0U
/*! Register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)*/
/*! Slice: filt_fac_bl1:*/
/*! Filter factor for blur 1 level (max blur)*/
#define MRV_FILT_FILT_FAC_BL1
#define MRV_FILT_FILT_FAC_BL1_MASK 0x0000003FU
#define MRV_FILT_FILT_FAC_BL1_SHIFT 0U
/*! Register: isp_cac_ctrl: Control register for chromatic aberration correction (0x00000000)*/
/*! Slice: h_clip_mode:*/
/*! Defines the maximum red/blue pixel shift in horizontal direction At pixel positions, that require a larger displacement, the maximum shift value is used instead (vector clipping)*/
/* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/
/* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-4 and +/-5)*/
#define MRV_CAC_H_CLIP_MODE
#define MRV_CAC_H_CLIP_MODE_MASK 0x00000008U
#define MRV_CAC_H_CLIP_MODE_SHIFT 3U
/*! Slice: v_clip_mode:*/
/*! Defines the maximum red/blue pixel shift in vertical direction */
/* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/
/* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for chroma low pass filter */
/* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/
/* 11: reserved */
#define MRV_CAC_V_CLIP_MODE
#define MRV_CAC_V_CLIP_MODE_MASK 0x00000006U
#define MRV_CAC_V_CLIP_MODE_SHIFT 1U
/*! Slice: cac_en:*/
/*! 0: chromatic aberration correction off */
/* 1: chromatic aberration correction on */
#define MRV_CAC_CAC_EN
#define MRV_CAC_CAC_EN_MASK 0x00000001U
#define MRV_CAC_CAC_EN_SHIFT 0U
/*! Register: isp_cac_count_start: Preload values for CAC pixel and line counter (0x00000004)*/
/*! Slice: v_count_start:*/
/*! 13 bit v_count preload value (range 8191 ... 1) of the vertical CAC line counter. Before frame start v_count has to be preloaded with (v_size/2 + v_center_offset), with */
/* v_size the image height and */
/* v_center_offset the vertical distance between image center and optical center.*/
     /**/
/* After frame start the v_count decrements with every line until a value of zero is reached for the line in the optical center. Than the v_sign bit toggles and the v_counter decrements with every line until end of frame.*/
#define MRV_CAC_V_COUNT_START
#define MRV_CAC_V_COUNT_START_MASK 0x1FFF0000U
#define MRV_CAC_V_COUNT_START_SHIFT 16U
/*! Slice: h_count_start:*/
/*! 13 bit h_count preload value (range 8191 .. 1) of the horizontal CAC pixel counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset), with */
/* h_size the image width and */
/* h_center_offset the horizontal distance between image center and optical center.*/
     /**/
/* After line start the h_count decrements with every pixel until a value of zero is reached for the column in the optical center. Than the h_sign bit toggles and the h_counter increments with every pixel until end of line.*/
#define MRV_CAC_H_COUNT_START
#define MRV_CAC_H_COUNT_START_MASK 0x00001FFFU
#define MRV_CAC_H_COUNT_START_SHIFT 0U
/*! Register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)*/
/*! Slice: A_Blue:*/
/*! Parameter A_Blue for radial blue shift calculation, according to */
/*(A_Blue * r  + B_Blue * r^2 + C_Blue * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_A_BLUE
#define MRV_CAC_A_BLUE_MASK 0x01FF0000U
#define MRV_CAC_A_BLUE_SHIFT 16U
/*! Slice: A_Red:*/
/*! Parameter A_Red for radial red shift calculation, according to */
/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_A_RED
#define MRV_CAC_A_RED_MASK 0x000001FFU
#define MRV_CAC_A_RED_SHIFT 0U
/*! Register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)*/
/*! Slice: B_Blue:*/
/*! Parameter B_Blue for radial blue shift calculation, according to */
/*(A_Blue * r  + B_Blue * r^2 + C_Blue * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_B_BLUE
#define MRV_CAC_B_BLUE_MASK 0x01FF0000U
#define MRV_CAC_B_BLUE_SHIFT 16U
/*! Slice: B_Red:*/
/*! Parameter B_Red for radial red shift calculation, according to */
/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_B_RED
#define MRV_CAC_B_RED_MASK 0x000001FFU
#define MRV_CAC_B_RED_SHIFT 0U
/*! Register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)*/
/*! Slice: C_Blue:*/
/*! Parameter C_Blue for radial blue shift calculation, according to */
/*(A_Blue * r  + B_Blue * r^2 + C_Blue * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_C_BLUE
#define MRV_CAC_C_BLUE_MASK 0x01FF0000U
#define MRV_CAC_C_BLUE_SHIFT 16U
/*! Slice: C_Red:*/
/*! Parameter C_Red for radial red shift calculation, according to */
/*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
/* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
#define MRV_CAC_C_RED
#define MRV_CAC_C_RED_MASK 0x000001FFU
#define MRV_CAC_C_RED_SHIFT 0U
/*! Register: isp_cac_x_norm: Normalization parameters for calculation of image coordinate x_d relative to optical center (0x00000014)*/
/*! Slice: x_ns:*/
/*! Horizontal normalization shift parameter x_ns (4 bit unsigned integer) in equation */
/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
#define MRV_CAC_X_NS
#define MRV_CAC_X_NS_MASK 0x000F0000U
#define MRV_CAC_X_NS_SHIFT 16U
/*! Slice: x_nf:*/
/*! Horizontal scaling or normalization factor x_nf (5 bit unsigned integer) range 0 .. 31 in equation */
/* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
#define MRV_CAC_X_NF
#define MRV_CAC_X_NF_MASK 0x0000001FU
#define MRV_CAC_X_NF_SHIFT 0U
/*! Register: isp_cac_y_norm: Normalization parameters for calculation of image coordinate y_d relative to optical center (0x00000018)*/
/*! Slice: y_ns:*/
/*! Vertical normalization shift parameter y_ns (4 bit unsigned integer) in equation */
/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
#define MRV_CAC_Y_NS
#define MRV_CAC_Y_NS_MASK 0x000F0000U
#define MRV_CAC_Y_NS_SHIFT 16U
/*! Slice: y_nf:*/
/*! Vertical scaling or normalization factor y_nf (5 bit unsigned integer) range 0 .. 31 in equation */
/* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
#define MRV_CAC_Y_NF
#define MRV_CAC_Y_NF_MASK 0x0000001FU
#define MRV_CAC_Y_NF_SHIFT 0U
/*! Register: isp_exp_ctrl: Exposure control (0x00000000)*/
/*! Slice: exp_meas_mode:*/
/*! '1' luminance calculation according to */
/* Y=(R+G+B) x 0.332 (85/256)*/
/* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
#define MRV_AE_EXP_MEAS_MODE
#define MRV_AE_EXP_MEAS_MODE_MASK 0x80000000U
#define MRV_AE_EXP_MEAS_MODE_SHIFT 31U
/*! Slice: autostop:*/
/*! '1' stop measuring after a complete frame */
/* '0' continous measurement */
#define MRV_AE_AUTOSTOP
#define MRV_AE_AUTOSTOP_MASK 0x00000002U
#define MRV_AE_AUTOSTOP_SHIFT 1U
/*! Slice: exp_start:*/
/*! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.*/
#define MRV_AE_EXP_START
#define MRV_AE_EXP_START_MASK 0x00000001U
#define MRV_AE_EXP_START_SHIFT 0U
/*! Register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)*/
/*! Slice: isp_exp_h_offset:*/
/*! Horizontal offset of first block in pixels.*/
/* 0 <= value <= 2424 */
#define MRV_AE_ISP_EXP_H_OFFSET
#define MRV_AE_ISP_EXP_H_OFFSET_MASK 0x00001FFFU
#define MRV_AE_ISP_EXP_H_OFFSET_SHIFT 0U
/*! Register: isp_exp_v_offset: Vertical offset for first block (0x00000008)*/
/*! Slice: isp_exp_v_offset:*/
/*! Vertical offset of first block in pixels.*/
/* 0 <= value <= 1806 */
#define MRV_AE_ISP_EXP_V_OFFSET
#define MRV_AE_ISP_EXP_V_OFFSET_MASK 0x00001FFFU
#define MRV_AE_ISP_EXP_V_OFFSET_SHIFT 0U
/*! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)*/
/*! Slice: isp_exp_h_size:*/
/*! Horizontal size in pixels of one block.*/
/* 35 <= value <= 516 */
#define MRV_AE_ISP_EXP_H_SIZE
#define MRV_AE_ISP_EXP_H_SIZE_MASK 0x000007FFU
#define MRV_AE_ISP_EXP_H_SIZE_SHIFT 0U
/*! Register: isp_exp_v_size: Vertical size of one block (0x00000010)*/
/*! Slice: isp_exp_v_size:*/
/*! Vertical size in pixels of one block.*/
/* 28 <= value <= 390 */
#define MRV_AE_ISP_EXP_V_SIZE
#define MRV_AE_ISP_EXP_V_SIZE_MASK 0x000007FEU
#define MRV_AE_ISP_EXP_V_SIZE_SHIFT 0U
/*! Register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)*/
/*! Slice: isp_exp_mean_00:*/
/*! Mean luminance value of block 00 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_00
#define MRV_AE_ISP_EXP_MEAN_00_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_00_SHIFT 0U
/*! Register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)*/
/*! Slice: isp_exp_mean_10:*/
/*! Mean luminance value of block 10 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_10
#define MRV_AE_ISP_EXP_MEAN_10_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_10_SHIFT 0U
/*! Register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)*/
/*! Slice: isp_exp_mean_20:*/
/*! Mean luminance value of block 20 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_20
#define MRV_AE_ISP_EXP_MEAN_20_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_20_SHIFT 0U
/*! Register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)*/
/*! Slice: isp_exp_mean_30:*/
/*! Mean luminance value of block 30 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_30
#define MRV_AE_ISP_EXP_MEAN_30_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_30_SHIFT 0U
/*! Register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)*/
/*! Slice: isp_exp_mean_40:*/
/*! Mean luminance value of block 40 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_40
#define MRV_AE_ISP_EXP_MEAN_40_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_40_SHIFT 0U
/*! Register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)*/
/*! Slice: isp_exp_mean_01:*/
/*! Mean luminance value of block 01 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_01
#define MRV_AE_ISP_EXP_MEAN_01_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_01_SHIFT 0U
/*! Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/
/*! Slice: isp_exp_mean_11:*/
/*! Mean luminance value of block 11 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_11
#define MRV_AE_ISP_EXP_MEAN_11_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_11_SHIFT 0U
/*! Register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)*/
/*! Slice: isp_exp_mean_21:*/
/*! Mean luminance value of block 21 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_21
#define MRV_AE_ISP_EXP_MEAN_21_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_21_SHIFT 0U
/*! Register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)*/
/*! Slice: isp_exp_mean_31:*/
/*! Mean luminance value of block 31 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_31
#define MRV_AE_ISP_EXP_MEAN_31_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_31_SHIFT 0U
/*! Register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)*/
/*! Slice: isp_exp_mean_41:*/
/*! Mean luminance value of block 41 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_41
#define MRV_AE_ISP_EXP_MEAN_41_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_41_SHIFT 0U
/*! Register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)*/
/*! Slice: isp_exp_mean_02:*/
/*! Mean luminance value of block 02 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_02
#define MRV_AE_ISP_EXP_MEAN_02_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_02_SHIFT 0U
/*! Register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)*/
/*! Slice: isp_exp_mean_12:*/
/*! Mean luminance value of block 12 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_12
#define MRV_AE_ISP_EXP_MEAN_12_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_12_SHIFT 0U
/*! Register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)*/
/*! Slice: isp_exp_mean_22:*/
/*! Mean luminance value of block 22 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_22
#define MRV_AE_ISP_EXP_MEAN_22_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_22_SHIFT 0U
/*! Register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)*/
/*! Slice: isp_exp_mean_32:*/
/*! Mean luminance value of block 32 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_32
#define MRV_AE_ISP_EXP_MEAN_32_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_32_SHIFT 0U
/*! Register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)*/
/*! Slice: isp_exp_mean_42:*/
/*! Mean luminance value of block 42 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_42
#define MRV_AE_ISP_EXP_MEAN_42_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_42_SHIFT 0U
/*! Register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)*/
/*! Slice: isp_exp_mean_03:*/
/*! Mean luminance value of block 03 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_03
#define MRV_AE_ISP_EXP_MEAN_03_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_03_SHIFT 0U
/*! Register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)*/
/*! Slice: isp_exp_mean_13:*/
/*! Mean luminance value of block 13 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_13
#define MRV_AE_ISP_EXP_MEAN_13_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_13_SHIFT 0U
/*! Register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)*/
/*! Slice: isp_exp_mean_23:*/
/*! Mean luminance value of block 23 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_23
#define MRV_AE_ISP_EXP_MEAN_23_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_23_SHIFT 0U
/*! Register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)*/
/*! Slice: isp_exp_mean_33:*/
/*! Mean luminance value of block 33 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_33
#define MRV_AE_ISP_EXP_MEAN_33_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_33_SHIFT 0U
/*! Register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)*/
/*! Slice: isp_exp_mean_43:*/
/*! Mean luminance value of block 43 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_43
#define MRV_AE_ISP_EXP_MEAN_43_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_43_SHIFT 0U
/*! Register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)*/
/*! Slice: isp_exp_mean_04:*/
/*! Mean luminance value of block 04 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_04
#define MRV_AE_ISP_EXP_MEAN_04_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_04_SHIFT 0U
/*! Register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)*/
/*! Slice: isp_exp_mean_14:*/
/*! Mean luminance value of block 14 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_14
#define MRV_AE_ISP_EXP_MEAN_14_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_14_SHIFT 0U
/*! Register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)*/
/*! Slice: isp_exp_mean_24:*/
/*! Mean luminance value of block 24 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_24
#define MRV_AE_ISP_EXP_MEAN_24_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_24_SHIFT 0U
/*! Register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)*/
/*! Slice: isp_exp_mean_34:*/
/*! Mean luminance value of block 34 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_34
#define MRV_AE_ISP_EXP_MEAN_34_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_34_SHIFT 0U
/*! Register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)*/
/*! Slice: isp_exp_mean_44:*/
/*! Mean luminance value of block 44 (x,y)*/
#define MRV_AE_ISP_EXP_MEAN_44
#define MRV_AE_ISP_EXP_MEAN_44_MASK 0x000000FFU
#define MRV_AE_ISP_EXP_MEAN_44_SHIFT 0U
/*! Register: isp_expv2_ctrl: (0x00002680)*/
/*! Slice: isp_expv2_ctrl:*/
#define MRV_AE_ISP_EXPV2_INPUT_SELECT
#define MRV_AE_ISP_EXPV2_INPUT_SELECT_MASK 0x0000000CU
#define MRV_AE_ISP_EXPV2_INPUT_SELECT_SHIFT 2U
#define MRV_AE_ISP_EXPV2_AUTO_STOP
#define MRV_AE_ISP_EXPV2_AUTO_STOP_MASK 0x00000002U
#define MRV_AE_ISP_EXPV2_AUTO_STOP_SHIFT 1U
#define MRV_AE_ISP_EXPV2_ENABLE
#define MRV_AE_ISP_EXPV2_ENABLE_MASK 0x00000001U
#define MRV_AE_ISP_EXPV2_ENABLE_SHIFT 0U
/*! Register: isp_expv2_offset: (0x00002684)*/
/*! Slice: isp_expv2_offset:*/
#define MRV_AE_ISP_EXPV2_OFFSET_V
#define MRV_AE_ISP_EXPV2_OFFSET_V_MASK 0x1FFF0000U
#define MRV_AE_ISP_EXPV2_OFFSET_V_SHIFT 16U
#define MRV_AE_ISP_EXPV2_OFFSET_H
#define MRV_AE_ISP_EXPV2_OFFSET_H_MASK 0x00001FFFU
#define MRV_AE_ISP_EXPV2_OFFSET_H_SHIFT 0
/*! Register: isp_expv2_size: (0x00002688)*/
/*! Slice: isp_expv2_size:*/
#define MRV_AE_ISP_EXPV2_SIZE_V
#define MRV_AE_ISP_EXPV2_SIZE_V_MASK 0x01FF0000U
#define MRV_AE_ISP_EXPV2_SIZE_V_SHIFT 16U
#define MRV_AE_ISP_EXPV2_SIZE_H
#define MRV_AE_ISP_EXPV2_SIZE_H_MASK 0x000001FFU
#define MRV_AE_ISP_EXPV2_SIZE_H_SHIFT 0U
/*! Register: isp_expv2_size_invert: (0x0000268c)*/
/*! Slice: isp_expv2_size_invert:*/
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_MASK 0xFFFF0000U
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_SHIFT 16U
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_MASK 0x0000FFFFU
#define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_SHIFT 0U
/*! Register: isp_expv2_pixel_weight: (0x00002690)*/
/*! Slice: isp_expv2_pixel_weight:*/
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_MASK 0x3F000000U
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_SHIFT 24U
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_MASK 0x003F0000U
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_SHIFT 16
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_MASK 0x00003F00U
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_SHIFT 8U
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_MASK 0x0000003FU
#define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_SHIFT 0U
/*! Register: isp_bls_ctrl: global control register (0x00000000)*/
/*! Slice: WINDOW_ENABLE:*/
/*! 0: no measuring is performed */
/* 1: only window 1 is measured */
/* 2: only window 2 is measured */
/* 3: both windows are measured */
#define MRV_BLS_WINDOW_ENABLE
#define MRV_BLS_WINDOW_ENABLE_MASK 0x0000000CU
#define MRV_BLS_WINDOW_ENABLE_SHIFT 2U
/*! Slice: BLS_MODE:*/
/*! 1: subtract measured values */
/* 0: subtract fixed values */
#define MRV_BLS_BLS_MODE
#define MRV_BLS_BLS_MODE_MASK 0x00000002U
#define MRV_BLS_BLS_MODE_SHIFT 1U
/*! Slice: BLS_ENABLE:*/
/*! 1: black level subtraction is enabled */
/* 0: bypass the black level processing */
#define MRV_BLS_BLS_ENABLE
#define MRV_BLS_BLS_ENABLE_MASK 0x00000001U
#define MRV_BLS_BLS_ENABLE_SHIFT 0U
/*! Register: isp_bls_samples: samples register (0x00000004)*/
/*! Slice: BLS_SAMPLES:*/
/*! This number to the power of two gives the number of measure samples for each Bayer position. Range 0x00: 2^0=1  to  0x12: 2^18=262144. This number is also the divider for the accumulator for each Bayer position.*/
/* The accumulation will be stopped, if the number of measured pixels for the current Bayer position is equal to the number of samples.*/
/* The measure windows must be positioned that way that the number of included pixels of each Bayer position included by both windows is equal or greater than the number of measure samples calculated by 2^BLS_SAMPLES !*/
/* NOTE: The number of pixels of one Bayer position is 1/4 of the number of all Pixels included by the measure windows.*/
#define MRV_BLS_BLS_SAMPLES
#define MRV_BLS_BLS_SAMPLES_MASK 0x0000001FU
#define MRV_BLS_BLS_SAMPLES_SHIFT 0U
/*! Register: isp_bls_h1_start: window 1 horizontal start (0x00000008)*/
/*! Slice: BLS_H1_START:*/
/*! Black pixel window 1 horizontal start position */
#define MRV_BLS_BLS_H1_START
#define MRV_BLS_BLS_H1_START_MASK 0x00003FFFU
#define MRV_BLS_BLS_H1_START_SHIFT 0U
/*! Register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)*/
/*! Slice: BLS_H1_STOP:*/
/*! Black pixel window 1 horizontal stop position */
#define MRV_BLS_BLS_H1_STOP
#define MRV_BLS_BLS_H1_STOP_MASK 0x00003FFFU
#define MRV_BLS_BLS_H1_STOP_SHIFT 0U
/*! Register: isp_bls_v1_start: window 1 vertical start (0x00000010)*/
/*! Slice: BLS_V1_START:*/
/*! Black pixel window 1 vertical start position */
#define MRV_BLS_BLS_V1_START
#define MRV_BLS_BLS_V1_START_MASK 0x00003FFFU
#define MRV_BLS_BLS_V1_START_SHIFT 0U
/*! Register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)*/
/*! Slice: BLS_V1_STOP:*/
/*! Black pixel window 1 vertical stop position */
#define MRV_BLS_BLS_V1_STOP
#define MRV_BLS_BLS_V1_STOP_MASK 0x00003FFFU
#define MRV_BLS_BLS_V1_STOP_SHIFT 0U
/*! Register: isp_bls_h2_start: window 2 horizontal start (0x00000018)*/
/*! Slice: BLS_H2_START:*/
/*! Black pixel window 2 horizontal start position */
#define MRV_BLS_BLS_H2_START
#define MRV_BLS_BLS_H2_START_MASK 0x00003FFFU
#define MRV_BLS_BLS_H2_START_SHIFT 0U
/*! Register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)*/
/*! Slice: BLS_H2_STOP:*/
/*! Black pixel window 2 horizontal stop position */
#define MRV_BLS_BLS_H2_STOP
#define MRV_BLS_BLS_H2_STOP_MASK 0x00003FFFU
#define MRV_BLS_BLS_H2_STOP_SHIFT 0U
/*! Register: isp_bls_v2_start: window 2 vertical start (0x00000020)*/
/*! Slice: BLS_V2_START:*/
/*! Black pixel window 2 vertical start position */
#define MRV_BLS_BLS_V2_START
#define MRV_BLS_BLS_V2_START_MASK 0x00003FFFU
#define MRV_BLS_BLS_V2_START_SHIFT 0U
/*! Register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)*/
/*! Slice: BLS_V2_STOP:*/
/*! Black pixel window 2 vertical stop position */
#define MRV_BLS_BLS_V2_STOP
#define MRV_BLS_BLS_V2_STOP_MASK 0x00003FFFU
#define MRV_BLS_BLS_V2_STOP_SHIFT 0U
/*! Register: isp_bls_a_fixed: fixed black level A (0x00000028)*/
/*! Slice: BLS_A_FIXED:*/
/*! Fixed black level for A pixels  signed */
/* two's complement, value range from -4096 to +4095,*/
/* a positive value will be subtracted from the pixel values */
#define MRV_BLS_BLS_A_FIXED
#define MRV_BLS_BLS_A_FIXED_MASK 0x00001FFFU
#define MRV_BLS_BLS_A_FIXED_SHIFT 0U
/*! Register: isp_bls_b_fixed: fixed black level B (0x0000002c)*/
/*! Slice: BLS_B_FIXED:*/
/*! Fixed black level for B pixels  signed */
/* two's complement, value range from -4096 to +4095 */
#define MRV_BLS_BLS_B_FIXED
#define MRV_BLS_BLS_B_FIXED_MASK 0x00001FFFU
#define MRV_BLS_BLS_B_FIXED_SHIFT 0U
/*! Register: isp_bls_c_fixed: fixed black level C (0x00000030)*/
/*! Slice: BLS_C_FIXED:*/
/*! Fixed black level for C pixels  signed */
/* two's complement, value range from -4096 to +4095 */
#define MRV_BLS_BLS_C_FIXED
#define MRV_BLS_BLS_C_FIXED_MASK 0x00001FFFU
#define MRV_BLS_BLS_C_FIXED_SHIFT 0U
/*! Register: isp_bls_d_fixed: fixed black level D (0x00000034)*/
/*! Slice: BLS_D_FIXED:*/
/*! Fixed black level for D pixels  - signed */
/* two's complement, value range from -4096 to +4095 */
#define MRV_BLS_BLS_D_FIXED
#define MRV_BLS_BLS_D_FIXED_MASK 0x00001FFFU
#define MRV_BLS_BLS_D_FIXED_SHIFT 0U
/*! Register: isp_bls_a_measured: measured black level A (0x00000038)*/
/*! Slice: BLS_A_MEASURED:*/
/*! Measured black level for A pixels */
#define MRV_BLS_BLS_A_MEASURED
#define MRV_BLS_BLS_A_MEASURED_MASK 0x00000FFFU
#define MRV_BLS_BLS_A_MEASURED_SHIFT 0U
/*! Register: isp_bls_b_measured: measured black level B (0x0000003c)*/
/*! Slice: BLS_B_MEASURED:*/
/*! Measured black level for B pixels */
#define MRV_BLS_BLS_B_MEASURED
#define MRV_BLS_BLS_B_MEASURED_MASK 0x00000FFFU
#define MRV_BLS_BLS_B_MEASURED_SHIFT 0U
/*! Register: isp_bls_c_measured: measured black level C (0x00000040)*/
/*! Slice: BLS_C_MEASURED:*/
/*! Measured black level for C pixels */
#define MRV_BLS_BLS_C_MEASURED
#define MRV_BLS_BLS_C_MEASURED_MASK 0x00000FFFU
#define MRV_BLS_BLS_C_MEASURED_SHIFT 0U
/*! Register: isp_bls_d_measured: measured black level D (0x00000044)*/
/*! Slice: BLS_D_MEASURED:*/
/*! Measured black level for D pixels */
#define MRV_BLS_BLS_D_MEASURED
#define MRV_BLS_BLS_D_MEASURED_MASK 0x00000FFFU
#define MRV_BLS_BLS_D_MEASURED_SHIFT 0U
/*! Register: isp_dpf_mode: Mode control for Denoising Pre-Filter block (0x00000000)*/
/*! Slice: USE_NF_GAIN:*/
/*! 1: DPF_NF_GAINs will be used.*/
/* 0: DPF_NF_GAINs will not be used.  *Default**/
#define MRV_DPF_USE_NF_GAIN
#define MRV_DPF_USE_NF_GAIN_MASK 0x00000200U
#define MRV_DPF_USE_NF_GAIN_SHIFT 9U
/*! Slice: LSC_GAIN_COMP:*/
/*! 1: LSC gain will be processed */
/* 0: LSC gain will not be processed. Use LSC gain factor of 1.  *Default**/
#define MRV_DPF_LSC_GAIN_COMP
#define MRV_DPF_LSC_GAIN_COMP_MASK 0x00000100U
#define MRV_DPF_LSC_GAIN_COMP_SHIFT 8U
/*! Slice: AWB_GAIN_COMP:*/
/*! Only relevant when use_nf_gain == 0 && ISP_CTRL::ISP_AWB_ENABLE ==1 */
/* 1: ISP_AWB gains will be processed */
/* 0: ISP_AWB gains will not be processed. Use AWB gain factor of 1.  *Default**/
#define MRV_DPF_AWB_GAIN_COMP
#define MRV_DPF_AWB_GAIN_COMP_MASK 0x00000080U
#define MRV_DPF_AWB_GAIN_COMP_SHIFT 7U
/*! Slice: NLL_SEGMENTATION:*/
/*! 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/
/* 0: equidistant segmentation for NLL  *Default**/
#define MRV_DPF_NLL_SEGMENTATION
#define MRV_DPF_NLL_SEGMENTATION_MASK 0x00000040U
#define MRV_DPF_NLL_SEGMENTATION_SHIFT 6U
/*! Slice: RB_FILTER_SIZE:*/
/*! 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */
/* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels  *Default**/
#define MRV_DPF_RB_FILTER_SIZE
#define MRV_DPF_RB_FILTER_SIZE_MASK 0x00000020U
#define MRV_DPF_RB_FILTER_SIZE_SHIFT 5U
/*! Slice: R_FILTER_OFF:*/
/*! 1: disable filter processing for red pixels (R)*/
/* 0: filter R pixels  *Default**/
#define MRV_DPF_R_FILTER_OFF
#define MRV_DPF_R_FILTER_OFF_MASK 0x00000010U
#define MRV_DPF_R_FILTER_OFF_SHIFT 4U
/*! Slice: GR_FILTER_OFF:*/
/*! 1: disable filter processing for green pixels in green/red lines (GR)*/
/* 0: filter GR pixels  *Default**/
#define MRV_DPF_GR_FILTER_OFF
#define MRV_DPF_GR_FILTER_OFF_MASK 0x00000008U
#define MRV_DPF_GR_FILTER_OFF_SHIFT 3U
/*! Slice: GB_FILTER_OFF:*/
/*! 1: disable filter processing for green pixels in green/blue lines (GB)*/
/* 0: filter GB pixels  *Default**/
#define MRV_DPF_GB_FILTER_OFF
#define MRV_DPF_GB_FILTER_OFF_MASK 0x00000004U
#define MRV_DPF_GB_FILTER_OFF_SHIFT 2U
/*! Slice: B_FILTER_OFF:*/
/*! 1: disable filter processing for blue pixels (B)*/
/* 0: filter B pixels  *Default**/
#define MRV_DPF_B_FILTER_OFF
#define MRV_DPF_B_FILTER_OFF_MASK 0x00000002U
#define MRV_DPF_B_FILTER_OFF_SHIFT 1U
/*! Slice: DPF_ENABLE:*/
/*! 1: enable dpf */
/* 0: bypass dpf  *Default**/
#define MRV_DPF_DPF_ENABLE
#define MRV_DPF_DPF_ENABLE_MASK 0x00000001U
#define MRV_DPF_DPF_ENABLE_SHIFT 0U
/*! Register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)*/
/*! Slice: INV_WEIGHT_R:*/
/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
     /**/
/* The following values show examples:*/
/* weight=0.251 -> 255, weight=0.5 -> 128,*/
/* weight=1 -> 64 *default**/
/* weight=1.25  -> 51, weight=1.5 -> 42,*/
/* weight=1.75 -> 37, weight=2 -> 32 */
#define MRV_DPF_INV_WEIGHT_R
#define MRV_DPF_INV_WEIGHT_R_MASK 0x000000FFU
#define MRV_DPF_INV_WEIGHT_R_SHIFT 0U
/*! Register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)*/
/*! Slice: INV_WEIGHT_G:*/
/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
     /**/
/* The following values show examples:*/
/* weight=0.251 -> 255, weight=0.5 -> 128,*/
/* weight=1 -> 64 *default**/
/* weight=1.25  -> 51, weight=1.5 -> 42,*/
/* weight=1.75 -> 37, weight=2 -> 32 */
#define MRV_DPF_INV_WEIGHT_G
#define MRV_DPF_INV_WEIGHT_G_MASK 0x000000FFU
#define MRV_DPF_INV_WEIGHT_G_SHIFT 0U
/*! Register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)*/
/*! Slice: INV_WEIGHT_B:*/
/*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
     /**/
/* The following values show examples:*/
/* weight=0.251 -> 255, weight=0.5 -> 128,*/
/* weight=1 -> 64 *default**/
/* weight=1.25  -> 51, weight=1.5 -> 42,*/
/* weight=1.75 -> 37, weight=2 -> 32 */
#define MRV_DPF_INV_WEIGHT_B
#define MRV_DPF_INV_WEIGHT_B_MASK 0x000000FFU
#define MRV_DPF_INV_WEIGHT_B_SHIFT 0U
/*! Register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 (0x00000010)*/
/*! Slice: S_WEIGHT_G4:*/
/*! Filter Coefficient green channel S_WEIGHT_G4 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G4
#define MRV_DPF_S_WEIGHT_G4_MASK 0x1F000000U
#define MRV_DPF_S_WEIGHT_G4_SHIFT 24U
/*! Slice: S_WEIGHT_G3:*/
/*! Filter Coefficient green channel S_WEIGHT_G3 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G3
#define MRV_DPF_S_WEIGHT_G3_MASK 0x001F0000U
#define MRV_DPF_S_WEIGHT_G3_SHIFT 16U
/*! Slice: S_WEIGHT_G2:*/
/*! Filter Coefficient green channel S_WEIGHT_G2 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G2
#define MRV_DPF_S_WEIGHT_G2_MASK 0x00001F00U
#define MRV_DPF_S_WEIGHT_G2_SHIFT 8U
/*! Slice: S_WEIGHT_G1:*/
/*! Filter Coefficient green channel S_WEIGHT_G1 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G1
#define MRV_DPF_S_WEIGHT_G1_MASK 0x0000001FU
#define MRV_DPF_S_WEIGHT_G1_SHIFT 0U
/*! Register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 (0x00000014)*/
/*! Slice: S_WEIGHT_G6:*/
/*! Filter Coefficient green channel S_WEIGHT_G6 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G6
#define MRV_DPF_S_WEIGHT_G6_MASK 0x00001F00U
#define MRV_DPF_S_WEIGHT_G6_SHIFT 8U
/*! Slice: S_WEIGHT_G5:*/
/*! Filter Coefficient green channel S_WEIGHT_G5 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_G5
#define MRV_DPF_S_WEIGHT_G5_MASK 0x0000001FU
#define MRV_DPF_S_WEIGHT_G5_SHIFT 0U
/*! Register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 (0x00000018)*/
/*! Slice: S_WEIGHT_RB4:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB4 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB4
#define MRV_DPF_S_WEIGHT_RB4_MASK 0x1F000000U
#define MRV_DPF_S_WEIGHT_RB4_SHIFT 24U
/*! Slice: S_WEIGHT_RB3:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB3 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB3
#define MRV_DPF_S_WEIGHT_RB3_MASK 0x001F0000U
#define MRV_DPF_S_WEIGHT_RB3_SHIFT 16U
/*! Slice: S_WEIGHT_RB2:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB2 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB2
#define MRV_DPF_S_WEIGHT_RB2_MASK 0x00001F00U
#define MRV_DPF_S_WEIGHT_RB2_SHIFT 8U
/*! Slice: S_WEIGHT_RB1:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB1 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB1
#define MRV_DPF_S_WEIGHT_RB1_MASK 0x0000001FU
#define MRV_DPF_S_WEIGHT_RB1_SHIFT 0U
/*! Register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 (0x0000001c)*/
/*! Slice: S_WEIGHT_RB6:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB6 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB6
#define MRV_DPF_S_WEIGHT_RB6_MASK 0x00001F00U
#define MRV_DPF_S_WEIGHT_RB6_SHIFT 8U
/*! Slice: S_WEIGHT_RB5:*/
/*! Filter Coefficient red/blue channels S_WEIGHT_RB5 */
/* 5 bit unsigned, value range 1/16 to 16/16 */
/* Default value is 16/16 (*Default*)*/
#define MRV_DPF_S_WEIGHT_RB5
#define MRV_DPF_S_WEIGHT_RB5_MASK 0x0000001FU
#define MRV_DPF_S_WEIGHT_RB5_SHIFT 0U
/*! Register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient (0x0040 + n*0x4 (n=0..16))*/
/*! Slice: nll_coeff_n:*/
/* Noise Level Lookup Table Coefficient nll_coeff_n */
/* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/
#define MRV_DPF_NLL_COEFF_N
#define MRV_DPF_NLL_COEFF_N_MASK 0x000003FFU
#define MRV_DPF_NLL_COEFF_N_SHIFT 0U
/*! Register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)*/
/*! Slice: DPF_NF_GAIN_R:*/
/*! Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/
/* 12 bit unsigned integer format: gain=1 -> 0x100 */
#define MRV_DPF_DPF_NF_GAIN_R
#define MRV_DPF_DPF_NF_GAIN_R_MASK 0x00000FFFU
#define MRV_DPF_DPF_NF_GAIN_R_SHIFT 0U
/*! Register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels (0x00000068)*/
/*! Slice: DPF_NF_GAIN_GR:*/
/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a red line.*/
/* 12 bit unsigned integer format: gain=1 -> 0x100 */
#define MRV_DPF_DPF_NF_GAIN_GR
#define MRV_DPF_DPF_NF_GAIN_GR_MASK 0x00000FFFU
#define MRV_DPF_DPF_NF_GAIN_GR_SHIFT 0U
/*! Register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels (0x0000006c)*/
/*! Slice: DPF_NF_GAIN_GB:*/
/*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a blue line.*/
/* 12 bit unsigned integer format: gain=1 -> 0x100 */
#define MRV_DPF_DPF_NF_GAIN_GB
#define MRV_DPF_DPF_NF_GAIN_GB_MASK 0x00000FFFU
#define MRV_DPF_DPF_NF_GAIN_GB_SHIFT 0U
/*! Register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)*/
/*! Slice: DPF_NF_GAIN_B:*/
/*! Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/
/* 12 bit unsigned integer format: gain=1 -> 0x100 */
#define MRV_DPF_DPF_NF_GAIN_B
#define MRV_DPF_DPF_NF_GAIN_B_MASK 0x00000FFFU
#define MRV_DPF_DPF_NF_GAIN_B_SHIFT 0U
/*! Register: isp_dpcc_mode: Mode control for DPCC detection unit (0x00000000)*/
/*! Slice: STAGE1_ENABLE:*/
/*! 1: enable  stage1 *Default**/
/* 0: bypass  stage1 */
#define MRV_DPCC_STAGE1_ENABLE
#define MRV_DPCC_STAGE1_ENABLE_MASK 0x00000004U
#define MRV_DPCC_STAGE1_ENABLE_SHIFT 2U
/*! Slice: GRAYSCALE_MODE:*/
/*! 1: enable gray scale data input from black and white sensors (without color filter array)*/
/* 0: BAYER DATA INPUT  *Default**/
#define MRV_DPCC_GRAYSCALE_MODE
#define MRV_DPCC_GRAYSCALE_MODE_MASK 0x00000002U
#define MRV_DPCC_GRAYSCALE_MODE_SHIFT 1U
/*! Slice: ISP_DPCC_enable:*/
/*! 1: enable DPCC */
/* 0: bypass DPCC  *Default**/
#define MRV_DPCC_ISP_DPCC_ENABLE
#define MRV_DPCC_ISP_DPCC_ENABLE_MASK 0x00000001U
#define MRV_DPCC_ISP_DPCC_ENABLE_SHIFT 0U
/*! Register: isp_dpcc_output_mode: Interpolation mode for correction unit (0x00000004)*/
/*! Slice: STAGE1_RB_3x3:*/
/*! 1: stage1 red/blue 9 pixel (3x3) output median */
/* 0: stage1 red/blue 4 or 5 pixel output median  *Default**/
#define MRV_DPCC_STAGE1_RB_3X3
#define MRV_DPCC_STAGE1_RB_3X3_MASK 0x00000008U
#define MRV_DPCC_STAGE1_RB_3X3_SHIFT 3U
/*! Slice: STAGE1_G_3x3:*/
/*! 1: stage1 green 9 pixel (3x3) output median */
/* 0: stage1 green 4 or 5 pixel output median  *Default**/
#define MRV_DPCC_STAGE1_G_3X3
#define MRV_DPCC_STAGE1_G_3X3_MASK 0x00000004U
#define MRV_DPCC_STAGE1_G_3X3_SHIFT 2U
/*! Slice: STAGE1_INCL_RB_CENTER:*/
/*! 1: stage1 include center pixel for red/blue output median 2x2+1 */
/* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */
#define MRV_DPCC_STAGE1_INCL_RB_CENTER
#define MRV_DPCC_STAGE1_INCL_RB_CENTER_MASK 0x00000002U
#define MRV_DPCC_STAGE1_INCL_RB_CENTER_SHIFT 1U
/*! Slice: STAGE1_INCL_GREEN_CENTER:*/
/*! 1: stage1 include center pixel for green output median 2x2+1 *Default**/
/* 0: stage1 do not include center pixel for green output median 2x2 */
#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER
#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_MASK 0x00000001U
#define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_SHIFT 0U
/*! Register: isp_dpcc_set_use: DPCC methods set usage for detection (0x00000008)*/
/*! Slice: STAGE1_USE_FIX_SET:*/
/*! 1: stage1 use hard coded methods set *Default**/
/* 0: stage1 do not use hard coded methods set */
#define MRV_DPCC_STAGE1_USE_FIX_SET
#define MRV_DPCC_STAGE1_USE_FIX_SET_MASK 0x00000008U
#define MRV_DPCC_STAGE1_USE_FIX_SET_SHIFT 3U
/*! Slice: STAGE1_USE_SET_3:*/
/*! 1: stage1 use methods set 3 */
/* 0: stage1 do not use methods set 3 *Default**/
#define MRV_DPCC_STAGE1_USE_SET_3
#define MRV_DPCC_STAGE1_USE_SET_3_MASK 0x00000004U
#define MRV_DPCC_STAGE1_USE_SET_3_SHIFT 2U
/*! Slice: STAGE1_USE_SET_2:*/
/*! 1: stage1 use methods set 2 */
/* 0: stage1 do not use methods set 2 *Default**/
#define MRV_DPCC_STAGE1_USE_SET_2
#define MRV_DPCC_STAGE1_USE_SET_2_MASK 0x00000002U
#define MRV_DPCC_STAGE1_USE_SET_2_SHIFT 1U
/*! Slice: STAGE1_USE_SET_1:*/
/*! 1: stage1 use methods set 1  *Default**/
/* 0: stage1 do not use methods set 1 */
#define MRV_DPCC_STAGE1_USE_SET_1
#define MRV_DPCC_STAGE1_USE_SET_1_MASK 0x00000001U
#define MRV_DPCC_STAGE1_USE_SET_1_SHIFT 0U
/*! Register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 (0x0000000c)*/
/*! Slice: RG_RED_BLUE1_ENABLE:*/
/*! 1: enable Rank Gradient check for red_blue  *Default**/
/* 0: bypass Rank Gradient check for red_blue */
#define MRV_DPCC_RG_RED_BLUE1_ENABLE
#define MRV_DPCC_RG_RED_BLUE1_ENABLE_MASK 0x00001000U
#define MRV_DPCC_RG_RED_BLUE1_ENABLE_SHIFT 12U
/*! Slice: RND_RED_BLUE1_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for red_blue  *Default**/
/* 0: bypass Rank Neighbor Difference check for red_blue */
#define MRV_DPCC_RND_RED_BLUE1_ENABLE
#define MRV_DPCC_RND_RED_BLUE1_ENABLE_MASK 0x00000800U
#define MRV_DPCC_RND_RED_BLUE1_ENABLE_SHIFT 11U
/*! Slice: RO_RED_BLUE1_ENABLE:*/
/*! 1: enable Rank Order check for red_blue  *Default**/
/* 0: bypass Rank Order check for red_blue */
#define MRV_DPCC_RO_RED_BLUE1_ENABLE
#define MRV_DPCC_RO_RED_BLUE1_ENABLE_MASK 0x00000400U
#define MRV_DPCC_RO_RED_BLUE1_ENABLE_SHIFT 10U
/*! Slice: LC_RED_BLUE1_ENABLE:*/
/*! 1: enable Line check for red_blue *Default**/
/* 0: bypass Line check for red_blue */
#define MRV_DPCC_LC_RED_BLUE1_ENABLE
#define MRV_DPCC_LC_RED_BLUE1_ENABLE_MASK 0x00000200U
#define MRV_DPCC_LC_RED_BLUE1_ENABLE_SHIFT 9U
/*! Slice: PG_RED_BLUE1_ENABLE:*/
/*! 1: enable Peak Gradient check for red_blue  *Default**/
/* 0: bypass Peak Gradient check for red_blue */
#define MRV_DPCC_PG_RED_BLUE1_ENABLE
#define MRV_DPCC_PG_RED_BLUE1_ENABLE_MASK 0x00000100U
#define MRV_DPCC_PG_RED_BLUE1_ENABLE_SHIFT 8U
/*! Slice: RG_GREEN1_ENABLE:*/
/*! 1: enable Rank Gradient check for green  *Default**/
/* 0: bypass Rank Gradient check for green */
#define MRV_DPCC_RG_GREEN1_ENABLE
#define MRV_DPCC_RG_GREEN1_ENABLE_MASK 0x00000010U
#define MRV_DPCC_RG_GREEN1_ENABLE_SHIFT 4U
/*! Slice: RND_GREEN1_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for green  *Default**/
/* 0: bypass Rank Neighbor Difference check for green */
#define MRV_DPCC_RND_GREEN1_ENABLE
#define MRV_DPCC_RND_GREEN1_ENABLE_MASK 0x00000008U
#define MRV_DPCC_RND_GREEN1_ENABLE_SHIFT 3U
/*! Slice: RO_GREEN1_ENABLE:*/
/*! 1: enable Rank Order check for green  *Default**/
/* 0: bypass Rank Order check for green */
#define MRV_DPCC_RO_GREEN1_ENABLE
#define MRV_DPCC_RO_GREEN1_ENABLE_MASK 0x00000004U
#define MRV_DPCC_RO_GREEN1_ENABLE_SHIFT 2U
/*! Slice: LC_GREEN1_ENABLE:*/
/*! 1: enable Line check for green *Default**/
/* 0: bypass Line check for green */
#define MRV_DPCC_LC_GREEN1_ENABLE
#define MRV_DPCC_LC_GREEN1_ENABLE_MASK 0x00000002U
#define MRV_DPCC_LC_GREEN1_ENABLE_SHIFT 1U
/*! Slice: PG_GREEN1_ENABLE:*/
/*! 1: enable Peak Gradient check for green  *Default**/
/* 0: bypass Peak Gradient check for green */
#define MRV_DPCC_PG_GREEN1_ENABLE
#define MRV_DPCC_PG_GREEN1_ENABLE_MASK 0x00000001U
#define MRV_DPCC_PG_GREEN1_ENABLE_SHIFT 0U
/*! Register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 (0x00000010)*/
/*! Slice: RG_RED_BLUE2_ENABLE:*/
/*! 1: enable Rank Gradient check for red_blue  *Default**/
/* 0: bypass Rank Gradient check for red_blue */
#define MRV_DPCC_RG_RED_BLUE2_ENABLE
#define MRV_DPCC_RG_RED_BLUE2_ENABLE_MASK 0x00001000U
#define MRV_DPCC_RG_RED_BLUE2_ENABLE_SHIFT 12U
/*! Slice: RND_RED_BLUE2_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for red_blue  *Default**/
/* 0: bypass Rank Neighbor Difference check for red_blue */
#define MRV_DPCC_RND_RED_BLUE2_ENABLE
#define MRV_DPCC_RND_RED_BLUE2_ENABLE_MASK 0x00000800U
#define MRV_DPCC_RND_RED_BLUE2_ENABLE_SHIFT 11U
/*! Slice: RO_RED_BLUE2_ENABLE:*/
/*! 1: enable Rank Order check for red_blue  *Default**/
/* 0: bypass Rank Order check for red_blue */
#define MRV_DPCC_RO_RED_BLUE2_ENABLE
#define MRV_DPCC_RO_RED_BLUE2_ENABLE_MASK 0x00000400U
#define MRV_DPCC_RO_RED_BLUE2_ENABLE_SHIFT 10U
/*! Slice: LC_RED_BLUE2_ENABLE:*/
/*! 1: enable Line check for red_blue */
/* 0: bypass Line check for red_blue  *Default**/
#define MRV_DPCC_LC_RED_BLUE2_ENABLE
#define MRV_DPCC_LC_RED_BLUE2_ENABLE_MASK 0x00000200U
#define MRV_DPCC_LC_RED_BLUE2_ENABLE_SHIFT 9U
/*! Slice: PG_RED_BLUE2_ENABLE:*/
/*! 1: enable Peak Gradient check for red_blue  *Default**/
/* 0: bypass Peak Gradient check for red_blue */
#define MRV_DPCC_PG_RED_BLUE2_ENABLE
#define MRV_DPCC_PG_RED_BLUE2_ENABLE_MASK 0x00000100U
#define MRV_DPCC_PG_RED_BLUE2_ENABLE_SHIFT 8U
/*! Slice: RG_GREEN2_ENABLE:*/
/*! 1: enable Rank Gradient check for green  *Default**/
/* 0: bypass Rank Gradient check for green */
#define MRV_DPCC_RG_GREEN2_ENABLE
#define MRV_DPCC_RG_GREEN2_ENABLE_MASK 0x00000010U
#define MRV_DPCC_RG_GREEN2_ENABLE_SHIFT 4U
/*! Slice: RND_GREEN2_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for green  *Default**/
/* 0: bypass Rank Neighbor Difference check for green */
#define MRV_DPCC_RND_GREEN2_ENABLE
#define MRV_DPCC_RND_GREEN2_ENABLE_MASK 0x00000008U
#define MRV_DPCC_RND_GREEN2_ENABLE_SHIFT 3U
/*! Slice: RO_GREEN2_ENABLE:*/
/*! 1: enable Rank Order check for green  *Default**/
/* 0: bypass Rank Order check for green */
#define MRV_DPCC_RO_GREEN2_ENABLE
#define MRV_DPCC_RO_GREEN2_ENABLE_MASK 0x00000004U
#define MRV_DPCC_RO_GREEN2_ENABLE_SHIFT 2U
/*! Slice: LC_GREEN2_ENABLE:*/
/*! 1: enable Line check for green */
/* 0: bypass Line check for green  *Default**/
#define MRV_DPCC_LC_GREEN2_ENABLE
#define MRV_DPCC_LC_GREEN2_ENABLE_MASK 0x00000002U
#define MRV_DPCC_LC_GREEN2_ENABLE_SHIFT 1U
/*! Slice: PG_GREEN2_ENABLE:*/
/*! 1: enable Peak Gradient check for green  *Default**/
/* 0: bypass Peak Gradient check for green */
#define MRV_DPCC_PG_GREEN2_ENABLE
#define MRV_DPCC_PG_GREEN2_ENABLE_MASK 0x00000001U
#define MRV_DPCC_PG_GREEN2_ENABLE_SHIFT 0U
/*! Register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 (0x00000014)*/
/*! Slice: RG_RED_BLUE3_ENABLE:*/
/*! 1: enable Rank Gradient check for red_blue */
/* 0: bypass Rank Gradient check for red_blue  *Default**/
#define MRV_DPCC_RG_RED_BLUE3_ENABLE
#define MRV_DPCC_RG_RED_BLUE3_ENABLE_MASK 0x00001000U
#define MRV_DPCC_RG_RED_BLUE3_ENABLE_SHIFT 12U
/*! Slice: RND_RED_BLUE3_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for red_blue */
/* 0: bypass Rank Neighbor Difference check for red_blue  *Default**/
#define MRV_DPCC_RND_RED_BLUE3_ENABLE
#define MRV_DPCC_RND_RED_BLUE3_ENABLE_MASK 0x00000800U
#define MRV_DPCC_RND_RED_BLUE3_ENABLE_SHIFT 11U
/*! Slice: RO_RED_BLUE3_ENABLE:*/
/*! 1: enable Rank Order check for red_blue  *Default**/
/* 0: bypass Rank Order check for red_blue */
#define MRV_DPCC_RO_RED_BLUE3_ENABLE
#define MRV_DPCC_RO_RED_BLUE3_ENABLE_MASK 0x00000400U
#define MRV_DPCC_RO_RED_BLUE3_ENABLE_SHIFT 10U
/*! Slice: LC_RED_BLUE3_ENABLE:*/
/*! 1: enable Line check for red_blue  *Default**/
/* 0: bypass Line check for red_blue */
#define MRV_DPCC_LC_RED_BLUE3_ENABLE
#define MRV_DPCC_LC_RED_BLUE3_ENABLE_MASK 0x00000200U
#define MRV_DPCC_LC_RED_BLUE3_ENABLE_SHIFT 9U
/*! Slice: PG_RED_BLUE3_ENABLE:*/
/*! 1: enable Peak Gradient check for red_blue  *Default**/
/* 0: bypass Peak Gradient check for red_blue */
#define MRV_DPCC_PG_RED_BLUE3_ENABLE
#define MRV_DPCC_PG_RED_BLUE3_ENABLE_MASK 0x00000100U
#define MRV_DPCC_PG_RED_BLUE3_ENABLE_SHIFT 8U
/*! Slice: RG_GREEN3_ENABLE:*/
/*! 1: enable Rank Gradient check for green */
/* 0: bypass Rank Gradient check for green  *Default**/
#define MRV_DPCC_RG_GREEN3_ENABLE
#define MRV_DPCC_RG_GREEN3_ENABLE_MASK 0x00000010U
#define MRV_DPCC_RG_GREEN3_ENABLE_SHIFT 4U
/*! Slice: RND_GREEN3_ENABLE:*/
/*! 1: enable Rank Neighbor Difference check for green */
/* 0: bypass Rank Neighbor Difference check for green  *Default**/
#define MRV_DPCC_RND_GREEN3_ENABLE
#define MRV_DPCC_RND_GREEN3_ENABLE_MASK 0x00000008U
#define MRV_DPCC_RND_GREEN3_ENABLE_SHIFT 3U
/*! Slice: RO_GREEN3_ENABLE:*/
/*! 1: enable Rank Order check for green  *Default**/
/* 0: bypass Rank Order check for green */
#define MRV_DPCC_RO_GREEN3_ENABLE
#define MRV_DPCC_RO_GREEN3_ENABLE_MASK 0x00000004U
#define MRV_DPCC_RO_GREEN3_ENABLE_SHIFT 2U
/*! Slice: LC_GREEN3_ENABLE:*/
/*! 1: enable Line check for green  *Default**/
/* 0: bypass Line check for green */
#define MRV_DPCC_LC_GREEN3_ENABLE
#define MRV_DPCC_LC_GREEN3_ENABLE_MASK 0x00000002U
#define MRV_DPCC_LC_GREEN3_ENABLE_SHIFT 1U
/*! Slice: PG_GREEN3_ENABLE:*/
/*! 1: enable Peak Gradient check for green  *Default**/
/* 0: bypass Peak Gradient check for green */
#define MRV_DPCC_PG_GREEN3_ENABLE
#define MRV_DPCC_PG_GREEN3_ENABLE_MASK 0x00000001U
#define MRV_DPCC_PG_GREEN3_ENABLE_SHIFT 0U
/*! Register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)*/
/*! Slice: LINE_THR_1_RB:*/
/*! line threshold for set 1 red/blue */
#define MRV_DPCC_LINE_THR_1_RB
#define MRV_DPCC_LINE_THR_1_RB_MASK 0x0000FF00U
#define MRV_DPCC_LINE_THR_1_RB_SHIFT 8U
/*! Slice: LINE_THR_1_G:*/
/*! line threshold for set 1 green */
#define MRV_DPCC_LINE_THR_1_G
#define MRV_DPCC_LINE_THR_1_G_MASK 0x000000FFU
#define MRV_DPCC_LINE_THR_1_G_SHIFT 0U
/*! Register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor for Line check set 1 (0x0000001c)*/
/*! Slice: LINE_MAD_FAC_1_RB:*/
/*! line MAD factor for set 1 red/blue */
#define MRV_DPCC_LINE_MAD_FAC_1_RB
#define MRV_DPCC_LINE_MAD_FAC_1_RB_MASK 0x00003F00U
#define MRV_DPCC_LINE_MAD_FAC_1_RB_SHIFT 8U
/*! Slice: LINE_MAD_FAC_1_G:*/
/*! line MAD factor for set 1 green */
#define MRV_DPCC_LINE_MAD_FAC_1_G
#define MRV_DPCC_LINE_MAD_FAC_1_G_MASK 0x0000003FU
#define MRV_DPCC_LINE_MAD_FAC_1_G_SHIFT 0U
/*! Register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)*/
/*! Slice: PG_FAC_1_RB:*/
/*! Peak gradient factor for set 1 red/blue */
#define MRV_DPCC_PG_FAC_1_RB
#define MRV_DPCC_PG_FAC_1_RB_MASK 0x00003F00U
#define MRV_DPCC_PG_FAC_1_RB_SHIFT 8U
/*! Slice: PG_FAC_1_G:*/
/*! Peak gradient factor for set 1 green */
#define MRV_DPCC_PG_FAC_1_G
#define MRV_DPCC_PG_FAC_1_G_MASK 0x0000003FU
#define MRV_DPCC_PG_FAC_1_G_SHIFT 0U
/*! Register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for set 1 (0x00000024)*/
/*! Slice: RND_THR_1_RB:*/
/*! Rank Neighbor Difference threshold for set 1 red/blue */
#define MRV_DPCC_RND_THR_1_RB
#define MRV_DPCC_RND_THR_1_RB_MASK 0x0000FF00U
#define MRV_DPCC_RND_THR_1_RB_SHIFT 8U
/*! Slice: RND_THR_1_G:*/
/*! Rank Neighbor Difference threshold for set 1 green */
#define MRV_DPCC_RND_THR_1_G
#define MRV_DPCC_RND_THR_1_G_MASK 0x000000FFU
#define MRV_DPCC_RND_THR_1_G_SHIFT 0U
/*! Register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)*/
/*! Slice: RG_FAC_1_RB:*/
/*! Rank gradient factor for set 1 red/blue */
#define MRV_DPCC_RG_FAC_1_RB
#define MRV_DPCC_RG_FAC_1_RB_MASK 0x00003F00U
#define MRV_DPCC_RG_FAC_1_RB_SHIFT 8U
/*! Slice: RG_FAC_1_G:*/
/*! Rank gradient factor for set 1 green */
#define MRV_DPCC_RG_FAC_1_G
#define MRV_DPCC_RG_FAC_1_G_MASK 0x0000003FU
#define MRV_DPCC_RG_FAC_1_G_SHIFT 0U
/*! Register: isp_dpcc_line_thresh_2: Line threshold set 2 (0x0000002c)*/
/*! Slice: LINE_THR_2_RB:*/
/*! line threshold for set 2 red/blue */
#define MRV_DPCC_LINE_THR_2_RB
#define MRV_DPCC_LINE_THR_2_RB_MASK 0x0000FF00U
#define MRV_DPCC_LINE_THR_2_RB_SHIFT 8U
/*! Slice: LINE_THR_2_G:*/
/*! line threshold for set 2 green */
#define MRV_DPCC_LINE_THR_2_G
#define MRV_DPCC_LINE_THR_2_G_MASK 0x000000FFU
#define MRV_DPCC_LINE_THR_2_G_SHIFT 0U
/*! Register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor for Line check set 2 (0x00000030)*/
/*! Slice: LINE_MAD_FAC_2_RB:*/
/*! line MAD factor for set 2 red/blue */
#define MRV_DPCC_LINE_MAD_FAC_2_RB
#define MRV_DPCC_LINE_MAD_FAC_2_RB_MASK 0x00003F00U
#define MRV_DPCC_LINE_MAD_FAC_2_RB_SHIFT 8U
/*! Slice: LINE_MAD_FAC_2_G:*/
/*! line MAD factor for set 2 green */
#define MRV_DPCC_LINE_MAD_FAC_2_G
#define MRV_DPCC_LINE_MAD_FAC_2_G_MASK 0x0000003FU
#define MRV_DPCC_LINE_MAD_FAC_2_G_SHIFT 0U
/*! Register: isp_dpcc_pg_fac_2: Peak gradient factor for set 2 (0x00000034)*/
/*! Slice: PG_FAC_2_RB:*/
/*! Peak gradient factor for set 2 red/blue */
#define MRV_DPCC_PG_FAC_2_RB
#define MRV_DPCC_PG_FAC_2_RB_MASK 0x00003F00U
#define MRV_DPCC_PG_FAC_2_RB_SHIFT 8U
/*! Slice: PG_FAC_2_G:*/
/*! Peak gradient factor for set 2 green */
#define MRV_DPCC_PG_FAC_2_G
#define MRV_DPCC_PG_FAC_2_G_MASK 0x0000003FU
#define MRV_DPCC_PG_FAC_2_G_SHIFT 0U
/*! Register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for set 2 (0x00000038)*/
/*! Slice: RND_THR_2_RB:*/
/*! Rank Neighbor Difference threshold for set 2 red/blue */
#define MRV_DPCC_RND_THR_2_RB
#define MRV_DPCC_RND_THR_2_RB_MASK 0x0000FF00U
#define MRV_DPCC_RND_THR_2_RB_SHIFT 8U
/*! Slice: RND_THR_2_G:*/
/*! Rank Neighbor Difference threshold for set 2 green */
#define MRV_DPCC_RND_THR_2_G
#define MRV_DPCC_RND_THR_2_G_MASK 0x000000FFU
#define MRV_DPCC_RND_THR_2_G_SHIFT 0U
/*! Register: isp_dpcc_rg_fac_2: Rank gradient factor for set 2 (0x0000003c)*/
/*! Slice: RG_FAC_2_RB:*/
/*! Rank gradient factor for set 2 red/blue */
#define MRV_DPCC_RG_FAC_2_RB
#define MRV_DPCC_RG_FAC_2_RB_MASK 0x00003F00U
#define MRV_DPCC_RG_FAC_2_RB_SHIFT 8U
/*! Slice: RG_FAC_2_G:*/
/*! Rank gradient factor for set 2 green */
#define MRV_DPCC_RG_FAC_2_G
#define MRV_DPCC_RG_FAC_2_G_MASK 0x0000003FU
#define MRV_DPCC_RG_FAC_2_G_SHIFT 0U
/*! Register: isp_dpcc_line_thresh_3: Line threshold set 3 (0x00000040)*/
/*! Slice: LINE_THR_3_RB:*/
/*! line threshold for set 3 red/blue */
#define MRV_DPCC_LINE_THR_3_RB
#define MRV_DPCC_LINE_THR_3_RB_MASK 0x0000FF00U
#define MRV_DPCC_LINE_THR_3_RB_SHIFT 8U
/*! Slice: LINE_THR_3_G:*/
/*! line threshold for set 3 green */
#define MRV_DPCC_LINE_THR_3_G
#define MRV_DPCC_LINE_THR_3_G_MASK 0x000000FFU
#define MRV_DPCC_LINE_THR_3_G_SHIFT 0U
/*! Register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor for Line check set 3 (0x00000044)*/
/*! Slice: LINE_MAD_FAC_3_RB:*/
/*! line MAD factor for set 3 red/blue */
#define MRV_DPCC_LINE_MAD_FAC_3_RB
#define MRV_DPCC_LINE_MAD_FAC_3_RB_MASK 0x00003F00U
#define MRV_DPCC_LINE_MAD_FAC_3_RB_SHIFT 8U
/*! Slice: LINE_MAD_FAC_3_G:*/
/*! line MAD factor for set 3 green */
#define MRV_DPCC_LINE_MAD_FAC_3_G
#define MRV_DPCC_LINE_MAD_FAC_3_G_MASK 0x0000003FU
#define MRV_DPCC_LINE_MAD_FAC_3_G_SHIFT 0U
/*! Register: isp_dpcc_pg_fac_3: Peak gradient factor for set 3 (0x00000048)*/
/*! Slice: PG_FAC_3_RB:*/
/*! Peak gradient factor for set 3 red/blue */
#define MRV_DPCC_PG_FAC_3_RB
#define MRV_DPCC_PG_FAC_3_RB_MASK 0x00003F00U
#define MRV_DPCC_PG_FAC_3_RB_SHIFT 8U
/*! Slice: PG_FAC_3_G:*/
/*! Peak gradient factor for set 3 green */
#define MRV_DPCC_PG_FAC_3_G
#define MRV_DPCC_PG_FAC_3_G_MASK 0x0000003FU
#define MRV_DPCC_PG_FAC_3_G_SHIFT 0U
/*! Register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for set 3 (0x0000004c)*/
/*! Slice: RND_THR_3_RB:*/
/*! Rank Neighbor Difference threshold for set 3 red/blue */
#define MRV_DPCC_RND_THR_3_RB
#define MRV_DPCC_RND_THR_3_RB_MASK 0x0000FF00U
#define MRV_DPCC_RND_THR_3_RB_SHIFT 8U
/*! Slice: RND_THR_3_G:*/
/*! Rank Neighbor Difference threshold for set 3 green */
#define MRV_DPCC_RND_THR_3_G
#define MRV_DPCC_RND_THR_3_G_MASK 0x000000FFU
#define MRV_DPCC_RND_THR_3_G_SHIFT 0U
/*! Register: isp_dpcc_rg_fac_3: Rank gradient factor for set 3 (0x00000050)*/
/*! Slice: RG_FAC_3_RB:*/
/*! Rank gradient factor for set 3 red/blue */
#define MRV_DPCC_RG_FAC_3_RB
#define MRV_DPCC_RG_FAC_3_RB_MASK 0x00003F00U
#define MRV_DPCC_RG_FAC_3_RB_SHIFT 8U
/*! Slice: RG_FAC_3_G:*/
/*! Rank gradient factor for set 3 green */
#define MRV_DPCC_RG_FAC_3_G
#define MRV_DPCC_RG_FAC_3_G_MASK 0x0000003FU
#define MRV_DPCC_RG_FAC_3_G_SHIFT 0U
/*! Register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)*/
/*! Slice: RO_LIM_3_RB:*/
/*! Rank order limit for set 3 red/blue */
#define MRV_DPCC_RO_LIM_3_RB
#define MRV_DPCC_RO_LIM_3_RB_MASK 0x00000C00U
#define MRV_DPCC_RO_LIM_3_RB_SHIFT 10U
/*! Slice: RO_LIM_3_G:*/
/*! Rank order limit for set 3 green */
#define MRV_DPCC_RO_LIM_3_G
#define MRV_DPCC_RO_LIM_3_G_MASK 0x00000300U
#define MRV_DPCC_RO_LIM_3_G_SHIFT 8U
/*! Slice: RO_LIM_2_RB:*/
/*! Rank order limit for set 2 red/blue */
#define MRV_DPCC_RO_LIM_2_RB
#define MRV_DPCC_RO_LIM_2_RB_MASK 0x000000C0U
#define MRV_DPCC_RO_LIM_2_RB_SHIFT 6U
/*! Slice: RO_LIM_2_G:*/
/*! Rank order limit for set 2 green */
#define MRV_DPCC_RO_LIM_2_G
#define MRV_DPCC_RO_LIM_2_G_MASK 0x00000030U
#define MRV_DPCC_RO_LIM_2_G_SHIFT 4U
/*! Slice: RO_LIM_1_RB:*/
/*! Rank order limit for set 1 red/blue */
#define MRV_DPCC_RO_LIM_1_RB
#define MRV_DPCC_RO_LIM_1_RB_MASK 0x0000000CU
#define MRV_DPCC_RO_LIM_1_RB_SHIFT 2U
/*! Slice: RO_LIM_1_G:*/
/*! Rank order limit for set 1 green */
#define MRV_DPCC_RO_LIM_1_G
#define MRV_DPCC_RO_LIM_1_G_MASK 0x00000003U
#define MRV_DPCC_RO_LIM_1_G_SHIFT 0U
/*! Register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor Difference (0x00000058)*/
/*! Slice: RND_OFFS_3_RB:*/
/*! Rank Offset to Neighbor for set 3 red/blue */
#define MRV_DPCC_RND_OFFS_3_RB
#define MRV_DPCC_RND_OFFS_3_RB_MASK 0x00000C00U
#define MRV_DPCC_RND_OFFS_3_RB_SHIFT 10U
/*! Slice: RND_OFFS_3_G:*/
/*! Rank Offset to Neighbor for set 3 green */
#define MRV_DPCC_RND_OFFS_3_G
#define MRV_DPCC_RND_OFFS_3_G_MASK 0x00000300U
#define MRV_DPCC_RND_OFFS_3_G_SHIFT 8U
/*! Slice: RND_OFFS_2_RB:*/
/*! Rank Offset to Neighbor for set 2 red/blue */
#define MRV_DPCC_RND_OFFS_2_RB
#define MRV_DPCC_RND_OFFS_2_RB_MASK 0x000000C0U
#define MRV_DPCC_RND_OFFS_2_RB_SHIFT 6U
/*! Slice: RND_OFFS_2_G:*/
/*! Rank Offset to Neighbor for set 2 green */
#define MRV_DPCC_RND_OFFS_2_G
#define MRV_DPCC_RND_OFFS_2_G_MASK 0x00000030U
#define MRV_DPCC_RND_OFFS_2_G_SHIFT 4U
/*! Slice: RND_OFFS_1_RB:*/
/*! Rank Offset to Neighbor for set 1 red/blue */
#define MRV_DPCC_RND_OFFS_1_RB
#define MRV_DPCC_RND_OFFS_1_RB_MASK 0x0000000CU
#define MRV_DPCC_RND_OFFS_1_RB_SHIFT 2U
/*! Slice: RND_OFFS_1_G:*/
/*! Rank Offset to Neighbor for set 1 green */
#define MRV_DPCC_RND_OFFS_1_G
#define MRV_DPCC_RND_OFFS_1_G_MASK 0x00000003U
#define MRV_DPCC_RND_OFFS_1_G_SHIFT 0U
/*! Register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)*/
/*! Slice: BPT_RB_3x3:*/
/*! 1: if BPT active red/blue 9 pixel (3x3) output median */
/* 0: if BPT active red/blue 4 or 5 pixel output median  *Default**/
#define MRV_DPCC_BPT_RB_3X3
#define MRV_DPCC_BPT_RB_3X3_MASK 0x00000800U
#define MRV_DPCC_BPT_RB_3X3_SHIFT 11U
/*! Slice: BPT_G_3x3:*/
/*! 1: if BPT active green 9 pixel (3x3) output median */
/* 0: if BPT active green 4 or 5 pixel output median  *Default**/
#define MRV_DPCC_BPT_G_3X3
#define MRV_DPCC_BPT_G_3X3_MASK 0x00000400U
#define MRV_DPCC_BPT_G_3X3_SHIFT 10U
/*! Slice: BPT_INCL_RB_CENTER:*/
/*! 1: if BPT active include center pixel for red/blue output median 2x2+1 */
/* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/
#define MRV_DPCC_BPT_INCL_RB_CENTER
#define MRV_DPCC_BPT_INCL_RB_CENTER_MASK 0x00000200U
#define MRV_DPCC_BPT_INCL_RB_CENTER_SHIFT 9U
/*! Slice: BPT_INCL_GREEN_CENTER:*/
/*! 1: if BPT active include center pixel for green output median 2x2+1 */
/* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/
#define MRV_DPCC_BPT_INCL_GREEN_CENTER
#define MRV_DPCC_BPT_INCL_GREEN_CENTER_MASK 0x00000100U
#define MRV_DPCC_BPT_INCL_GREEN_CENTER_SHIFT 8U
/*! Slice: BPT_USE_FIX_SET:*/
/*! 1: for BPT write use hard coded methods set */
/* 0: for BPT write do not use hard coded methods set *Default**/
#define MRV_DPCC_BPT_USE_FIX_SET
#define MRV_DPCC_BPT_USE_FIX_SET_MASK 0x00000080U
#define MRV_DPCC_BPT_USE_FIX_SET_SHIFT 7U
/*! Slice: BPT_USE_SET_3:*/
/*! 1: for BPT write use methods set 3 */
/* 0: for BPT write do not use methods set 3 *Default**/
#define MRV_DPCC_BPT_USE_SET_3
#define MRV_DPCC_BPT_USE_SET_3_MASK 0x00000040U
#define MRV_DPCC_BPT_USE_SET_3_SHIFT 6U
/*! Slice: BPT_USE_SET_2:*/
/*! 1: for BPT write use methods set 2 */
/* 0: for BPT write do not use methods set 2 *Default**/
#define MRV_DPCC_BPT_USE_SET_2
#define MRV_DPCC_BPT_USE_SET_2_MASK 0x00000020U
#define MRV_DPCC_BPT_USE_SET_2_SHIFT 5U
/*! Slice: BPT_USE_SET_1:*/
/*! 1: for BPT write use methods set 1 */
/* 0: for BPT write do not use methods set 1 *Default**/
#define MRV_DPCC_BPT_USE_SET_1
#define MRV_DPCC_BPT_USE_SET_1_MASK 0x00000010U
#define MRV_DPCC_BPT_USE_SET_1_SHIFT 4U
/*! Slice: bpt_cor_en:*/
/*! table based correction enable */
/* 1: table based correction is enabled */
/* 0: table based correction is disabled */
#define MRV_DPCC_BPT_COR_EN
#define MRV_DPCC_BPT_COR_EN_MASK 0x00000002U
#define MRV_DPCC_BPT_COR_EN_SHIFT 1U
/*! Slice: bpt_det_en:*/
/*! Bad pixel detection write enable */
/* 1: bad pixel detection write to memory is enabled */
/* 0: bad pixel detection write to memory is disabled */
#define MRV_DPCC_BPT_DET_EN
#define MRV_DPCC_BPT_DET_EN_MASK 0x00000001U
#define MRV_DPCC_BPT_DET_EN_SHIFT 0U
/*! Register: isp_dpcc_bpt_number: Number of entries for bad pixel table (table based correction) (0x00000060)*/
/*! Slice: bp_number:*/
/*! Number of current Bad Pixel entries in bad pixel table (BPT)*/
#define MRV_DPCC_BP_NUMBER
#define MRV_DPCC_BP_NUMBER_MASK 0x00000FFFU
#define MRV_DPCC_BP_NUMBER_SHIFT 0U
/*! Register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction algorithm (0x00000064)*/
/*! Slice: bp_table_addr:*/
/*! Table RAM start address for read or write operations. The address counter is incremented at each read or write access to the data register (auto-increment mechanism).*/
#define MRV_DPCC_BP_TABLE_ADDR
#define MRV_DPCC_BP_TABLE_ADDR_MASK 0x000007FFU
#define MRV_DPCC_BP_TABLE_ADDR_SHIFT 0U
/*! Register: isp_dpcc_bpt_data: TABLE DATA register for read and write access of table RAM (0x00000068)*/
/*! Slice: bpt_v_addr:*/
/*! Bad Pixel vertical address (pixel position)*/
#define MRV_DPCC_BPT_V_ADDR
#define MRV_DPCC_BPT_V_ADDR_MASK 0x0FFF0000U
#define MRV_DPCC_BPT_V_ADDR_SHIFT 16U
/*! Slice: bpt_h_addr:*/
/*! Bad Pixel horizontal address (pixel position)*/
#define MRV_DPCC_BPT_H_ADDR
#define MRV_DPCC_BPT_H_ADDR_MASK 0x00001FFFU
#define MRV_DPCC_BPT_H_ADDR_SHIFT 0U
/*! Register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)*/
/*! Slice: WDR_RGB_FACTOR:*/
/*! rgb_factor defines how much influence the RGBmax approach has in comparison to Y. The illumination reference Iref is calculated according to the following formula:*/
/* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
/* So, rgb_factor = 0 means that the standard approach is used. Use of this factor requires that Iref has been selected, see WDR_USE_IREF.*/
/* Value range of rgb_factor: 0...8 */
#define MRV_WDR_RGB_FACTOR
#define MRV_WDR_RGB_FACTOR_MASK 0x00000F00U
#define MRV_WDR_RGB_FACTOR_SHIFT 8U
/*! Slice: WDR_DISABLE_TRANSIENT:*/
/*! 1: disable transient between Y and RGBY_max */
/* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/
/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
#define MRV_WDR_DISABLE_TRANSIENT
#define MRV_WDR_DISABLE_TRANSIENT_MASK 0x00000040U
#define MRV_WDR_DISABLE_TRANSIENT_SHIFT 6U
/*! Slice: WDR_USE_RGB7_8:*/
/*! 1: decrease RGBmax by 7/8 (for noise reduction)*/
/* 0: do not modify RGBmax *Default**/
/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
#define MRV_WDR_USE_RGB7_8
#define MRV_WDR_USE_RGB7_8_MASK 0x00000020U
#define MRV_WDR_USE_RGB7_8_SHIFT 5U
/*! Slice: WDR_USE_Y9_8:*/
/*! 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/
/* 0: only use R G B for maximum value calculation (RGBYmax approach)  *Default**/
/* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
#define MRV_WDR_USE_Y9_8
#define MRV_WDR_USE_Y9_8_MASK 0x00000010U
#define MRV_WDR_USE_Y9_8_SHIFT 4U
/*! Slice: WDR_USE_IREF:*/
/*! 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */
/* 0: use Y for ToneMapping and Gain calculation  *Default**/
/* Iref is calculated according to the following formula:*/
/* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
#define MRV_WDR_USE_IREF
#define MRV_WDR_USE_IREF_MASK 0x00000008U
#define MRV_WDR_USE_IREF_SHIFT 3U
/*! Slice: WDR_CR_MAPPING_DISABLE:*/
/*! 1: disable (bypass) Chrominance Mapping */
/* 0: enable Chrominance Mapping  *Default**/
/* requires that Luminance/chrominance color space has been selected */
#define MRV_WDR_CR_MAPPING_DISABLE
#define MRV_WDR_CR_MAPPING_DISABLE_MASK 0x00000004U
#define MRV_WDR_CR_MAPPING_DISABLE_SHIFT 2U
/*! Slice: WDR_COLOR_SPACE_SELECT:*/
/*! 1: R, G, B color space */
/* 0: Luminance/Chrominance color space  *Default**/
#define MRV_WDR_COLOR_SPACE_SELECT
#define MRV_WDR_COLOR_SPACE_SELECT_MASK 0x00000002U
#define MRV_WDR_COLOR_SPACE_SELECT_SHIFT 1U
/*! Slice: WDR_ENABLE:*/
/*! 1: enable WDR */
/* 0: bypass WDR  *Default**/
#define MRV_WDR_ENABLE
#define MRV_WDR_ENABLE_MASK 0x00000001U
#define MRV_WDR_ENABLE_SHIFT 0U
/*! Register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition (part 1) (0x00000004)*/
/*! Slice: WDR_dY8:*/
/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/
#define MRV_WDR_DY8
#define MRV_WDR_DY8_MASK 0x70000000U
#define MRV_WDR_DY8_SHIFT 28U
/*! Slice: WDR_dY7:*/
/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/
#define MRV_WDR_DY7
#define MRV_WDR_DY7_MASK 0x07000000U
#define MRV_WDR_DY7_SHIFT 24U
/*! Slice: WDR_dY6:*/
/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/
#define MRV_WDR_DY6
#define MRV_WDR_DY6_MASK 0x00700000U
#define MRV_WDR_DY6_SHIFT 20U
/*! Slice: WDR_dY5:*/
/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/
#define MRV_WDR_DY5
#define MRV_WDR_DY5_MASK 0x00070000U
#define MRV_WDR_DY5_SHIFT 16U
/*! Slice: WDR_dY4:*/
/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/
#define MRV_WDR_DY4
#define MRV_WDR_DY4_MASK 0x00007000U
#define MRV_WDR_DY4_SHIFT 12U
/*! Slice: WDR_dY3:*/
/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/
#define MRV_WDR_DY3
#define MRV_WDR_DY3_MASK 0x00000700U
#define MRV_WDR_DY3_SHIFT 8U
/*! Slice: WDR_dY2:*/
/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/
#define MRV_WDR_DY2
#define MRV_WDR_DY2_MASK 0x00000070U
#define MRV_WDR_DY2_SHIFT 4U
/*! Slice: WDR_dY1:*/
/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/
#define MRV_WDR_DY1
#define MRV_WDR_DY1_MASK 0x00000007U
#define MRV_WDR_DY1_SHIFT 0U
/*! Register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition (part 2) (0x00000008)*/
/*! Slice: WDR_dY16:*/
/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/
#define MRV_WDR_DY16
#define MRV_WDR_DY16_MASK 0x70000000U
#define MRV_WDR_DY16_SHIFT 28U
/*! Slice: WDR_dY15:*/
/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/
#define MRV_WDR_DY15
#define MRV_WDR_DY15_MASK 0x07000000U
#define MRV_WDR_DY15_SHIFT 24U
/*! Slice: WDR_dY14:*/
/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/
#define MRV_WDR_DY14
#define MRV_WDR_DY14_MASK 0x00700000U
#define MRV_WDR_DY14_SHIFT 20U
/*! Slice: WDR_dY13:*/
/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/
#define MRV_WDR_DY13
#define MRV_WDR_DY13_MASK 0x00070000U
#define MRV_WDR_DY13_SHIFT 16U
/*! Slice: WDR_dY12:*/
/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/
#define MRV_WDR_DY12
#define MRV_WDR_DY12_MASK 0x00007000U
#define MRV_WDR_DY12_SHIFT 12U
/*! Slice: WDR_dY11:*/
/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/
#define MRV_WDR_DY11
#define MRV_WDR_DY11_MASK 0x00000700U
#define MRV_WDR_DY11_SHIFT 8U
/*! Slice: WDR_dY10:*/
/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/
#define MRV_WDR_DY10
#define MRV_WDR_DY10_MASK 0x00000070U
#define MRV_WDR_DY10_SHIFT 4U
/*! Slice: WDR_dY9:*/
/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/
#define MRV_WDR_DY9
#define MRV_WDR_DY9_MASK 0x00000007U
#define MRV_WDR_DY9_SHIFT 0U
/*! Register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition (part 3) (0x0000000c)*/
/*! Slice: WDR_dY24:*/
/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/
#define MRV_WDR_DY24
#define MRV_WDR_DY24_MASK 0x70000000U
#define MRV_WDR_DY24_SHIFT 28U
/*! Slice: WDR_dY23:*/
/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/
#define MRV_WDR_DY23
#define MRV_WDR_DY23_MASK 0x07000000U
#define MRV_WDR_DY23_SHIFT 24U
/*! Slice: WDR_dY22:*/
/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/
#define MRV_WDR_DY22
#define MRV_WDR_DY22_MASK 0x00700000U
#define MRV_WDR_DY22_SHIFT 20U
/*! Slice: WDR_dY21:*/
/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/
#define MRV_WDR_DY21
#define MRV_WDR_DY21_MASK 0x00070000U
#define MRV_WDR_DY21_SHIFT 16U
/*! Slice: WDR_dY20:*/
/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/
#define MRV_WDR_DY20
#define MRV_WDR_DY20_MASK 0x00007000U
#define MRV_WDR_DY20_SHIFT 12U
/*! Slice: WDR_dY19:*/
/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/
#define MRV_WDR_DY19
#define MRV_WDR_DY19_MASK 0x00000700U
#define MRV_WDR_DY19_SHIFT 8U
/*! Slice: WDR_dY18:*/
/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/
#define MRV_WDR_DY18
#define MRV_WDR_DY18_MASK 0x00000070U
#define MRV_WDR_DY18_SHIFT 4U
/*! Slice: WDR_dY17:*/
/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/
#define MRV_WDR_DY17
#define MRV_WDR_DY17_MASK 0x00000007U
#define MRV_WDR_DY17_SHIFT 0U
/*! Register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition (part 4) (0x00000010)*/
/*! Slice: WDR_dY32:*/
/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/
#define MRV_WDR_DY32
#define MRV_WDR_DY32_MASK 0x70000000U
#define MRV_WDR_DY32_SHIFT 28U
/*! Slice: WDR_dY31:*/
/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/
#define MRV_WDR_DY31
#define MRV_WDR_DY31_MASK 0x07000000U
#define MRV_WDR_DY31_SHIFT 24U
/*! Slice: WDR_dY30:*/
/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/
#define MRV_WDR_DY30
#define MRV_WDR_DY30_MASK 0x00700000U
#define MRV_WDR_DY30_SHIFT 20U
/*! Slice: WDR_dY29:*/
/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/
#define MRV_WDR_DY29
#define MRV_WDR_DY29_MASK 0x00070000U
#define MRV_WDR_DY29_SHIFT 16U
/*! Slice: WDR_dY28:*/
/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/
#define MRV_WDR_DY28
#define MRV_WDR_DY28_MASK 0x00007000U
#define MRV_WDR_DY28_SHIFT 12U
/*! Slice: WDR_dY27:*/
/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/
#define MRV_WDR_DY27
#define MRV_WDR_DY27_MASK 0x00000700U
#define MRV_WDR_DY27_SHIFT 8U
/*! Slice: WDR_dY26:*/
/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/
#define MRV_WDR_DY26
#define MRV_WDR_DY26_MASK 0x00000070U
#define MRV_WDR_DY26_SHIFT 4U
/*! Slice: WDR_dY25:*/
/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/
#define MRV_WDR_DY25
#define MRV_WDR_DY25_MASK 0x00000007U
#define MRV_WDR_DY25_SHIFT 0U
/*! Register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ (0x0028 + n*0x4 (n=0..32))*/
/*! Slice: tonecurve_ym_n:*/
/* Tone curve value definition y-axis (output) of WDR unit */
#define MRV_WDR_TONECURVE_YM_N
#define MRV_WDR_TONECURVE_YM_N_MASK 0x00001FFFU
#define MRV_WDR_TONECURVE_YM_N_SHIFT 0U
/*! Register: isp_wdr_offset: Offset values for RGB path (0x00000098)*/
/*! Slice: LUM_OFFSET:*/
/*! Luminance Offset value (a) for RGB operation mode */
/* unsigned 12 bit value */
#define MRV_WDR_LUM_OFFSET
#define MRV_WDR_LUM_OFFSET_MASK 0x0FFF0000U
#define MRV_WDR_LUM_OFFSET_SHIFT 16U
/*! Slice: RGB_OFFSET:*/
/*! RGB Offset value (b) for RGB operation mode */
/* unsigned 12 bit value */
#define MRV_WDR_RGB_OFFSET
#define MRV_WDR_RGB_OFFSET_MASK 0x00000FFFU
#define MRV_WDR_RGB_OFFSET_SHIFT 0U
/*! Register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)*/
/*! Slice: DMIN_STRENGTH:*/
/*! strength factor for DMIN */
/* unsigned 5 bit value, range 0x00...0x10 */
#define MRV_WDR_DMIN_STRENGTH
#define MRV_WDR_DMIN_STRENGTH_MASK 0x001F0000U
#define MRV_WDR_DMIN_STRENGTH_SHIFT 16U
/*! Slice: DMIN_THRESH:*/
/*! Lower threshold for deltaMin value */
/* unsigned 12 bit value */
#define MRV_WDR_DMIN_THRESH
#define MRV_WDR_DMIN_THRESH_MASK 0x00000FFFU
#define MRV_WDR_DMIN_THRESH_SHIFT 0U
/*! Register: isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition shadow register (part 1) (0x000000a0)*/
/*! Slice: WDR_dY8:*/
/*! Tone curve sample point definition dY8 on the horizontal axis (input)*/
#define MRV_WDR_DY8
#define MRV_WDR_DY8_MASK 0x70000000U
#define MRV_WDR_DY8_SHIFT 28U
/*! Slice: WDR_dY7:*/
/*! Tone curve sample point definition dY7 on the horizontal axis (input)*/
#define MRV_WDR_DY7
#define MRV_WDR_DY7_MASK 0x07000000U
#define MRV_WDR_DY7_SHIFT 24U
/*! Slice: WDR_dY6:*/
/*! Tone curve sample point definition dY6 on the horizontal axis (input)*/
#define MRV_WDR_DY6
#define MRV_WDR_DY6_MASK 0x00700000U
#define MRV_WDR_DY6_SHIFT 20U
/*! Slice: WDR_dY5:*/
/*! Tone curve sample point definition dY5 on the horizontal axis (input)*/
#define MRV_WDR_DY5
#define MRV_WDR_DY5_MASK 0x00070000U
#define MRV_WDR_DY5_SHIFT 16U
/*! Slice: WDR_dY4:*/
/*! Tone curve sample point definition dY4 on the horizontal axis (input)*/
#define MRV_WDR_DY4
#define MRV_WDR_DY4_MASK 0x00007000U
#define MRV_WDR_DY4_SHIFT 12U
/*! Slice: WDR_dY3:*/
/*! Tone curve sample point definition dY3 on the horizontal axis (input)*/
#define MRV_WDR_DY3
#define MRV_WDR_DY3_MASK 0x00000700U
#define MRV_WDR_DY3_SHIFT 8U
/*! Slice: WDR_dY2:*/
/*! Tone curve sample point definition dY2 on the horizontal axis (input)*/
#define MRV_WDR_DY2
#define MRV_WDR_DY2_MASK 0x00000070U
#define MRV_WDR_DY2_SHIFT 4U
/*! Slice: WDR_dY1:*/
/*! Tone curve sample point definition dY1 on the horizontal axis (input)*/
#define MRV_WDR_DY1
#define MRV_WDR_DY1_MASK 0x00000007U
#define MRV_WDR_DY1_SHIFT 0U
/*! Register: isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition shadow register (part 2) (0x000000a4)*/
/*! Slice: WDR_dY16:*/
/*! Tone curve sample point definition dY16 on the horizontal axis (input)*/
#define MRV_WDR_DY16
#define MRV_WDR_DY16_MASK 0x70000000U
#define MRV_WDR_DY16_SHIFT 28U
/*! Slice: WDR_dY15:*/
/*! Tone curve sample point definition dY15 on the horizontal axis (input)*/
#define MRV_WDR_DY15
#define MRV_WDR_DY15_MASK 0x07000000U
#define MRV_WDR_DY15_SHIFT 24U
/*! Slice: WDR_dY14:*/
/*! Tone curve sample point definition dY14 on the horizontal axis (input)*/
#define MRV_WDR_DY14
#define MRV_WDR_DY14_MASK 0x00700000U
#define MRV_WDR_DY14_SHIFT 20U
/*! Slice: WDR_dY13:*/
/*! Tone curve sample point definition dY13 on the horizontal axis (input)*/
#define MRV_WDR_DY13
#define MRV_WDR_DY13_MASK 0x00070000U
#define MRV_WDR_DY13_SHIFT 16U
/*! Slice: WDR_dY12:*/
/*! Tone curve sample point definition dY12 on the horizontal axis (input)*/
#define MRV_WDR_DY12
#define MRV_WDR_DY12_MASK 0x00007000U
#define MRV_WDR_DY12_SHIFT 12U
/*! Slice: WDR_dY11:*/
/*! Tone curve sample point definition dY11 on the horizontal axis (input)*/
#define MRV_WDR_DY11
#define MRV_WDR_DY11_MASK 0x00000700U
#define MRV_WDR_DY11_SHIFT 8U
/*! Slice: WDR_dY10:*/
/*! Tone curve sample point definition dY10 on the horizontal axis (input)*/
#define MRV_WDR_DY10
#define MRV_WDR_DY10_MASK 0x00000070U
#define MRV_WDR_DY10_SHIFT 4U
/*! Slice: WDR_dY9:*/
/*! Tone curve sample point definition dY9 on the horizontal axis (input)*/
#define MRV_WDR_DY9
#define MRV_WDR_DY9_MASK 0x00000007U
#define MRV_WDR_DY9_SHIFT 0U
/*! Register: isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition shadow register (part 3) (0x000000a8)*/
/*! Slice: WDR_dY24:*/
/*! Tone curve sample point definition dY24 on the horizontal axis (input)*/
#define MRV_WDR_DY24
#define MRV_WDR_DY24_MASK 0x70000000U
#define MRV_WDR_DY24_SHIFT 28U
/*! Slice: WDR_dY23:*/
/*! Tone curve sample point definition dY23 on the horizontal axis (input)*/
#define MRV_WDR_DY23
#define MRV_WDR_DY23_MASK 0x07000000U
#define MRV_WDR_DY23_SHIFT 24U
/*! Slice: WDR_dY22:*/
/*! Tone curve sample point definition dY22 on the horizontal axis (input)*/
#define MRV_WDR_DY22
#define MRV_WDR_DY22_MASK 0x00700000U
#define MRV_WDR_DY22_SHIFT 20U
/*! Slice: WDR_dY21:*/
/*! Tone curve sample point definition dY21 on the horizontal axis (input)*/
#define MRV_WDR_DY21
#define MRV_WDR_DY21_MASK 0x00070000U
#define MRV_WDR_DY21_SHIFT 16U
/*! Slice: WDR_dY20:*/
/*! Tone curve sample point definition dY20 on the horizontal axis (input)*/
#define MRV_WDR_DY20
#define MRV_WDR_DY20_MASK 0x00007000U
#define MRV_WDR_DY20_SHIFT 12U
/*! Slice: WDR_dY19:*/
/*! Tone curve sample point definition dY19 on the horizontal axis (input)*/
#define MRV_WDR_DY19
#define MRV_WDR_DY19_MASK 0x00000700U
#define MRV_WDR_DY19_SHIFT 8U
/*! Slice: WDR_dY18:*/
/*! Tone curve sample point definition dY18 on the horizontal axis (input)*/
#define MRV_WDR_DY18
#define MRV_WDR_DY18_MASK 0x00000070U
#define MRV_WDR_DY18_SHIFT 4U
/*! Slice: WDR_dY17:*/
/*! Tone curve sample point definition dY17 on the horizontal axis (input)*/
#define MRV_WDR_DY17
#define MRV_WDR_DY17_MASK 0x00000007U
#define MRV_WDR_DY17_SHIFT 0U
/*! Register: isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition shadow register(part 4) (0x000000ac)*/
/*! Slice: WDR_dY32:*/
/*! Tone curve sample point definition dY32 on the horizontal axis (input)*/
#define MRV_WDR_DY32
#define MRV_WDR_DY32_MASK 0x70000000U
#define MRV_WDR_DY32_SHIFT 28U
/*! Slice: WDR_dY31:*/
/*! Tone curve sample point definition dY31 on the horizontal axis (input)*/
#define MRV_WDR_DY31
#define MRV_WDR_DY31_MASK 0x07000000U
#define MRV_WDR_DY31_SHIFT 24U
/*! Slice: WDR_dY30:*/
/*! Tone curve sample point definition dY30 on the horizontal axis (input)*/
#define MRV_WDR_DY30
#define MRV_WDR_DY30_MASK 0x00700000U
#define MRV_WDR_DY30_SHIFT 20U
/*! Slice: WDR_dY29:*/
/*! Tone curve sample point definition dY29 on the horizontal axis (input)*/
#define MRV_WDR_DY29
#define MRV_WDR_DY29_MASK 0x00070000U
#define MRV_WDR_DY29_SHIFT 16U
/*! Slice: WDR_dY28:*/
/*! Tone curve sample point definition dY28 on the horizontal axis (input)*/
#define MRV_WDR_DY28
#define MRV_WDR_DY28_MASK 0x00007000U
#define MRV_WDR_DY28_SHIFT 12U
/*! Slice: WDR_dY27:*/
/*! Tone curve sample point definition dY27 on the horizontal axis (input)*/
#define MRV_WDR_DY27
#define MRV_WDR_DY27_MASK 0x00000700U
#define MRV_WDR_DY27_SHIFT 8U
/*! Slice: WDR_dY26:*/
/*! Tone curve sample point definition dY26 on the horizontal axis (input)*/
#define MRV_WDR_DY26
#define MRV_WDR_DY26_MASK 0x00000070U
#define MRV_WDR_DY26_SHIFT 4U
/*! Slice: WDR_dY25:*/
/*! Tone curve sample point definition dY25 on the horizontal axis (input)*/
#define MRV_WDR_DY25
#define MRV_WDR_DY25_MASK 0x00000007U
#define MRV_WDR_DY25_SHIFT 0U
/*! Register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient shadow register (0x0160 + n*0x4 (n=0..32))*/
/*! Slice: tonecurve_ym_n_shd:*/
/* Tone curve value definition y-axis (output) of WDR unit */
/* shadow register.*/
#define MRV_WDR_TONECURVE_YM_N_SHD
#define MRV_WDR_TONECURVE_YM_N_SHD_MASK 0x00001FFFU
#define MRV_WDR_TONECURVE_YM_N_SHD_SHIFT 0U
/*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/
/*! Slice: AWB_union_e5_and_e8:*/
/*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/
#define ISP_AWB_UNION_E5_AND_E8
#define ISP_AWB_UNION_E5_AND_E8_MASK 0x00000200U
#define ISP_AWB_UNION_E5_AND_E8_SHIFT 9U
/*! Slice: AWB_union_e5_and_e7:*/
/*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/
#define ISP_AWB_UNION_E5_AND_E7
#define ISP_AWB_UNION_E5_AND_E7_MASK 0x00000100U
#define ISP_AWB_UNION_E5_AND_E7_SHIFT 8U
/*! Slice: AWB_union_e5_and_e6:*/
/*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/
#define ISP_AWB_UNION_E5_AND_E6
#define ISP_AWB_UNION_E5_AND_E6_MASK 0x00000080U
#define ISP_AWB_UNION_E5_AND_E6_SHIFT 7U
/*! Slice: AWB_union_e1_and_e4:*/
/*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/
#define ISP_AWB_UNION_E1_AND_E4
#define ISP_AWB_UNION_E1_AND_E4_MASK 0x00000040U
#define ISP_AWB_UNION_E1_AND_E4_SHIFT 6U
/*! Slice: AWB_union_e1_and_e3:*/
/*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/
#define ISP_AWB_UNION_E1_AND_E3
#define ISP_AWB_UNION_E1_AND_E3_MASK 0x00000020U
#define ISP_AWB_UNION_E1_AND_E3_SHIFT 5U
/*! Slice: AWB_union_e1_and_e2:*/
/*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/
#define ISP_AWB_UNION_E1_AND_E2
#define ISP_AWB_UNION_E1_AND_E2_MASK 0x00000010U
#define ISP_AWB_UNION_E1_AND_E2_SHIFT 4U
/*! Slice: AWB_meas_chrom_switch:*/
/*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/
#define ISP_AWB_MEAS_CHROM_SWITCH
#define ISP_AWB_MEAS_CHROM_SWITCH_MASK 0x00000008U
#define ISP_AWB_MEAS_CHROM_SWITCH_SHIFT 3U
/*! Slice: AWB_meas_irq_enable:*/
/*! AWB measure done IRQ enable.*/
#define ISP_AWB_MEAS_IRQ_ENABLE
#define ISP_AWB_MEAS_IRQ_ENABLE_MASK 0x00000004U
#define ISP_AWB_MEAS_IRQ_ENABLE_SHIFT 2U
/*! Slice: AWB_pre_filt_en:*/
/*! median pre filter enable.*/
#define ISP_AWB_PRE_FILT_EN
#define ISP_AWB_PRE_FILT_EN_MASK 0x00000002U
#define ISP_AWB_PRE_FILT_EN_SHIFT 1U
/*! Slice: AWB_meas_en:*/
/*! enable measure.*/
#define ISP_AWB_MEAS_EN
#define ISP_AWB_MEAS_EN_MASK 0x00000001U
#define ISP_AWB_MEAS_EN_SHIFT 0U
/*! Register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)*/
/*! Slice: AWB_h_offset:*/
/*! Horizontal offset in pixels.*/
#define ISP_AWB_H_OFFSET
#define ISP_AWB_H_OFFSET_MASK 0x00001FFFU
#define ISP_AWB_H_OFFSET_SHIFT 0U
/*! Register: awb_meas_v_offs: AWB window vertical offset (0x00000008)*/
/*! Slice: AWB_v_offset:*/
/*! Vertical offset in pixels.*/
#define ISP_AWB_V_OFFSET
#define ISP_AWB_V_OFFSET_MASK 0x00001FFFU
#define ISP_AWB_V_OFFSET_SHIFT 0U
/*! Register: awb_meas_h_size: Horizontal window size (0x0000000c)*/
/*! Slice: AWB_h_size:*/
/*! Horizontal size in pixels.*/
#define ISP_AWB_H_SIZE
#define ISP_AWB_H_SIZE_MASK 0x00003FFFU
#define ISP_AWB_H_SIZE_SHIFT 0U
/*! Register: awb_meas_v_size: Vertical window size (0x00000010)*/
/*! Slice: AWB_v_size:*/
/*! Vertical size.*/
#define ISP_AWB_V_SIZE
#define ISP_AWB_V_SIZE_MASK 0x00003FFFU
#define ISP_AWB_V_SIZE_SHIFT 0U
/*! Register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)*/
/*! Slice: r_max:*/
/*! max red value */
#define ISP_AWB_R_MAX
#define ISP_AWB_R_MAX_MASK 0x0000FF00U
#define ISP_AWB_R_MAX_SHIFT 8U
/*! Slice: r_min:*/
/*! min red value */
#define ISP_AWB_R_MIN
#define ISP_AWB_R_MIN_MASK 0x000000FFU
#define ISP_AWB_R_MIN_SHIFT 0U
/*! Register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)*/
/*! Slice: g_max:*/
/*! max green value */
#define ISP_AWB_G_MAX
#define ISP_AWB_G_MAX_MASK 0x0000FF00U
#define ISP_AWB_G_MAX_SHIFT 8U
/*! Slice: g_min:*/
/*! min green value */
#define ISP_AWB_G_MIN
#define ISP_AWB_G_MIN_MASK 0x000000FFU
#define ISP_AWB_G_MIN_SHIFT 0U
/*! Register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)*/
/*! Slice: b_max:*/
/*! max blue value */
#define ISP_AWB_B_MAX
#define ISP_AWB_B_MAX_MASK 0x0000FF00U
#define ISP_AWB_B_MAX_SHIFT 8U
/*! Slice: b_min:*/
/*! min blue value */
#define ISP_AWB_B_MIN
#define ISP_AWB_B_MIN_MASK 0x000000FFU
#define ISP_AWB_B_MIN_SHIFT 0U
/*! Register: awb_meas_divider_min: Min Compare Divider (0x00000020)*/
/*! Slice: div_min:*/
/*! min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */
#define ISP_AWB_DIV_MIN
#define ISP_AWB_DIV_MIN_MASK 0x000003FFU
#define ISP_AWB_DIV_MIN_SHIFT 0U
/*! Register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)*/
/*! Slice: cc_coeff_0:*/
/*! coefficient 0 for color space conversion */
#define ISP_AWB_CC_COEFF_0
#define ISP_AWB_CC_COEFF_0_MASK 0x000007FFU
#define ISP_AWB_CC_COEFF_0_SHIFT 0U
/*! Register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)*/
/*! Slice: ellip1_cen_x:*/
/*! Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
#define ISP_AWB_ELLIP1_CEN_X
#define ISP_AWB_ELLIP1_CEN_X_MASK 0x000003FFU
#define ISP_AWB_ELLIP1_CEN_X_SHIFT 0U
/*! Register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)*/
/*! Slice: ellip1_cen_y:*/
/*! Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
#define ISP_AWB_ELLIP1_CEN_Y
#define ISP_AWB_ELLIP1_CEN_Y_MASK 0x000003FFU
#define ISP_AWB_ELLIP1_CEN_Y_SHIFT 0U
/*! Register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)*/
/*! Slice: ellip1_a1:*/
/*! Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
#define ISP_AWB_ELLIP1_A1
#define ISP_AWB_ELLIP1_A1_MASK 0x00000FFFU
#define ISP_AWB_ELLIP1_A1_SHIFT 0U
/*! Register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)*/
/*! Slice: ellip1_a2:*/
/*! Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
#define ISP_AWB_ELLIP1_A2
#define ISP_AWB_ELLIP1_A2_MASK 0x000001FFU
#define ISP_AWB_ELLIP1_A2_SHIFT 0U
/*! Register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)*/
/*! Slice: ellip1_a3:*/
/*! Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
#define ISP_AWB_ELLIP1_A3
#define ISP_AWB_ELLIP1_A3_MASK 0x00000FFFU
#define ISP_AWB_ELLIP1_A3_SHIFT 0U
/*! Register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)*/
/*! Slice: ellip1_a4:*/
/*! Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
#define ISP_AWB_ELLIP1_A4
#define ISP_AWB_ELLIP1_A4_MASK 0x000001FFU
#define ISP_AWB_ELLIP1_A4_SHIFT 0U
/*! Register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)*/
/*! Slice: ellip1_rmax:*/
/*! Ellipse 1 max radius square compare value */
#define ISP_AWB_ELLIP1_RMAX
#define ISP_AWB_ELLIP1_RMAX_MASK 0x00FFFFFFU
#define ISP_AWB_ELLIP1_RMAX_SHIFT 0U
/*! Register: awb_meas_counter_1: AWB Counter 1 (0x00000128)*/
/*! Slice: count_1:*/
/*! counted Pixels of Ellipse 1 */
#define ISP_AWB_COUNT_1
#define ISP_AWB_COUNT_1_MASK 0x00FFFFFFU
#define ISP_AWB_COUNT_1_SHIFT 0U
/*! Register array: awb_meas_accu: AWB Accu Read (0x290 + n*0x4 (n=0..23))*/
/*! Slice: read_accu:*/
/* measured sum[34:3] of RGB values.*/
#define ISP_AWB_READ_ACCU
#define ISP_AWB_READ_ACCU_MASK 0xFFFFFFFFU
#define ISP_AWB_READ_ACCU_SHIFT 0U
/*! Register: isp64_hist_ctrl: Histogram control (0x00000000)*/
/*! Slice: hist_update_enable:*/
/*! 0: automatic register update at end of measuement ot frame denied */
/* 1: automatic register update at end of measuement ot frame enabled.*/
#define MRV_HIST_UPDATE_ENABLE
#define MRV_HIST_UPDATE_ENABLE_MASK 0x00000001U
#define MRV_HIST_UPDATE_ENABLE_SHIFT 0U
/*! Register: isp64_hist_prop: Histogram properties (0x00000004)*/
/*! Slice: channel_select:*/
/*! select 1 out of max. 8 input channels */
/* 7: channel 7 */
/* 6: channel 6 */
/* 5: channel 5 */
/* 4: channel 4 */
/* 3: channel 3 */
/* 2: channel 2 */
/* 1: channel 1 */
/* 0: channel 0 */
/* The channels might be RGB or Bayer channels. Each channel provides 3 subchannels for tranfer the RGB component data. However if the channel operates in bayer mode only subchannel 0 is used transferring the interleaved bayer pattern data. Check with top level specification to discover the channel type.*/
#define MRV_HIST_CHANNEL_SELECT
#define MRV_HIST_CHANNEL_SELECT_MASK 0x00000038U
#define MRV_HIST_CHANNEL_SELECT_SHIFT 3U
/*! Slice: hist_mode:*/
/*! histogram mode (RGB/Bayer)*/
/* 7, 6: reserved */
/* 5: bayer Gb histogram */
/* 4: bayer B histogram */
/* 3: bayer Gr histogram */
/* 2: bayer R histogram */
/* 1: Y/R/G/B histogram controlled via coefficients coeff_r/g/b */
/* 0: disable, no measurements */
/* With histogram mode 1 all three subchannels are used. Modes 2...5 use only th subchannel 0 which transfers the bayer pattern data. Check with top level specification to discover the channel type.*/
#define MRV_HIST_MODE
#define MRV_HIST_MODE_MASK 0x00000007U
#define MRV_HIST_MODE_SHIFT 0U
/*! Register: isp64_hist_subsampling: Subsampling properties (0x00000008)*/
/*! Slice: v_stepsize:*/
/*! histogram veritcal predivider, process every (stepsize)th line, all other lines are skipped */
/* RGB mode:*/
/* 0: not allowed */
/* 1: process every input line */
/* 2: process every second line */
/* 3: process every third input line */
/* 4: process every fourth input line */
/* ...*/
/* 7FH: process every 127th line */
/* Bayer mode:*/
/* 0: not allowed */
/* 1: process every second input line */
/* 2: process every fourth line */
/* 3: process every sixth input line */
/* 4: process every eighth input line */
/* ...*/
/* 7FH: process every 254th line */
/* In bayer mode vertical subsampling will start at the 1st input line which contain the bayer component selected in ISP64_HIST_PROP::hist_mode.*/
#define MRV_HIST_V_STEPSIZE
#define MRV_HIST_V_STEPSIZE_MASK 0x7F000000U
#define MRV_HIST_V_STEPSIZE_SHIFT 24U
/*! Slice: h_step_inc:*/
/*! horizontal subsampling step counter increment.*/
/* In RGB mode the subsampling counter cnt is incremented by h_step_inc with every input pixel (cnt %= cnt + h_step_inc). A valid subsampling position is reached when cnt would result in a value %= 2^16. In this case the new counter value is cnt = cnt + h_step_inc - 2^16. For example if every incoming pixel shall be selected configure h_step_inc = 2^16.*/
/* In Bayer mode the behaviour is similar but for the fact that cnt is only incremented for pixels which belong to the bayer component selected in ISP64_HIST_PROP::hist_mode.*/
#define MRV_HIST_H_STEP_INC
#define MRV_HIST_H_STEP_INC_MASK 0x0001FFFFU
#define MRV_HIST_H_STEP_INC_SHIFT 0U
/*! Register: isp64_hist_coeff_r: Color conversion coefficient for red (0x0000000c)*/
/*! Slice: coeff_r:*/
/*! coefficient for red for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
#define MRV_HIST_COEFF_R
#define MRV_HIST_COEFF_R_MASK 0x000000FFU
#define MRV_HIST_COEFF_R_SHIFT 0U
/*! Register: isp64_hist_coeff_g: Color conversion coefficient for green (0x00000010)*/
/*! Slice: coeff_g:*/
/*! coefficient for green for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
#define MRV_HIST_COEFF_G
#define MRV_HIST_COEFF_G_MASK 0x000000FFU
#define MRV_HIST_COEFF_G_SHIFT 0U
/*! Register: isp64_hist_coeff_b: Color conversion coefficient for blue (0x00000014)*/
/*! Slice: coeff_b:*/
/*! coefficient for blue for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
#define MRV_HIST_COEFF_B
#define MRV_HIST_COEFF_B_MASK 0x000000FFU
#define MRV_HIST_COEFF_B_SHIFT 0U
/*! Register: isp64_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000018)*/
/*! Slice: hist_h_offset:*/
/*! Horizontal offset of first window in pixels.*/
#define MRV_HIST_H_OFFSET
#define MRV_HIST_H_OFFSET_MASK 0x00001FFFU
#define MRV_HIST_H_OFFSET_SHIFT 0U
/*! Register: isp64_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x0000001c)*/
/*! Slice: hist_v_offset:*/
/*! Vertical offset of first window in pixels.*/
#define MRV_HIST_V_OFFSET
#define MRV_HIST_V_OFFSET_MASK 0x00001FFFU
#define MRV_HIST_V_OFFSET_SHIFT 0U
/*! Register: isp64_hist_h_size: Horizontal (sub-)window size (0x00000020)*/
/*! Slice: hist_h_size:*/
/*! Horizontal size in pixels of one sub-window.*/
#define MRV_HIST_H_SIZE
#define MRV_HIST_H_SIZE_MASK 0x000007FFU
#define MRV_HIST_H_SIZE_SHIFT 0U
/*! Register: isp64_hist_v_size: Vertical (sub-)window size (0x00000024)*/
/*! Slice: hist_v_size:*/
/*! Vertical size in lines of one sub-window.*/
#define MRV_HIST_V_SIZE
#define MRV_HIST_V_SIZE_MASK 0x000007FFU
#define MRV_HIST_V_SIZE_SHIFT 0U
/*! Register: isp64_hist_sample_range: Weighting factor for sub-windows (0x00000028)*/
/*! Slice: sample_shift:*/
/*! sample (left) shift will be executed after offset subtraction and prior to histogram evaluation */
#define MRV_HIST_SAMPLE_SHIFT
#define MRV_HIST_SAMPLE_SHIFT_MASK 0x00070000U
#define MRV_HIST_SAMPLE_SHIFT_SHIFT 16U
/*! Slice: sample_offset:*/
/*! sample offset will be subtracted from input sample prior to shift and histogram evaluation */
#define MRV_HIST_SAMPLE_OFFSET
#define MRV_HIST_SAMPLE_OFFSET_MASK 0x00000FFFU
#define MRV_HIST_SAMPLE_OFFSET_SHIFT 0U
/*! Register: isp64_hist_weight_00to30: Weighting factor for sub-windows (0x0000002c)*/
/*! Slice: hist_weight_30:*/
/*! weighting factor for sub-window 30 */
#define MRV_HIST_WEIGHT_30
#define MRV_HIST_WEIGHT_30_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_30_SHIFT 24U
/*! Slice: hist_weight_20:*/
/*! weighting factor for sub-window 20 */
#define MRV_HIST_WEIGHT_20
#define MRV_HIST_WEIGHT_20_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_20_SHIFT 16U
/*! Slice: hist_weight_10:*/
/*! weighting factor for sub-window 10 */
#define MRV_HIST_WEIGHT_10
#define MRV_HIST_WEIGHT_10_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_10_SHIFT 8U
/*! Slice: hist_weight_00:*/
/*! weighting factor for sub-window 00 */
#define MRV_HIST_WEIGHT_00
#define MRV_HIST_WEIGHT_00_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_00_SHIFT 0U
/*! Register: isp64_hist_weight_40to21: Weighting factor for sub-windows (0x00000030)*/
/*! Slice: hist_weight_21:*/
/*! weighting factor for sub-window 21 */
#define MRV_HIST_WEIGHT_21
#define MRV_HIST_WEIGHT_21_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_21_SHIFT 24U
/*! Slice: hist_weight_11:*/
/*! weighting factor for sub-window 11 */
#define MRV_HIST_WEIGHT_11
#define MRV_HIST_WEIGHT_11_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_11_SHIFT 16U
/*! Slice: hist_weight_01:*/
/*! weighting factor for sub-window 01 */
#define MRV_HIST_WEIGHT_01
#define MRV_HIST_WEIGHT_01_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_01_SHIFT 8U
/*! Slice: hist_weight_40:*/
/*! weighting factor for sub-window 40 */
#define MRV_HIST_WEIGHT_40
#define MRV_HIST_WEIGHT_40_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_40_SHIFT 0U
/*! Register: isp64_hist_weight_31to12: Weighting factor for sub-windows (0x00000034)*/
/*! Slice: hist_weight_12:*/
/*! weighting factor for sub-window 12 */
#define MRV_HIST_WEIGHT_12
#define MRV_HIST_WEIGHT_12_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_12_SHIFT 24U
/*! Slice: hist_weight_02:*/
/*! weighting factor for sub-window 02 */
#define MRV_HIST_WEIGHT_02
#define MRV_HIST_WEIGHT_02_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_02_SHIFT 16U
/*! Slice: hist_weight_41:*/
/*! weighting factor for sub-window 41 */
#define MRV_HIST_WEIGHT_41
#define MRV_HIST_WEIGHT_41_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_41_SHIFT 8U
/*! Slice: hist_weight_31:*/
/*! weighting factor for sub-window 31 */
#define MRV_HIST_WEIGHT_31
#define MRV_HIST_WEIGHT_31_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_31_SHIFT 0U
/*! Register: isp64_hist_weight_22to03: Weighting factor for sub-windows (0x00000038)*/
/*! Slice: hist_weight_03:*/
/*! weighting factor for sub-window 03 */
#define MRV_HIST_WEIGHT_03
#define MRV_HIST_WEIGHT_03_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_03_SHIFT 24U
/*! Slice: hist_weight_42:*/
/*! weighting factor for sub-window 42 */
#define MRV_HIST_WEIGHT_42
#define MRV_HIST_WEIGHT_42_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_42_SHIFT 16U
/*! Slice: hist_weight_32:*/
/*! weighting factor for sub-window 32 */
#define MRV_HIST_WEIGHT_32
#define MRV_HIST_WEIGHT_32_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_32_SHIFT 8U
/*! Slice: hist_weight_22:*/
/*! weighting factor for sub-window 22 */
#define MRV_HIST_WEIGHT_22
#define MRV_HIST_WEIGHT_22_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_22_SHIFT 0U
/*! Register: isp64_hist_weight_13to43: Weighting factor for sub-windows (0x0000003c)*/
/*! Slice: hist_weight_43:*/
/*! weighting factor for sub-window 43 */
#define MRV_HIST_WEIGHT_43
#define MRV_HIST_WEIGHT_43_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_43_SHIFT 24U
/*! Slice: hist_weight_33:*/
/*! weighting factor for sub-window 33 */
#define MRV_HIST_WEIGHT_33
#define MRV_HIST_WEIGHT_33_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_33_SHIFT 16U
/*! Slice: hist_weight_23:*/
/*! weighting factor for sub-window 23 */
#define MRV_HIST_WEIGHT_23
#define MRV_HIST_WEIGHT_23_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_23_SHIFT 8U
/*! Slice: hist_weight_13:*/
/*! weighting factor for sub-window 13 */
#define MRV_HIST_WEIGHT_13
#define MRV_HIST_WEIGHT_13_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_13_SHIFT 0U
/*! Register: isp64_hist_weight_04to34: Weighting factor for sub-windows (0x00000040)*/
/*! Slice: hist_weight_34:*/
/*! weighting factor for sub-window 34 */
#define MRV_HIST_WEIGHT_34
#define MRV_HIST_WEIGHT_34_MASK 0x1F000000U
#define MRV_HIST_WEIGHT_34_SHIFT 24U
/*! Slice: hist_weight_24:*/
/*! weighting factor for sub-window 24 */
#define MRV_HIST_WEIGHT_24
#define MRV_HIST_WEIGHT_24_MASK 0x001F0000U
#define MRV_HIST_WEIGHT_24_SHIFT 16U
/*! Slice: hist_weight_14:*/
/*! weighting factor for sub-window 14 */
#define MRV_HIST_WEIGHT_14
#define MRV_HIST_WEIGHT_14_MASK 0x00001F00U
#define MRV_HIST_WEIGHT_14_SHIFT 8U
/*! Slice: hist_weight_04:*/
/*! weighting factor for sub-window 04 */
#define MRV_HIST_WEIGHT_04
#define MRV_HIST_WEIGHT_04_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_04_SHIFT 0U
/*! Register: isp64_hist_weight_44: Weighting factor for sub-windows (0x00000044)*/
/*! Slice: hist_weight_44:*/
/*! weighting factor for sub-window 44 */
#define MRV_HIST_WEIGHT_44
#define MRV_HIST_WEIGHT_44_MASK 0x0000001FU
#define MRV_HIST_WEIGHT_44_SHIFT 0U
/*! Register: isp64_hist_forced_upd_start_line: Forced update start line limit (0x00000048)*/
/*! Slice: forced_upd_start_line:*/
/*! start line for histogram calculation in case of forced update. histogram is started as soon as current line < forced_upd_start_line. Used start line will be given in ISP64_HIST_VSTART_STATUS.*/
#define MRV_HIST_FORCED_UPD_START_LINE
#define MRV_HIST_FORCED_UPD_START_LINE_MASK 0x00001FFFU
#define MRV_HIST_FORCED_UPD_START_LINE_SHIFT 0U
/*! Register: isp64_hist_forced_update: Histogram forced update (0x0000004c)*/
/*! Slice: forced_upd:*/
/*! 0: no effect */
/* 1: forcing register update.*/
#define MRV_HIST_FORCED_UPD
#define MRV_HIST_FORCED_UPD_MASK 0x00000001U
#define MRV_HIST_FORCED_UPD_SHIFT 0U
/*! Register: isp64_hist_vstart_status: Forced update start line status (0x00000050)*/
/*! Slice: hist_vstart_status:*/
/*! start line for histogram. Important in case of backward switching because 1st histogram after switch might not cover the complete image.*/
#define MRV_HIST_VSTART_STATUS
#define MRV_HIST_VSTART_STATUS_MASK 0x00001FFFU
#define MRV_HIST_VSTART_STATUS_SHIFT 0U
/*! Register array: isp64_hist_bin: histogram measurement result bin (0x0A8 + n*0x4 (n=0..31))*/
/*! Slice: hist_bin:*/
/* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
#define MRV_HIST_BIN
#define MRV_HIST_BIN_MASK 0x000FFFFFU
#define MRV_HIST_BIN_SHIFT 0U
/*! Register: isp_vsm_mode: VS Measure Mode (0x00000000)*/
/*! Slice: vsm_meas_irq_enable:*/
/*! 1: VS measure done IRQ enable.*/
#define ISP_VSM_MEAS_IRQ_ENABLE
#define ISP_VSM_MEAS_IRQ_ENABLE_MASK 0x00000002U
#define ISP_VSM_MEAS_IRQ_ENABLE_SHIFT 1U
/*! Slice: vsm_meas_en:*/
/*! 1: enable measure.*/
#define ISP_VSM_MEAS_EN
#define ISP_VSM_MEAS_EN_MASK 0x00000001U
#define ISP_VSM_MEAS_EN_SHIFT 0U
/*! Register: isp_vsm_h_offs: VSM window horizontal offset (0x00000004)*/
/*! Slice: vsm_h_offset:*/
/*! Horizontal offset in pixels.*/
#define ISP_VSM_H_OFFSET
#define ISP_VSM_H_OFFSET_MASK 0x00001FFFU
#define ISP_VSM_H_OFFSET_SHIFT 0U
/*! Register: isp_vsm_v_offs: VSM window vertical offset (0x00000008)*/
/*! Slice: vsm_v_offset:*/
/*! Vertical offset in pixels.*/
#define ISP_VSM_V_OFFSET
#define ISP_VSM_V_OFFSET_MASK 0x00001FFFU
#define ISP_VSM_V_OFFSET_SHIFT 0U
/*! Register: isp_vsm_h_size: Horizontal measure window size (0x0000000c)*/
/*! Slice: vsm_h_size:*/
/*! Horizontal size in pixels. Range 64..1920 */
#define ISP_VSM_H_SIZE
#define ISP_VSM_H_SIZE_MASK 0x00000780U
#define ISP_VSM_H_SIZE_SHIFT 1U
/*! Register: isp_vsm_v_size: Vertical measure window size (0x00000010)*/
/*! Slice: vsm_v_size:*/
/*! Vertical size. Range 64..1088 */
#define ISP_VSM_V_SIZE
#define ISP_VSM_V_SIZE_MASK 0x00000440U
#define ISP_VSM_V_SIZE_SHIFT 1U
/*! Register: isp_vsm_h_segments: Iteration 1 horizontal segments (0x00000014)*/
/*! Slice: vsm_h_segments:*/
/*! number of 16 point wide segments enclosed by the first iteration sample points in horizontal direction. Range: 1 ... 128 */
#define ISP_VSM_H_SEGMENTS
#define ISP_VSM_H_SEGMENTS_MASK 0x000000FFU
#define ISP_VSM_H_SEGMENTS_SHIFT 0U
/*! Register: isp_vsm_v_segments: Iteration 1 vertical segments (0x00000018)*/
/*! Slice: vsm_v_segments:*/
/*! number of 16 point wide segments enclosed by the first iteration sample points in vertical direction. Range: 1 ... 128 */
#define ISP_VSM_V_SEGMENTS
#define ISP_VSM_V_SEGMENTS_MASK 0x000000FFU
#define ISP_VSM_V_SEGMENTS_SHIFT 0U
/*! Register: isp_vsm_delta_h: estimated horizontal displacement (0x0000001c)*/
/*! Slice: delta_h:*/
/*! estimated horizontal displacement 12Bit two's complement. positive values indicate a displacement of the image from right to left (camera turns right)*/
#define ISP_VSM_DELTA_H
#define ISP_VSM_DELTA_H_MASK 0x00000FFFU
#define ISP_VSM_DELTA_H_SHIFT 0U
/*! Register: isp_vsm_delta_v: estimated vertical displacement (0x00000020)*/
/*! Slice: delta_v:*/
/*! estimated vertical displacement 12Bit two's complement. positive values indicate a displacement of the image from bottom to top (camera turns down)*/
#define ISP_VSM_DELTA_V
#define ISP_VSM_DELTA_V_MASK 0x00000FFFU
#define ISP_VSM_DELTA_V_SHIFT 0U
#ifdef ISP_RGBGC
/*! Register: isp_ctrl:isp control register (0x00000400)*/
/*! Slice: rgb_gc_enable */
/*! Control of rgb gamma correction */
/*! 1'b0: disable rgb GC bypass mode */
/*! 1'b1: enable rgb GC mode */
#define ISP_RGBGC_ENABLE
#define ISP_RGBGC_ENABLE_MASK  0x00000800U
#define ISP_RGBGC_ENABLE_SHIFT 11U
#endif
#ifdef ISP_GCMONO
/*! Register: isp_ctrl:isp control register (0x00000400)*/
/*! Slice: mono_gc_enable */
/*! Control of gamma correction for mono sensor RAW data */
/*! 1'b0: disable GC bypass mode */
/*! 1'b1: enable GC mode */
#define ISP_GCMONO_ENABLE
#define ISP_GCMONO_ENABLE_MASK  0x00080000U
#define ISP_GCMONO_ENABLE_SHIFT 19U
/*! Register: isp_ctrl:isp control register (0x00000400)*/
/*! Slice: mono_gc_mode */
/*! Control of gamma correction for mono sensor RAW data mode */
/*! 1'b0: 0: 10->8 */
/*! 1'b1: 12->10 */
#define ISP_GCMONO_MODE
#define ISP_GCMONO_MODE_MASK  0x00100000U
#define ISP_GCMONO_MODE_SHIFT 20
/*! Register: isp_gcmono_ctrl: GC Mono control register (0x00000000)*/
/*! Slice: mono_gc_enable */
/*! Control of gamma correction for mono sensor RAW data */
/*! 1'b0: disable GC bypass mode */
/*! 1'b1: enable GC mode */
#define ISP_GCMONO_SWITCH
#define ISP_GCMONO_SWITCH_MASK  0x00000001U
#define ISP_GCMONO_SWITCH_SHIFT 0U
/*! Slice: mono_gc_cfg_done */
/*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/
/*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/
#define ISP_GCMONO_CFG_DONE
#define ISP_GCMONO_CFG_DONE_MASK  0x00000002U
#define ISP_GCMONO_CFG_DONE_SHIFT 1U
/*! Register: isp_gcmono_para_base: GC Mono Gamma LUT for mono sensor (0x00000004)*/
/*! Slice: Base address of Gamma LUT for mono sensor, when AHB slave writes/reads this register address continuously, it means it will start to */
/*!   write or read the LUT.*/
#define ISP_GCMONO_PARA_BASE
#define ISP_GCMONO_PARA_BASE_MASK 0xFFFFFFFFU
#define ISP_GCMONO_PARA_BASE_SHIFT 0U
#endif
/*! Register: isp_wdr2_ctrl   (0x00003100)*/
/*! Slice: wdr2_soft_reset_flag:*/
#define  WDR2_SOFT_RESET_FLAG
#define  WDR2_SOFT_RESET_FLAG_MASK 0x00000004U
#define  WDR2_SOFT_RESET_FLAG_SHIFT 2U
/*! Slice: wdr2_mono_input:*/
#define  WDR2_MONO_INPUT
#define  WDR2_MONO_INPUT_MASK 0x00000002U
#define  WDR2_MONO_INPUT_SHIFT 1U
/*! Slice: wdr2_enable:*/
#define  WDR2_ENABLE
#define  WDR2_ENABLE_MASK 0x00000001U
#define  WDR2_ENABLE_SHIFT 0U
/*! Register: isp_wdr2_blk_siz  (0x00003104)*/
/*! Slice: hist_block_width:*/
#define  HIST_BLOCK_WIDTH
#define  HIST_BLOCK_WIDTH_MASK 0x000FFC00U
#define  HIST_BLOCK_WIDTH_SHIFT 10U
/*! Slice: hist_block_height:*/
#define  HIST_BLOCK_HEIGHT
#define  HIST_BLOCK_HEIGHT_MASK 0x000003FFU
#define  HIST_BLOCK_HEIGHT_SHIFT 0U
/*! Register: isp_wdr2_color_weight   (0x00003108)*/
/*! Slice: wdr2_color_weight_2:*/
#define  WDR2_COLOR_WEIGHT_2
#define  WDR2_COLOR_WEIGHT_2_MASK 0x00FF0000U
#define  WDR2_COLOR_WEIGHT_2_SHIFT 16U
/*! Slice: wdr2_color_weight_1:*/
#define  WDR2_COLOR_WEIGHT_1
#define  WDR2_COLOR_WEIGHT_1_MASK 0x0000FF00U
#define  WDR2_COLOR_WEIGHT_1_SHIFT 8U
/*! Slice: wdr2_color_weight_0:*/
#define  WDR2_COLOR_WEIGHT_0
#define  WDR2_COLOR_WEIGHT_0_MASK 0x000000FFU
#define  WDR2_COLOR_WEIGHT_0_SHIFT 0U
/*! Register: isp_wdr2_blt_sigma  (0x0000310C)*/
/*! Slice: wdr2_blt_range_sigma:*/
#define  WDR2_BLT_RANGE_SIGMA
#define  WDR2_BLT_RANGE_SIGMA_MASK 0x000FFC00U
#define  WDR2_BLT_RANGE_SIGMA_SHIFT 10U
/*! Slice: wdr2_blt_spatial_sigma:*/
#define  WDR2_BLT_SPATIAL_SIGMA
#define  WDR2_BLT_SPATIAL_SIGMA_MASK 0x000003FFU
#define  WDR2_BLT_SPATIAL_SIGMA_SHIFT 0U
/*! Register: isp_wdr2_blt_kernel_0  (0x00003110)*/
/*! Slice: wdr2_blt_kernel_c:*/
#define  WDR2_BLT_KERNEL_C
#define  WDR2_BLT_KERNEL_C_MASK 0x00FF0000U
#define  WDR2_BLT_KERNEL_C_SHIFT 16U
/*! Slice: wdr2_blt_kernel_b:*/
#define  WDR2_BLT_KERNEL_B
#define  WDR2_BLT_KERNEL_B_MASK 0x0000FF00U
#define  WDR2_BLT_KERNEL_B_SHIFT 8U
/*! Slice: wdr2_blt_kernel_a:*/
#define  WDR2_BLT_KERNEL_A
#define  WDR2_BLT_KERNEL_A_MASK 0x000000FFU
#define  WDR2_BLT_KERNEL_A_SHIFT 0U
/*! Register: isp_wdr2_blt_kernel_1  (0x00003114)*/
/*! Slice: wdr2_blt_kernel_f:*/
#define  WDR2_BLT_KERNEL_F
#define  WDR2_BLT_KERNEL_F_MASK 0x00FF0000U
#define  WDR2_BLT_KERNEL_F_SHIFT 16U
/*! Slice: wdr2_blt_kernel_e:*/
#define  WDR2_BLT_KERNEL_E
#define  WDR2_BLT_KERNEL_E_MASK 0x0000FF00U
#define  WDR2_BLT_KERNEL_E_SHIFT 8U
/*! Slice: wdr2_blt_kernel_d:*/
#define  WDR2_BLT_KERNEL_D
#define  WDR2_BLT_KERNEL_D_MASK 0x000000FFU
#define  WDR2_BLT_KERNEL_D_SHIFT 0U
/*! Register: isp_wdr2_vol_shift_bit  (0x00003118)*/
/*! Slice: wdr2_vol_shift_bit:*/
#define  WDR2_VOL_SHIFT_BIT
#define  WDR2_VOL_SHIFT_BIT_MASK 0x0000001FU
#define  WDR2_VOL_SHIFT_BIT_SHIFT 0U
/*! Register: isp_wdr2_bin_dist_0  (0x0000311C)*/
/*! Slice: wdr2_bin_dist_1:*/
#define  WDR2_BIN_DIST_1
#define  WDR2_BIN_DIST_1_MASK 0x0FFF0000U
#define  WDR2_BIN_DIST_1_SHIFT 16U
/*! Slice: wdr2_bin_dist_0:*/
#define  WDR2_BIN_DIST_0
#define  WDR2_BIN_DIST_0_MASK 0x00000FFFU
#define  WDR2_BIN_DIST_0_SHIFT 0U
/*! Register: isp_wdr2_bin_dist_1  (0x00003120)*/
/*! Slice: wdr2_bin_dist_3:*/
#define  WDR2_BIN_DIST_3
#define  WDR2_BIN_DIST_3_MASK 0x0FFF0000U
#define  WDR2_BIN_DIST_3_SHIFT 16U
/*! Slice: wdr2_bin_dist_2:*/
#define  WDR2_BIN_DIST_2
#define  WDR2_BIN_DIST_2_MASK 0x00000FFFU
#define  WDR2_BIN_DIST_2_SHIFT 0U
/*! Register: isp_wdr2_bin_dist_2  (0x00003124)*/
/*! Slice: wdr2_bin_dist_5:*/
#define  WDR2_BIN_DIST_5
#define  WDR2_BIN_DIST_5_MASK 0x0FFF0000U
#define  WDR2_BIN_DIST_5_SHIFT 16U
/*! Slice: wdr2_bin_dist_4:*/
#define  WDR2_BIN_DIST_4
#define  WDR2_BIN_DIST_4_MASK 0x00000FFFU
#define  WDR2_BIN_DIST_4_SHIFT 0U
/*! Register: isp_wdr2_bin_dist_3  (0x00003128)*/
/*! Slice: wdr2_bin_dist_7:*/
#define  WDR2_BIN_DIST_7
#define  WDR2_BIN_DIST_7_MASK 0x0FFF0000U
#define  WDR2_BIN_DIST_7_SHIFT 16U
/*! Slice: wdr2_bin_dist_6:*/
#define  WDR2_BIN_DIST_6
#define  WDR2_BIN_DIST_6_MASK 0x00000FFFU
#define  WDR2_BIN_DIST_6_SHIFT 0U
/*! Register: isp_wdr2_hist_norm_fac  (0x0000312C)*/
/*! Slice: wdr2_hist_norm_shift_bit:*/
#define  WDR2_HIST_NORM_SHIFT_BIT
#define  WDR2_HIST_NORM_SHIFT_BIT_MASK 0x0FFF0000U
#define  WDR2_HIST_NORM_SHIFT_BIT_SHIFT 16U
/*! Slice: wdr2_hist_norm_mul:*/
#define  WDR2_HIST_NORM_MUL
#define  WDR2_HIST_NORM_MUL_MASK 0x00000FFFU
#define  WDR2_HIST_NORM_MUL_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_lut  (0x00003138)*/
/*! Slice: wdr2_pre_gamma_lut:*/
#define  WDR2_PRE_GAMMA_LUT
#define  WDR2_PRE_GAMMA_LUT_MASK 0xFFFFFFFFU
#define  WDR2_PRE_GAMMA_LUT_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_write_data  (0x0000313C)*/
/*! Slice: wdr2_pre_gamma_write_data:*/
#define  WDR2_PRE_GAMMA_WRITE_DATA
#define  WDR2_PRE_GAMMA_WRITE_DATA_MASK 0x00000FFFU
#define  WDR2_PRE_GAMMA_WRITE_DATA_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_lut  (0x00003140)*/
/*! Slice: wdr2_tone_curve_lut:*/
#define  WDR2_TONE_CURVE_LUT
#define  WDR2_TONE_CURVE_LUT_MASK 0xFFFFFFFFU
#define  WDR2_TONE_CURVE_LUT_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_write_data  (0x00003144)*/
/*! Slice: wdr2_tone_curve_write_data:*/
#define  WDR2_TONE_CURVE_WRITE_DATA
#define  WDR2_TONE_CURVE_WRITE_DATA_MASK 0x00000FFFU
#define  WDR2_TONE_CURVE_WRITE_DATA_SHIFT 0U
/*! Register: isp_wdr2_merge_coeff_lut  (0x00003148)*/
/*! Slice: wdr2_merge_coeff_lut:*/
#define  WDR2_MERGE_COEFF_LUT
#define  WDR2_MERGE_COEFF_LUT_MASK 0xFFFFFFFFU
#define  WDR2_MERGE_COEFF_LUT_SHIFT 0U
/*! Register: isp_wdr2_merge_coeff_write_data  (0x0000314C)*/
/*! Slice: wdr2_merge_coeff_write_data:*/
#define  WDR2_MERGE_COEFF_WRITE_DATA
#define  WDR2_MERGE_COEFF_WRITE_DATA_MASK 0x000000FFU
#define  WDR2_MERGE_COEFF_WRITE_DATA_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_0  (0x00003150)*/
/*! Slice: wdr2_pre_gamma_cx_5:*/
#define  WDR2_PRE_GAMMA_CX_5
#define  WDR2_PRE_GAMMA_CX_5_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_5_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_4:*/
#define  WDR2_PRE_GAMMA_CX_4
#define  WDR2_PRE_GAMMA_CX_4_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_4_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_3:*/
#define  WDR2_PRE_GAMMA_CX_3
#define  WDR2_PRE_GAMMA_CX_3_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_3_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_2:*/
#define  WDR2_PRE_GAMMA_CX_2
#define  WDR2_PRE_GAMMA_CX_2_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_2_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_1:*/
#define  WDR2_PRE_GAMMA_CX_1
#define  WDR2_PRE_GAMMA_CX_1_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_1_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_0:*/
#define  WDR2_PRE_GAMMA_CX_0
#define  WDR2_PRE_GAMMA_CX_0_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_0_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_1  (0x00003154)*/
/*! Slice: wdr2_pre_gamma_cx_11:*/
#define  WDR2_PRE_GAMMA_CX_11
#define  WDR2_PRE_GAMMA_CX_11_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_11_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_10:*/
#define  WDR2_PRE_GAMMA_CX_10
#define  WDR2_PRE_GAMMA_CX_10_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_10_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_9:*/
#define  WDR2_PRE_GAMMA_CX_9
#define  WDR2_PRE_GAMMA_CX_9_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_9_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_8:*/
#define  WDR2_PRE_GAMMA_CX_8
#define  WDR2_PRE_GAMMA_CX_8_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_8_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_7:*/
#define  WDR2_PRE_GAMMA_CX_7
#define  WDR2_PRE_GAMMA_CX_7_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_7_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_6:*/
#define  WDR2_PRE_GAMMA_CX_6
#define  WDR2_PRE_GAMMA_CX_6_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_6_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_2  (0x00003158)*/
/*! Slice: wdr2_pre_gamma_cx_17:*/
#define  WDR2_PRE_GAMMA_CX_17
#define  WDR2_PRE_GAMMA_CX_17_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_17_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_16:*/
#define  WDR2_PRE_GAMMA_CX_16
#define  WDR2_PRE_GAMMA_CX_16_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_16_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_15:*/
#define  WDR2_PRE_GAMMA_CX_15
#define  WDR2_PRE_GAMMA_CX_15_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_15_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_14:*/
#define  WDR2_PRE_GAMMA_CX_14
#define  WDR2_PRE_GAMMA_CX_14_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_14_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_13:*/
#define  WDR2_PRE_GAMMA_CX_13
#define  WDR2_PRE_GAMMA_CX_13_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_13_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_12:*/
#define  WDR2_PRE_GAMMA_CX_12
#define  WDR2_PRE_GAMMA_CX_12_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_12_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_3  (0x0000315C)*/
/*! Slice: wdr2_pre_gamma_cx_23:*/
#define  WDR2_PRE_GAMMA_CX_23
#define  WDR2_PRE_GAMMA_CX_23_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_23_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_22:*/
#define  WDR2_PRE_GAMMA_CX_22
#define  WDR2_PRE_GAMMA_CX_22_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_22_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_21:*/
#define  WDR2_PRE_GAMMA_CX_21
#define  WDR2_PRE_GAMMA_CX_21_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_21_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_20:*/
#define  WDR2_PRE_GAMMA_CX_20
#define  WDR2_PRE_GAMMA_CX_20_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_20_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_19:*/
#define  WDR2_PRE_GAMMA_CX_19
#define  WDR2_PRE_GAMMA_CX_19_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_19_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_18:*/
#define  WDR2_PRE_GAMMA_CX_18
#define  WDR2_PRE_GAMMA_CX_18_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_18_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_4  (0x00003160)*/
/*! Slice: wdr2_pre_gamma_cx_29:*/
#define  WDR2_PRE_GAMMA_CX_29
#define  WDR2_PRE_GAMMA_CX_29_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_29_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_28:*/
#define  WDR2_PRE_GAMMA_CX_28
#define  WDR2_PRE_GAMMA_CX_28_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_28_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_27:*/
#define  WDR2_PRE_GAMMA_CX_27
#define  WDR2_PRE_GAMMA_CX_27_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_27_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_26:*/
#define  WDR2_PRE_GAMMA_CX_26
#define  WDR2_PRE_GAMMA_CX_26_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_26_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_25:*/
#define  WDR2_PRE_GAMMA_CX_25
#define  WDR2_PRE_GAMMA_CX_25_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_25_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_24:*/
#define  WDR2_PRE_GAMMA_CX_24
#define  WDR2_PRE_GAMMA_CX_24_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_24_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_5  (0x00003164)*/
/*! Slice: wdr2_pre_gamma_cx_35:*/
#define  WDR2_PRE_GAMMA_CX_35
#define  WDR2_PRE_GAMMA_CX_35_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_35_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_34:*/
#define  WDR2_PRE_GAMMA_CX_34
#define  WDR2_PRE_GAMMA_CX_34_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_34_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_33:*/
#define  WDR2_PRE_GAMMA_CX_33
#define  WDR2_PRE_GAMMA_CX_33_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_33_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_32:*/
#define  WDR2_PRE_GAMMA_CX_32
#define  WDR2_PRE_GAMMA_CX_32_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_32_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_31:*/
#define  WDR2_PRE_GAMMA_CX_31
#define  WDR2_PRE_GAMMA_CX_31_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_31_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_30:*/
#define  WDR2_PRE_GAMMA_CX_30
#define  WDR2_PRE_GAMMA_CX_30_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_30_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_6  (0x00003168)*/
/*! Slice: wdr2_pre_gamma_cx_41:*/
#define  WDR2_PRE_GAMMA_CX_41
#define  WDR2_PRE_GAMMA_CX_41_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_41_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_40:*/
#define  WDR2_PRE_GAMMA_CX_40
#define  WDR2_PRE_GAMMA_CX_40_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_40_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_39:*/
#define  WDR2_PRE_GAMMA_CX_39
#define  WDR2_PRE_GAMMA_CX_39_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_39_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_38:*/
#define  WDR2_PRE_GAMMA_CX_38
#define  WDR2_PRE_GAMMA_CX_38_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_38_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_37:*/
#define  WDR2_PRE_GAMMA_CX_37
#define  WDR2_PRE_GAMMA_CX_37_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_37_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_36:*/
#define  WDR2_PRE_GAMMA_CX_36
#define  WDR2_PRE_GAMMA_CX_36_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_36_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_7  (0x0000316C)*/
/*! Slice: wdr2_pre_gamma_cx_47:*/
#define  WDR2_PRE_GAMMA_CX_47
#define  WDR2_PRE_GAMMA_CX_47_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_47_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_46:*/
#define  WDR2_PRE_GAMMA_CX_46
#define  WDR2_PRE_GAMMA_CX_46_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_46_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_45:*/
#define  WDR2_PRE_GAMMA_CX_45
#define  WDR2_PRE_GAMMA_CX_45_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_45_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_44:*/
#define  WDR2_PRE_GAMMA_CX_44
#define  WDR2_PRE_GAMMA_CX_44_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_44_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_43:*/
#define  WDR2_PRE_GAMMA_CX_43
#define  WDR2_PRE_GAMMA_CX_43_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_43_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_42:*/
#define  WDR2_PRE_GAMMA_CX_42
#define  WDR2_PRE_GAMMA_CX_42_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_42_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_8  (0x00003170)*/
/*! Slice: wdr2_pre_gamma_cx_53:*/
#define  WDR2_PRE_GAMMA_CX_53
#define  WDR2_PRE_GAMMA_CX_53_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_53_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_52:*/
#define  WDR2_PRE_GAMMA_CX_52
#define  WDR2_PRE_GAMMA_CX_52_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_52_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_51:*/
#define  WDR2_PRE_GAMMA_CX_51
#define  WDR2_PRE_GAMMA_CX_51_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_51_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_50:*/
#define  WDR2_PRE_GAMMA_CX_50
#define  WDR2_PRE_GAMMA_CX_50_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_50_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_49:*/
#define  WDR2_PRE_GAMMA_CX_49
#define  WDR2_PRE_GAMMA_CX_49_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_49_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_48:*/
#define  WDR2_PRE_GAMMA_CX_48
#define  WDR2_PRE_GAMMA_CX_48_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_48_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_9  (0x00003174)*/
/*! Slice: wdr2_pre_gamma_cx_59:*/
#define  WDR2_PRE_GAMMA_CX_59
#define  WDR2_PRE_GAMMA_CX_59_MASK 0x3E000000U
#define  WDR2_PRE_GAMMA_CX_59_SHIFT 25U
/*! Slice: wdr2_pre_gamma_cx_58:*/
#define  WDR2_PRE_GAMMA_CX_58
#define  WDR2_PRE_GAMMA_CX_58_MASK 0x01F00000U
#define  WDR2_PRE_GAMMA_CX_58_SHIFT 20U
/*! Slice: wdr2_pre_gamma_cx_57:*/
#define  WDR2_PRE_GAMMA_CX_57
#define  WDR2_PRE_GAMMA_CX_57_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_57_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_56:*/
#define  WDR2_PRE_GAMMA_CX_56
#define  WDR2_PRE_GAMMA_CX_56_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_56_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_55:*/
#define  WDR2_PRE_GAMMA_CX_55
#define  WDR2_PRE_GAMMA_CX_55_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_55_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_54:*/
#define  WDR2_PRE_GAMMA_CX_54
#define  WDR2_PRE_GAMMA_CX_54_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_54_SHIFT 0U
/*! Register: isp_wdr2_pre_gamma_cx_10  (0x00003178)*/
/*! Slice: wdr2_pre_gamma_cx_63:*/
#define  WDR2_PRE_GAMMA_CX_63
#define  WDR2_PRE_GAMMA_CX_63_MASK 0x000F8000U
#define  WDR2_PRE_GAMMA_CX_63_SHIFT 15U
/*! Slice: wdr2_pre_gamma_cx_62:*/
#define  WDR2_PRE_GAMMA_CX_62
#define  WDR2_PRE_GAMMA_CX_62_MASK 0x00007C00U
#define  WDR2_PRE_GAMMA_CX_62_SHIFT 10U
/*! Slice: wdr2_pre_gamma_cx_61:*/
#define  WDR2_PRE_GAMMA_CX_61
#define  WDR2_PRE_GAMMA_CX_61_MASK 0x000003E0U
#define  WDR2_PRE_GAMMA_CX_61_SHIFT 5U
/*! Slice: wdr2_pre_gamma_cx_60:*/
#define  WDR2_PRE_GAMMA_CX_60
#define  WDR2_PRE_GAMMA_CX_60_MASK 0x0000001FU
#define  WDR2_PRE_GAMMA_CX_60_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_cx_0  (0x0000317C)*/
/*! Slice: wdr2_tone_curve_cx_7:*/
#define  WDR2_TONE_CURVE_CX_7
#define  WDR2_TONE_CURVE_CX_7_MASK 0xF0000000U
#define  WDR2_TONE_CURVE_CX_7_SHIFT 28U
/*! Slice: wdr2_tone_curve_cx_6:*/
#define  WDR2_TONE_CURVE_CX_6
#define  WDR2_TONE_CURVE_CX_6_MASK 0x0F000000U
#define  WDR2_TONE_CURVE_CX_6_SHIFT 24U
/*! Slice: wdr2_tone_curve_cx_5:*/
#define  WDR2_TONE_CURVE_CX_5
#define  WDR2_TONE_CURVE_CX_5_MASK 0x00F00000U
#define  WDR2_TONE_CURVE_CX_5_SHIFT 20U
/*! Slice: wdr2_tone_curve_cx_4:*/
#define  WDR2_TONE_CURVE_CX_4
#define  WDR2_TONE_CURVE_CX_4_MASK 0x000F0000U
#define  WDR2_TONE_CURVE_CX_4_SHIFT 16U
/*! Slice: wdr2_tone_curve_cx_3:*/
#define  WDR2_TONE_CURVE_CX_3
#define  WDR2_TONE_CURVE_CX_3_MASK 0x0000F000U
#define  WDR2_TONE_CURVE_CX_3_SHIFT 12U
/*! Slice: wdr2_tone_curve_cx_2:*/
#define  WDR2_TONE_CURVE_CX_2
#define  WDR2_TONE_CURVE_CX_2_MASK 0x00000F00U
#define  WDR2_TONE_CURVE_CX_2_SHIFT 8U
/*! Slice: wdr2_tone_curve_cx_1:*/
#define  WDR2_TONE_CURVE_CX_1
#define  WDR2_TONE_CURVE_CX_1_MASK 0x000000F0U
#define  WDR2_TONE_CURVE_CX_1_SHIFT 4U
/*! Slice: wdr2_tone_curve_cx_0:*/
#define  WDR2_TONE_CURVE_CX_0
#define  WDR2_TONE_CURVE_CX_0_MASK 0x0000000FU
#define  WDR2_TONE_CURVE_CX_0_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_cx_1  (0x00003180)*/
/*! Slice: wdr2_tone_curve_cx_15:*/
#define  WDR2_TONE_CURVE_CX_15
#define  WDR2_TONE_CURVE_CX_15_MASK 0xF0000000U
#define  WDR2_TONE_CURVE_CX_15_SHIFT 28U
/*! Slice: wdr2_tone_curve_cx_14:*/
#define  WDR2_TONE_CURVE_CX_14
#define  WDR2_TONE_CURVE_CX_14_MASK 0x0F000000U
#define  WDR2_TONE_CURVE_CX_14_SHIFT 24U
/*! Slice: wdr2_tone_curve_cx_13:*/
#define  WDR2_TONE_CURVE_CX_13
#define  WDR2_TONE_CURVE_CX_13_MASK 0x00F00000U
#define  WDR2_TONE_CURVE_CX_13_SHIFT 20U
/*! Slice: wdr2_tone_curve_cx_12:*/
#define  WDR2_TONE_CURVE_CX_12
#define  WDR2_TONE_CURVE_CX_12_MASK 0x000F0000U
#define  WDR2_TONE_CURVE_CX_12_SHIFT 16U
/*! Slice: wdr2_tone_curve_cx_11:*/
#define  WDR2_TONE_CURVE_CX_11
#define  WDR2_TONE_CURVE_CX_11_MASK 0x0000F000U
#define  WDR2_TONE_CURVE_CX_11_SHIFT 12U
/*! Slice: wdr2_tone_curve_cx_10:*/
#define  WDR2_TONE_CURVE_CX_10
#define  WDR2_TONE_CURVE_CX_10_MASK 0x00000F00U
#define  WDR2_TONE_CURVE_CX_10_SHIFT 8U
/*! Slice: wdr2_tone_curve_cx_9:*/
#define  WDR2_TONE_CURVE_CX_9
#define  WDR2_TONE_CURVE_CX_9_MASK 0x000000F0U
#define  WDR2_TONE_CURVE_CX_9_SHIFT 4U
/*! Slice: wdr2_tone_curve_cx_8:*/
#define  WDR2_TONE_CURVE_CX_8
#define  WDR2_TONE_CURVE_CX_8_MASK 0x0000000FU
#define  WDR2_TONE_CURVE_CX_8_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_cx_2  (0x00003184)*/
/*! Slice: wdr2_tone_curve_cx_23:*/
#define  WDR2_TONE_CURVE_CX_23
#define  WDR2_TONE_CURVE_CX_23_MASK 0xF0000000U
#define  WDR2_TONE_CURVE_CX_23_SHIFT 28U
/*! Slice: wdr2_tone_curve_cx_22:*/
#define  WDR2_TONE_CURVE_CX_22
#define  WDR2_TONE_CURVE_CX_22_MASK 0x0F000000U
#define  WDR2_TONE_CURVE_CX_22_SHIFT 24U
/*! Slice: wdr2_tone_curve_cx_21:*/
#define  WDR2_TONE_CURVE_CX_21
#define  WDR2_TONE_CURVE_CX_21_MASK 0x00F00000U
#define  WDR2_TONE_CURVE_CX_21_SHIFT 20U
/*! Slice: wdr2_tone_curve_cx_20:*/
#define  WDR2_TONE_CURVE_CX_20
#define  WDR2_TONE_CURVE_CX_20_MASK 0x000F0000U
#define  WDR2_TONE_CURVE_CX_20_SHIFT 16U
/*! Slice: wdr2_tone_curve_cx_19:*/
#define  WDR2_TONE_CURVE_CX_19
#define  WDR2_TONE_CURVE_CX_19_MASK 0x0000F000U
#define  WDR2_TONE_CURVE_CX_19_SHIFT 12U
/*! Slice: wdr2_tone_curve_cx_18:*/
#define  WDR2_TONE_CURVE_CX_18
#define  WDR2_TONE_CURVE_CX_18_MASK 0x00000F00U
#define  WDR2_TONE_CURVE_CX_18_SHIFT 8U
/*! Slice: wdr2_tone_curve_cx_17:*/
#define  WDR2_TONE_CURVE_CX_17
#define  WDR2_TONE_CURVE_CX_17_MASK 0x000000F0U
#define  WDR2_TONE_CURVE_CX_17_SHIFT 4U
/*! Slice: wdr2_tone_curve_cx_16:*/
#define  WDR2_TONE_CURVE_CX_16
#define  WDR2_TONE_CURVE_CX_16_MASK 0x0000000FU
#define  WDR2_TONE_CURVE_CX_16_SHIFT 0U
/*! Register: isp_wdr2_tone_curve_cx_3  (0x00003188)*/
/*! Slice: wdr2_tone_curve_cx_31:*/
#define  WDR2_TONE_CURVE_CX_31
#define  WDR2_TONE_CURVE_CX_31_MASK 0xF0000000U
#define  WDR2_TONE_CURVE_CX_31_SHIFT 28U
/*! Slice: wdr2_tone_curve_cx_30:*/
#define  WDR2_TONE_CURVE_CX_30
#define  WDR2_TONE_CURVE_CX_30_MASK 0x0F000000U
#define  WDR2_TONE_CURVE_CX_30_SHIFT 24U
/*! Slice: wdr2_tone_curve_cx_29:*/
#define  WDR2_TONE_CURVE_CX_29
#define  WDR2_TONE_CURVE_CX_29_MASK 0x00F00000U
#define  WDR2_TONE_CURVE_CX_29_SHIFT 20U
/*! Slice: wdr2_tone_curve_cx_28:*/
#define  WDR2_TONE_CURVE_CX_28
#define  WDR2_TONE_CURVE_CX_28_MASK 0x000F0000U
#define  WDR2_TONE_CURVE_CX_28_SHIFT 16U
/*! Slice: wdr2_tone_curve_cx_27:*/
#define  WDR2_TONE_CURVE_CX_27
#define  WDR2_TONE_CURVE_CX_27_MASK 0x0000F000U
#define  WDR2_TONE_CURVE_CX_27_SHIFT 12U
/*! Slice: wdr2_tone_curve_cx_26:*/
#define  WDR2_TONE_CURVE_CX_26
#define  WDR2_TONE_CURVE_CX_26_MASK 0x00000F00U
#define  WDR2_TONE_CURVE_CX_26_SHIFT 8U
/*! Slice: wdr2_tone_curve_cx_25:*/
#define  WDR2_TONE_CURVE_CX_25
#define  WDR2_TONE_CURVE_CX_25_MASK 0x000000F0U
#define  WDR2_TONE_CURVE_CX_25_SHIFT 4U
/*! Slice: wdr2_tone_curve_cx_24:*/
#define  WDR2_TONE_CURVE_CX_24
#define  WDR2_TONE_CURVE_CX_24_MASK 0x0000000FU
#define  WDR2_TONE_CURVE_CX_24_SHIFT 0U
/*! Register: isp_wdr2_merge_coeff_cx_0  (0x0000318C)*/
/*! Slice: wdr2_merge_coeff_cx_7:*/
#define  WDR2_MERGE_COEFF_CX_7
#define  WDR2_MERGE_COEFF_CX_7_MASK 0xF0000000U
#define  WDR2_MERGE_COEFF_CX_7_SHIFT 28U
/*! Slice: wdr2_merge_coeff_cx_6:*/
#define  WDR2_MERGE_COEFF_CX_6
#define  WDR2_MERGE_COEFF_CX_6_MASK 0x0F000000U
#define  WDR2_MERGE_COEFF_CX_6_SHIFT 24U
/*! Slice: wdr2_merge_coeff_cx_5:*/
#define  WDR2_MERGE_COEFF_CX_5
#define  WDR2_MERGE_COEFF_CX_5_MASK 0x00F00000U
#define  WDR2_MERGE_COEFF_CX_5_SHIFT 20U
/*! Slice: wdr2_merge_coeff_cx_4:*/
#define  WDR2_MERGE_COEFF_CX_4
#define  WDR2_MERGE_COEFF_CX_4_MASK 0x000F0000U
#define  WDR2_MERGE_COEFF_CX_4_SHIFT 16U
/*! Slice: wdr2_merge_coeff_cx_3:*/
#define  WDR2_MERGE_COEFF_CX_3
#define  WDR2_MERGE_COEFF_CX_3_MASK 0x0000F000U
#define  WDR2_MERGE_COEFF_CX_3_SHIFT 12U
/*! Slice: wdr2_merge_coeff_cx_2:*/
#define  WDR2_MERGE_COEFF_CX_2
#define  WDR2_MERGE_COEFF_CX_2_MASK 0x00000F00U
#define  WDR2_MERGE_COEFF_CX_2_SHIFT 8U
/*! Slice: wdr2_merge_coeff_cx_1:*/
#define  WDR2_MERGE_COEFF_CX_1
#define  WDR2_MERGE_COEFF_CX_1_MASK 0x000000F0U
#define  WDR2_MERGE_COEFF_CX_1_SHIFT 4U
/*! Slice: wdr2_merge_coeff_cx_0:*/
#define  WDR2_MERGE_COEFF_CX_0
#define  WDR2_MERGE_COEFF_CX_0_MASK 0x0000000FU
#define  WDR2_MERGE_COEFF_CX_0_SHIFT 0U
/*! Register: isp_wdr2_merge_coeff_cx_1  (0x00003190)*/
/*! Slice: wdr2_merge_coeff_cx_15:*/
#define  WDR2_MERGE_COEFF_CX_15
#define  WDR2_MERGE_COEFF_CX_15_MASK 0xF0000000U
#define  WDR2_MERGE_COEFF_CX_15_SHIFT 28U
/*! Slice: wdr2_merge_coeff_cx_14:*/
#define  WDR2_MERGE_COEFF_CX_14
#define  WDR2_MERGE_COEFF_CX_14_MASK 0x0F000000U
#define  WDR2_MERGE_COEFF_CX_14_SHIFT 24U
/*! Slice: wdr2_merge_coeff_cx_13:*/
#define  WDR2_MERGE_COEFF_CX_13
#define  WDR2_MERGE_COEFF_CX_13_MASK 0x00F00000U
#define  WDR2_MERGE_COEFF_CX_13_SHIFT 20U
/*! Slice: wdr2_merge_coeff_cx_12:*/
#define  WDR2_MERGE_COEFF_CX_12
#define  WDR2_MERGE_COEFF_CX_12_MASK 0x000F0000U
#define  WDR2_MERGE_COEFF_CX_12_SHIFT 16U
/*! Slice: wdr2_merge_coeff_cx_11:*/
#define  WDR2_MERGE_COEFF_CX_11
#define  WDR2_MERGE_COEFF_CX_11_MASK 0x0000F000U
#define  WDR2_MERGE_COEFF_CX_11_SHIFT 12U
/*! Slice: wdr2_merge_coeff_cx_10:*/
#define  WDR2_MERGE_COEFF_CX_10
#define  WDR2_MERGE_COEFF_CX_10_MASK 0x00000F00U
#define  WDR2_MERGE_COEFF_CX_10_SHIFT 8U
/*! Slice: wdr2_merge_coeff_cx_9:*/
#define  WDR2_MERGE_COEFF_CX_9
#define  WDR2_MERGE_COEFF_CX_9_MASK 0x000000F0U
#define  WDR2_MERGE_COEFF_CX_9_SHIFT 4U
/*! Slice: wdr2_merge_coeff_cx_8:*/
#define  WDR2_MERGE_COEFF_CX_8
#define  WDR2_MERGE_COEFF_CX_8_MASK 0x0000000FU
#define  WDR2_MERGE_COEFF_CX_8_SHIFT 0U
/*! Register: isp_wdr2_max_gain_cx  (0x000031A8)*/
/*! Slice: wdr2_max_gain_cx_4:*/
#define  WDR2_MAX_GAIN_CX_4
#define  WDR2_MAX_GAIN_CX_4_MASK 0xFF000000U
#define  WDR2_MAX_GAIN_CX_4_SHIFT 24U
/*! Slice: wdr2_max_gain_cx_3:*/
#define  WDR2_MAX_GAIN_CX_3
#define  WDR2_MAX_GAIN_CX_3_MASK 0x00FF0000U
#define  WDR2_MAX_GAIN_CX_3_SHIFT 16U
/*! Slice: wdr2_max_gain_cx_2:*/
#define  WDR2_MAX_GAIN_CX_2
#define  WDR2_MAX_GAIN_CX_2_MASK 0x0000FF00U
#define  WDR2_MAX_GAIN_CX_2_SHIFT 8U
/*! Slice: wdr2_max_gain_cx_1:*/
#define  WDR2_MAX_GAIN_CX_1
#define  WDR2_MAX_GAIN_CX_1_MASK 0x000000FFU
#define  WDR2_MAX_GAIN_CX_1_SHIFT 0U
/*! Register: isp_wdr2_max_gain_slope_0  (0x000031AC)*/
/*! Slice: wdr2_max_gain_slope_1:*/
#define  WDR2_MAX_GAIN_SLOPE_1
#define  WDR2_MAX_GAIN_SLOPE_1_MASK 0x0FFF0000U
#define  WDR2_MAX_GAIN_SLOPE_1_SHIFT 16U
/*! Slice: wdr2_max_gain_slope_0:*/
#define  WDR2_MAX_GAIN_SLOPE_0
#define  WDR2_MAX_GAIN_SLOPE_0_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_SLOPE_0_SHIFT 0U
/*! Register: isp_wdr2_max_gain_slope_1  (0x000031B0)*/
/*! Slice: wdr2_max_gain_slope_3:*/
#define  WDR2_MAX_GAIN_SLOPE_3
#define  WDR2_MAX_GAIN_SLOPE_3_MASK 0x0FFF0000U
#define  WDR2_MAX_GAIN_SLOPE_3_SHIFT 16U
/*! Slice: wdr2_max_gain_slope_2:*/
#define  WDR2_MAX_GAIN_SLOPE_2
#define  WDR2_MAX_GAIN_SLOPE_2_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_SLOPE_2_SHIFT 0U
/*! Register: isp_wdr2_max_gain_slope_2  (0x000031B4)*/
/*! Slice: wdr2_max_gain_slope_4:*/
#define  WDR2_MAX_GAIN_SLOPE_4
#define  WDR2_MAX_GAIN_SLOPE_4_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_SLOPE_4_SHIFT 0U
/*! Register: isp_wdr2_max_gain_cy_0  (0x000031B8)*/
/*! Slice: wdr2_max_gain_cy_1:*/
#define  WDR2_MAX_GAIN_CY_1
#define  WDR2_MAX_GAIN_CY_1_MASK 0x0FFF0000U
#define  WDR2_MAX_GAIN_CY_1_SHIFT 16U
/*! Slice: wdr2_max_gain_cy_0:*/
#define  WDR2_MAX_GAIN_CY_0
#define  WDR2_MAX_GAIN_CY_0_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_CY_0_SHIFT 0U
/*! Register: isp_wdr2_max_gain_cy_1  (0x000031BC)*/
/*! Slice: wdr2_max_gain_cy_3:*/
#define  WDR2_MAX_GAIN_CY_3
#define  WDR2_MAX_GAIN_CY_3_MASK 0x0FFF0000U
#define  WDR2_MAX_GAIN_CY_3_SHIFT 16U
/*! Slice: wdr2_max_gain_cy_2:*/
#define  WDR2_MAX_GAIN_CY_2
#define  WDR2_MAX_GAIN_CY_2_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_CY_2_SHIFT 0U
/*! Register: isp_wdr2_max_gain_cy_2  (0x000031C0)*/
/*! Slice: wdr2_max_gain_cy_5:*/
#define  WDR2_MAX_GAIN_CY_5
#define  WDR2_MAX_GAIN_CY_5_MASK 0x0FFF0000U
#define  WDR2_MAX_GAIN_CY_5_SHIFT 16U
/*! Slice: wdr2_max_gain_cy_4:*/
#define  WDR2_MAX_GAIN_CY_4
#define  WDR2_MAX_GAIN_CY_4_MASK 0x00000FFFU
#define  WDR2_MAX_GAIN_CY_4_SHIFT 0U
/*! Register: isp_wdr2_norm_factor_mul_0  (0x000031C4)*/
/*! Slice: wdr2_norm_factor_mul_3:*/
#define  WDR2_NORM_FACTOR_MUL_3
#define  WDR2_NORM_FACTOR_MUL_3_MASK 0xFF000000U
#define  WDR2_NORM_FACTOR_MUL_3_SHIFT 24U
/*! Slice: wdr2_norm_factor_mul_2:*/
#define  WDR2_NORM_FACTOR_MUL_2
#define  WDR2_NORM_FACTOR_MUL_2_MASK 0x00FF0000U
#define  WDR2_NORM_FACTOR_MUL_2_SHIFT 16U
/*! Slice: wdr2_norm_factor_mul_1:*/
#define  WDR2_NORM_FACTOR_MUL_1
#define  WDR2_NORM_FACTOR_MUL_1_MASK 0x0000FF00U
#define  WDR2_NORM_FACTOR_MUL_1_SHIFT 8U
/*! Slice: wdr2_norm_factor_mul_0:*/
#define  WDR2_NORM_FACTOR_MUL_0
#define  WDR2_NORM_FACTOR_MUL_0_MASK 0x000000FFU
#define  WDR2_NORM_FACTOR_MUL_0_SHIFT 0U
/*! Register: isp_wdr2_norm_factor_mul_1  (0x000031C8)*/
/*! Slice: wdr2_norm_factor_mul_7:*/
#define  WDR2_NORM_FACTOR_MUL_7
#define  WDR2_NORM_FACTOR_MUL_7_MASK 0xFF000000U
#define  WDR2_NORM_FACTOR_MUL_7_SHIFT 24U
/*! Slice: wdr2_norm_factor_mul_6:*/
#define  WDR2_NORM_FACTOR_MUL_6
#define  WDR2_NORM_FACTOR_MUL_6_MASK 0x00FF0000U
#define  WDR2_NORM_FACTOR_MUL_6_SHIFT 16U
/*! Slice: wdr2_norm_factor_mul_5:*/
#define  WDR2_NORM_FACTOR_MUL_5
#define  WDR2_NORM_FACTOR_MUL_5_MASK 0x0000FF00U
#define  WDR2_NORM_FACTOR_MUL_5_SHIFT 8U
/*! Slice: wdr2_norm_factor_mul_4:*/
#define  WDR2_NORM_FACTOR_MUL_4
#define  WDR2_NORM_FACTOR_MUL_4_MASK 0x000000FFU
#define  WDR2_NORM_FACTOR_MUL_4_SHIFT 0U
/*! Register: isp_wdr2_norm_factor_shift_bit_0  (0x000031CC)*/
/*! Slice: wdr2_norm_factor_shift_bit_3:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_3
#define  WDR2_NORM_FACTOR_SHIFT_BIT_3_MASK 0xFF000000U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_3_SHIFT 24U
/*! Slice: wdr2_norm_factor_shift_bit_2:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_2
#define  WDR2_NORM_FACTOR_SHIFT_BIT_2_MASK 0x00FF0000U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_2_SHIFT 16U
/*! Slice: wdr2_norm_factor_shift_bit_1:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_1
#define  WDR2_NORM_FACTOR_SHIFT_BIT_1_MASK 0x0000FF00U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_1_SHIFT 8U
/*! Slice: wdr2_norm_factor_shift_bit_0:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_0
#define  WDR2_NORM_FACTOR_SHIFT_BIT_0_MASK 0x000000FFU
#define  WDR2_NORM_FACTOR_SHIFT_BIT_0_SHIFT 0U
/*! Register: isp_wdr2_norm_factor_shift_bit_1  (0x000031D0)*/
/*! Slice: wdr2_norm_factor_shift_bit_7:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_7
#define  WDR2_NORM_FACTOR_SHIFT_BIT_7_MASK 0xFF000000U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_7_SHIFT 24U
/*! Slice: wdr2_norm_factor_shift_bit_6:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_6
#define  WDR2_NORM_FACTOR_SHIFT_BIT_6_MASK 0x00FF0000U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_6_SHIFT 16U
/*! Slice: wdr2_norm_factor_shift_bit_5:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_5
#define  WDR2_NORM_FACTOR_SHIFT_BIT_5_MASK 0x0000FF00U
#define  WDR2_NORM_FACTOR_SHIFT_BIT_5_SHIFT 8U
/*! Slice: wdr2_norm_factor_shift_bit_4:*/
#define  WDR2_NORM_FACTOR_SHIFT_BIT_4
#define  WDR2_NORM_FACTOR_SHIFT_BIT_4_MASK 0x000000FFU
#define  WDR2_NORM_FACTOR_SHIFT_BIT_4_SHIFT 0U
/*! Register: isp_wdr2_bin_range_0  (0x000031D4)*/
/*! Slice: wdr2_bin_range_2:*/
#define  WDR2_BIN_RANGE_2
#define  WDR2_BIN_RANGE_2_MASK 0x0FFF0000U
#define  WDR2_BIN_RANGE_2_SHIFT 16U
/*! Slice: wdr2_bin_range_1:*/
#define  WDR2_BIN_RANGE_1
#define  WDR2_BIN_RANGE_1_MASK 0x00000FFFU
#define  WDR2_BIN_RANGE_1_SHIFT 0U
/*! Register: isp_wdr2_bin_range_1  (0x000031D8)*/
/*! Slice: wdr2_bin_range_4:*/
#define  WDR2_BIN_RANGE_4
#define  WDR2_BIN_RANGE_4_MASK 0x0FFF0000U
#define  WDR2_BIN_RANGE_4_SHIFT 16U
/*! Slice: wdr2_bin_range_3:*/
#define  WDR2_BIN_RANGE_3
#define  WDR2_BIN_RANGE_3_MASK 0x00000FFFU
#define  WDR2_BIN_RANGE_3_SHIFT 0U
/*! Register: isp_wdr2_bin_range_2  (0x000031DC)*/
/*! Slice: wdr2_bin_range_6:*/
#define  WDR2_BIN_RANGE_6
#define  WDR2_BIN_RANGE_6_MASK 0x0FFF0000U
#define  WDR2_BIN_RANGE_6_SHIFT 16U
/*! Slice: wdr2_bin_range_5:*/
#define  WDR2_BIN_RANGE_5
#define  WDR2_BIN_RANGE_5_MASK 0x00000FFFU
#define  WDR2_BIN_RANGE_5_SHIFT 0U
/*! Register: isp_wdr2_bin_range_3  (0x000031E0)*/
/*! Slice: wdr2_bin_range_8:*/
#define  WDR2_BIN_RANGE_8
#define  WDR2_BIN_RANGE_8_MASK 0x0FFF0000U
#define  WDR2_BIN_RANGE_8_SHIFT 16U
/*! Slice: wdr2_bin_range_7:*/
#define  WDR2_BIN_RANGE_7
#define  WDR2_BIN_RANGE_7_MASK 0x00000FFFU
#define  WDR2_BIN_RANGE_7_SHIFT 0U
/*! Register: isp_wdr2_hist_data_0  (0x000031E4)*/
/*! Slice: wdr2_hist_data_3:*/
#define  WDR2_HIST_DATA_3
#define  WDR2_HIST_DATA_3_MASK 0xFF000000U
#define  WDR2_HIST_DATA_3_SHIFT 24U
/*! Slice: wdr2_hist_data_2:*/
#define  WDR2_HIST_DATA_2
#define  WDR2_HIST_DATA_2_MASK 0x00FF0000U
#define  WDR2_HIST_DATA_2_SHIFT 16U
/*! Slice: wdr2_hist_data_1:*/
#define  WDR2_HIST_DATA_1
#define  WDR2_HIST_DATA_1_MASK 0x0000FF00U
#define  WDR2_HIST_DATA_1_SHIFT 8U
/*! Slice: wdr2_hist_data_0:*/
#define  WDR2_HIST_DATA_0
#define  WDR2_HIST_DATA_0_MASK 0x000000FFU
#define  WDR2_HIST_DATA_0_SHIFT 0U
/*! Register: isp_wdr2_hist_data_1  (0x000031E8)*/
/*! Slice: wdr2_hist_data_7:*/
#define  WDR2_HIST_DATA_7
#define  WDR2_HIST_DATA_7_MASK 0xFF000000U
#define  WDR2_HIST_DATA_7_SHIFT 24U
/*! Slice: wdr2_hist_data_6:*/
#define  WDR2_HIST_DATA_6
#define  WDR2_HIST_DATA_6_MASK 0x00FF0000U
#define  WDR2_HIST_DATA_6_SHIFT 16U
/*! Slice: wdr2_hist_data_5:*/
#define  WDR2_HIST_DATA_5
#define  WDR2_HIST_DATA_5_MASK 0x0000FF00U
#define  WDR2_HIST_DATA_5_SHIFT 8U
/*! Slice: wdr2_hist_data_4:*/
#define  WDR2_HIST_DATA_4
#define  WDR2_HIST_DATA_4_MASK 0x000000FFU
#define  WDR2_HIST_DATA_4_SHIFT 0U
/*! Register: isp_compand_ctrl  (0x00003200)*/
/*! Slice: compand_ctrl_bls_enable:*/
#define  COMPAND_CTRL_BLS_ENABLE
#define  COMPAND_CTRL_BLS_ENABLE_MASK 0x00000008U
#define  COMPAND_CTRL_BLS_ENABLE_SHIFT 3U
/*! Slice: compand_ctrl_soft_reset_flag:*/
#define  COMPAND_CTRL_SOFT_RESET_FLAG
#define  COMPAND_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U
#define  COMPAND_CTRL_SOFT_RESET_FLAG_SHIFT 2U
/*! Slice: compand_ctrl_compress_enable:*/
#define  COMPAND_CTRL_COMPRESS_ENABLE
#define  COMPAND_CTRL_COMPRESS_ENABLE_MASK 0x00000002U
#define  COMPAND_CTRL_COMPRESS_ENABLE_SHIFT 1U
/*! Slice: compand_ctrl_expand_enable:*/
#define  COMPAND_CTRL_EXPAND_ENABLE
#define  COMPAND_CTRL_EXPAND_ENABLE_MASK 0x00000001U
#define  COMPAND_CTRL_EXPAND_ENABLE_SHIFT 0U
/*! Register: isp_compand_bls_a_fixed  (0x00003204)*/
/*! Slice: compand_bls_a_fixed:*/
#define  COMPAND_BLS_A_FIXED
#define  COMPAND_BLS_A_FIXED_MASK 0x001FFFFFU
#define  COMPAND_BLS_A_FIXED_SHIFT 0U
/*! Register: isp_compand_bls_b_fixed  (0x00003208)*/
/*! Slice: compand_bls_b_fixed:*/
#define  COMPAND_BLS_B_FIXED
#define  COMPAND_BLS_B_FIXED_MASK 0x001FFFFFU
#define  COMPAND_BLS_B_FIXED_SHIFT 0U
/*! Register: isp_compand_bls_c_fixed  (0x0000320C)*/
/*! Slice: compand_bls_c_fixed:*/
#define  COMPAND_BLS_C_FIXED
#define  COMPAND_BLS_C_FIXED_MASK 0x001FFFFFU
#define  COMPAND_BLS_C_FIXED_SHIFT 0U
/*! Register: isp_compand_bls_d_fixed  (0x00003210)*/
/*! Slice: compand_bls_d_fixed:*/
#define  COMPAND_BLS_D_FIXED
#define  COMPAND_BLS_D_FIXED_MASK 0x001FFFFFU
#define  COMPAND_BLS_D_FIXED_SHIFT 0U
/*! Register: isp_compand_expand_px_0  (0x00003214)*/
/*! Slice: compand_expand_px_5:*/
#define  COMPAND_EXPAND_PX_5
#define  COMPAND_EXPAND_PX_5_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_5_SHIFT 25U
/*! Slice: compand_expand_px_4:*/
#define  COMPAND_EXPAND_PX_4
#define  COMPAND_EXPAND_PX_4_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_4_SHIFT 20U
/*! Slice: compand_expand_px_3:*/
#define  COMPAND_EXPAND_PX_3
#define  COMPAND_EXPAND_PX_3_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_3_SHIFT 15U
/*! Slice: compand_expand_px_2:*/
#define  COMPAND_EXPAND_PX_2
#define  COMPAND_EXPAND_PX_2_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_2_SHIFT 10U
/*! Slice: compand_expand_px_1:*/
#define  COMPAND_EXPAND_PX_1
#define  COMPAND_EXPAND_PX_1_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_1_SHIFT 5U
/*! Slice: compand_expand_px_0:*/
#define  COMPAND_EXPAND_PX_0
#define  COMPAND_EXPAND_PX_0_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_0_SHIFT 0U
/*! Register: isp_compand_expand_px_1  (0x00003218)*/
/*! Slice: compand_expand_px_11:*/
#define  COMPAND_EXPAND_PX_11
#define  COMPAND_EXPAND_PX_11_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_11_SHIFT 25U
/*! Slice: compand_expand_px_10:*/
#define  COMPAND_EXPAND_PX_10
#define  COMPAND_EXPAND_PX_10_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_10_SHIFT 20U
/*! Slice: compand_expand_px_9:*/
#define  COMPAND_EXPAND_PX_9
#define  COMPAND_EXPAND_PX_9_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_9_SHIFT 15U
/*! Slice: compand_expand_px_8:*/
#define  COMPAND_EXPAND_PX_8
#define  COMPAND_EXPAND_PX_8_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_8_SHIFT 10U
/*! Slice: compand_expand_px_7:*/
#define  COMPAND_EXPAND_PX_7
#define  COMPAND_EXPAND_PX_7_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_7_SHIFT 5U
/*! Slice: compand_expand_px_6:*/
#define  COMPAND_EXPAND_PX_6
#define  COMPAND_EXPAND_PX_6_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_6_SHIFT 0U
/*! Register: isp_compand_expand_px_2  (0x0000321C)*/
/*! Slice: compand_expand_px_17:*/
#define  COMPAND_EXPAND_PX_17
#define  COMPAND_EXPAND_PX_17_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_17_SHIFT 25U
/*! Slice: compand_expand_px_16:*/
#define  COMPAND_EXPAND_PX_16
#define  COMPAND_EXPAND_PX_16_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_16_SHIFT 20U
/*! Slice: compand_expand_px_15:*/
#define  COMPAND_EXPAND_PX_15
#define  COMPAND_EXPAND_PX_15_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_15_SHIFT 15U
/*! Slice: compand_expand_px_14:*/
#define  COMPAND_EXPAND_PX_14
#define  COMPAND_EXPAND_PX_14_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_14_SHIFT 10U
/*! Slice: compand_expand_px_13:*/
#define  COMPAND_EXPAND_PX_13
#define  COMPAND_EXPAND_PX_13_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_13_SHIFT 5U
/*! Slice: compand_expand_px_12:*/
#define  COMPAND_EXPAND_PX_12
#define  COMPAND_EXPAND_PX_12_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_12_SHIFT 0U
/*! Register: isp_compand_expand_px_3  (0x00003220)*/
/*! Slice: compand_expand_px_23:*/
#define  COMPAND_EXPAND_PX_23
#define  COMPAND_EXPAND_PX_23_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_23_SHIFT 25U
/*! Slice: compand_expand_px_22:*/
#define  COMPAND_EXPAND_PX_22
#define  COMPAND_EXPAND_PX_22_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_22_SHIFT 20U
/*! Slice: compand_expand_px_21:*/
#define  COMPAND_EXPAND_PX_21
#define  COMPAND_EXPAND_PX_21_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_21_SHIFT 15U
/*! Slice: compand_expand_px_20:*/
#define  COMPAND_EXPAND_PX_20
#define  COMPAND_EXPAND_PX_20_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_20_SHIFT 10U
/*! Slice: compand_expand_px_19:*/
#define  COMPAND_EXPAND_PX_19
#define  COMPAND_EXPAND_PX_19_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_19_SHIFT 5U
/*! Slice: compand_expand_px_18:*/
#define  COMPAND_EXPAND_PX_18
#define  COMPAND_EXPAND_PX_18_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_18_SHIFT 0U
/*! Register: isp_compand_expand_px_4  (0x00003224)*/
/*! Slice: compand_expand_px_29:*/
#define  COMPAND_EXPAND_PX_29
#define  COMPAND_EXPAND_PX_29_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_29_SHIFT 25U
/*! Slice: compand_expand_px_28:*/
#define  COMPAND_EXPAND_PX_28
#define  COMPAND_EXPAND_PX_28_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_28_SHIFT 20U
/*! Slice: compand_expand_px_27:*/
#define  COMPAND_EXPAND_PX_27
#define  COMPAND_EXPAND_PX_27_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_27_SHIFT 15U
/*! Slice: compand_expand_px_26:*/
#define  COMPAND_EXPAND_PX_26
#define  COMPAND_EXPAND_PX_26_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_26_SHIFT 10U
/*! Slice: compand_expand_px_25:*/
#define  COMPAND_EXPAND_PX_25
#define  COMPAND_EXPAND_PX_25_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_25_SHIFT 5U
/*! Slice: compand_expand_px_24:*/
#define  COMPAND_EXPAND_PX_24
#define  COMPAND_EXPAND_PX_24_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_24_SHIFT 0U
/*! Register: isp_compand_expand_px_5  (0x00003228)*/
/*! Slice: compand_expand_px_35:*/
#define  COMPAND_EXPAND_PX_35
#define  COMPAND_EXPAND_PX_35_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_35_SHIFT 25U
/*! Slice: compand_expand_px_34:*/
#define  COMPAND_EXPAND_PX_34
#define  COMPAND_EXPAND_PX_34_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_34_SHIFT 20U
/*! Slice: compand_expand_px_33:*/
#define  COMPAND_EXPAND_PX_33
#define  COMPAND_EXPAND_PX_33_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_33_SHIFT 15U
/*! Slice: compand_expand_px_32:*/
#define  COMPAND_EXPAND_PX_32
#define  COMPAND_EXPAND_PX_32_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_32_SHIFT 10U
/*! Slice: compand_expand_px_31:*/
#define  COMPAND_EXPAND_PX_31
#define  COMPAND_EXPAND_PX_31_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_31_SHIFT 5U
/*! Slice: compand_expand_px_30:*/
#define  COMPAND_EXPAND_PX_30
#define  COMPAND_EXPAND_PX_30_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_30_SHIFT 0U
/*! Register: isp_compand_expand_px_6  (0x0000322C)*/
/*! Slice: compand_expand_px_41:*/
#define  COMPAND_EXPAND_PX_41
#define  COMPAND_EXPAND_PX_41_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_41_SHIFT 25U
/*! Slice: compand_expand_px_40:*/
#define  COMPAND_EXPAND_PX_40
#define  COMPAND_EXPAND_PX_40_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_40_SHIFT 20U
/*! Slice: compand_expand_px_39:*/
#define  COMPAND_EXPAND_PX_39
#define  COMPAND_EXPAND_PX_39_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_39_SHIFT 15U
/*! Slice: compand_expand_px_38:*/
#define  COMPAND_EXPAND_PX_38
#define  COMPAND_EXPAND_PX_38_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_38_SHIFT 10U
/*! Slice: compand_expand_px_37:*/
#define  COMPAND_EXPAND_PX_37
#define  COMPAND_EXPAND_PX_37_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_37_SHIFT 5U
/*! Slice: compand_expand_px_36:*/
#define  COMPAND_EXPAND_PX_36
#define  COMPAND_EXPAND_PX_36_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_36_SHIFT 0U
/*! Register: isp_compand_expand_px_7  (0x00003230)*/
/*! Slice: compand_expand_px_47:*/
#define  COMPAND_EXPAND_PX_47
#define  COMPAND_EXPAND_PX_47_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_47_SHIFT 25U
/*! Slice: compand_expand_px_46:*/
#define  COMPAND_EXPAND_PX_46
#define  COMPAND_EXPAND_PX_46_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_46_SHIFT 20U
/*! Slice: compand_expand_px_45:*/
#define  COMPAND_EXPAND_PX_45
#define  COMPAND_EXPAND_PX_45_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_45_SHIFT 15U
/*! Slice: compand_expand_px_44:*/
#define  COMPAND_EXPAND_PX_44
#define  COMPAND_EXPAND_PX_44_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_44_SHIFT 10U
/*! Slice: compand_expand_px_43:*/
#define  COMPAND_EXPAND_PX_43
#define  COMPAND_EXPAND_PX_43_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_43_SHIFT 5U
/*! Slice: compand_expand_px_42:*/
#define  COMPAND_EXPAND_PX_42
#define  COMPAND_EXPAND_PX_42_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_42_SHIFT 0U
/*! Register: isp_compand_expand_px_8  (0x00003234)*/
/*! Slice: compand_expand_px_53:*/
#define  COMPAND_EXPAND_PX_53
#define  COMPAND_EXPAND_PX_53_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_53_SHIFT 25U
/*! Slice: compand_expand_px_52:*/
#define  COMPAND_EXPAND_PX_52
#define  COMPAND_EXPAND_PX_52_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_52_SHIFT 20U
/*! Slice: compand_expand_px_51:*/
#define  COMPAND_EXPAND_PX_51
#define  COMPAND_EXPAND_PX_51_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_51_SHIFT 15U
/*! Slice: compand_expand_px_50:*/
#define  COMPAND_EXPAND_PX_50
#define  COMPAND_EXPAND_PX_50_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_50_SHIFT 10U
/*! Slice: compand_expand_px_49:*/
#define  COMPAND_EXPAND_PX_49
#define  COMPAND_EXPAND_PX_49_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_49_SHIFT 5U
/*! Slice: compand_expand_px_48:*/
#define  COMPAND_EXPAND_PX_48
#define  COMPAND_EXPAND_PX_48_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_48_SHIFT 0U
/*! Register: isp_compand_expand_px_9  (0x00003238)*/
/*! Slice: compand_expand_px_59:*/
#define  COMPAND_EXPAND_PX_59
#define  COMPAND_EXPAND_PX_59_MASK 0x3E000000U
#define  COMPAND_EXPAND_PX_59_SHIFT 25U
/*! Slice: compand_expand_px_58:*/
#define  COMPAND_EXPAND_PX_58
#define  COMPAND_EXPAND_PX_58_MASK 0x01F00000U
#define  COMPAND_EXPAND_PX_58_SHIFT 20U
/*! Slice: compand_expand_px_57:*/
#define  COMPAND_EXPAND_PX_57
#define  COMPAND_EXPAND_PX_57_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_57_SHIFT 15U
/*! Slice: compand_expand_px_56:*/
#define  COMPAND_EXPAND_PX_56
#define  COMPAND_EXPAND_PX_56_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_56_SHIFT 10U
/*! Slice: compand_expand_px_55:*/
#define  COMPAND_EXPAND_PX_55
#define  COMPAND_EXPAND_PX_55_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_55_SHIFT 5U
/*! Slice: compand_expand_px_54:*/
#define  COMPAND_EXPAND_PX_54
#define  COMPAND_EXPAND_PX_54_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_54_SHIFT 0U
/*! Register: isp_compand_expand_px_10  (0x0000323C)*/
/*! Slice: compand_expand_px_63:*/
#define  COMPAND_EXPAND_PX_63
#define  COMPAND_EXPAND_PX_63_MASK 0x000F8000U
#define  COMPAND_EXPAND_PX_63_SHIFT 15U
/*! Slice: compand_expand_px_62:*/
#define  COMPAND_EXPAND_PX_62
#define  COMPAND_EXPAND_PX_62_MASK 0x00007C00U
#define  COMPAND_EXPAND_PX_62_SHIFT 10U
/*! Slice: compand_expand_px_61:*/
#define  COMPAND_EXPAND_PX_61
#define  COMPAND_EXPAND_PX_61_MASK 0x000003E0U
#define  COMPAND_EXPAND_PX_61_SHIFT 5U
/*! Slice: compand_expand_px_60:*/
#define  COMPAND_EXPAND_PX_60
#define  COMPAND_EXPAND_PX_60_MASK 0x0000001FU
#define  COMPAND_EXPAND_PX_60_SHIFT 0U
/*! Register: isp_compand_compress_px_0  (0x00003240)*/
/*! Slice: compand_compress_px_5:*/
#define  COMPAND_COMPRESS_PX_5
#define  COMPAND_COMPRESS_PX_5_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_5_SHIFT 25U
/*! Slice: compand_compress_px_4:*/
#define  COMPAND_COMPRESS_PX_4
#define  COMPAND_COMPRESS_PX_4_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_4_SHIFT 20U
/*! Slice: compand_compress_px_3:*/
#define  COMPAND_COMPRESS_PX_3
#define  COMPAND_COMPRESS_PX_3_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_3_SHIFT 15U
/*! Slice: compand_compress_px_2:*/
#define  COMPAND_COMPRESS_PX_2
#define  COMPAND_COMPRESS_PX_2_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_2_SHIFT 10U
/*! Slice: compand_compress_px_1:*/
#define  COMPAND_COMPRESS_PX_1
#define  COMPAND_COMPRESS_PX_1_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_1_SHIFT 5U
/*! Slice: compand_compress_px_0:*/
#define  COMPAND_COMPRESS_PX_0
#define  COMPAND_COMPRESS_PX_0_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_0_SHIFT 0U
/*! Register: isp_compand_compress_px_1  (0x00003244)*/
/*! Slice: compand_compress_px_11:*/
#define  COMPAND_COMPRESS_PX_11
#define  COMPAND_COMPRESS_PX_11_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_11_SHIFT 25U
/*! Slice: compand_compress_px_10:*/
#define  COMPAND_COMPRESS_PX_10
#define  COMPAND_COMPRESS_PX_10_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_10_SHIFT 20U
/*! Slice: compand_compress_px_9:*/
#define  COMPAND_COMPRESS_PX_9
#define  COMPAND_COMPRESS_PX_9_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_9_SHIFT 15U
/*! Slice: compand_compress_px_8:*/
#define  COMPAND_COMPRESS_PX_8
#define  COMPAND_COMPRESS_PX_8_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_8_SHIFT 10U
/*! Slice: compand_compress_px_7:*/
#define  COMPAND_COMPRESS_PX_7
#define  COMPAND_COMPRESS_PX_7_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_7_SHIFT 5U
/*! Slice: compand_compress_px_6:*/
#define  COMPAND_COMPRESS_PX_6
#define  COMPAND_COMPRESS_PX_6_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_6_SHIFT 0U
/*! Register: isp_compand_compress_px_2  (0x00003248)*/
/*! Slice: compand_compress_px_17:*/
#define  COMPAND_COMPRESS_PX_17
#define  COMPAND_COMPRESS_PX_17_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_17_SHIFT 25U
/*! Slice: compand_compress_px_16:*/
#define  COMPAND_COMPRESS_PX_16
#define  COMPAND_COMPRESS_PX_16_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_16_SHIFT 20U
/*! Slice: compand_compress_px_15:*/
#define  COMPAND_COMPRESS_PX_15
#define  COMPAND_COMPRESS_PX_15_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_15_SHIFT 15U
/*! Slice: compand_compress_px_14:*/
#define  COMPAND_COMPRESS_PX_14
#define  COMPAND_COMPRESS_PX_14_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_14_SHIFT 10U
/*! Slice: compand_compress_px_13:*/
#define  COMPAND_COMPRESS_PX_13
#define  COMPAND_COMPRESS_PX_13_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_13_SHIFT 5U
/*! Slice: compand_compress_px_12:*/
#define  COMPAND_COMPRESS_PX_12
#define  COMPAND_COMPRESS_PX_12_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_12_SHIFT 0U
/*! Register: isp_compand_compress_px_3  (0x0000324C)*/
/*! Slice: compand_compress_px_23:*/
#define  COMPAND_COMPRESS_PX_23
#define  COMPAND_COMPRESS_PX_23_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_23_SHIFT 25U
/*! Slice: compand_compress_px_22:*/
#define  COMPAND_COMPRESS_PX_22
#define  COMPAND_COMPRESS_PX_22_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_22_SHIFT 20U
/*! Slice: compand_compress_px_21:*/
#define  COMPAND_COMPRESS_PX_21
#define  COMPAND_COMPRESS_PX_21_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_21_SHIFT 15U
/*! Slice: compand_compress_px_20:*/
#define  COMPAND_COMPRESS_PX_20
#define  COMPAND_COMPRESS_PX_20_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_20_SHIFT 10U
/*! Slice: compand_compress_px_19:*/
#define  COMPAND_COMPRESS_PX_19
#define  COMPAND_COMPRESS_PX_19_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_19_SHIFT 5U
/*! Slice: compand_compress_px_18:*/
#define  COMPAND_COMPRESS_PX_18
#define  COMPAND_COMPRESS_PX_18_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_18_SHIFT 0U
/*! Register: isp_compand_compress_px_4  (0x00003250)*/
/*! Slice: compand_compress_px_29:*/
#define  COMPAND_COMPRESS_PX_29
#define  COMPAND_COMPRESS_PX_29_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_29_SHIFT 25U
/*! Slice: compand_compress_px_28:*/
#define  COMPAND_COMPRESS_PX_28
#define  COMPAND_COMPRESS_PX_28_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_28_SHIFT 20U
/*! Slice: compand_compress_px_27:*/
#define  COMPAND_COMPRESS_PX_27
#define  COMPAND_COMPRESS_PX_27_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_27_SHIFT 15U
/*! Slice: compand_compress_px_26:*/
#define  COMPAND_COMPRESS_PX_26
#define  COMPAND_COMPRESS_PX_26_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_26_SHIFT 10U
/*! Slice: compand_compress_px_25:*/
#define  COMPAND_COMPRESS_PX_25
#define  COMPAND_COMPRESS_PX_25_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_25_SHIFT 5U
/*! Slice: compand_compress_px_24:*/
#define  COMPAND_COMPRESS_PX_24
#define  COMPAND_COMPRESS_PX_24_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_24_SHIFT 0U
/*! Register: isp_compand_compress_px_5  (0x00003254)*/
/*! Slice: compand_compress_px_35:*/
#define  COMPAND_COMPRESS_PX_35
#define  COMPAND_COMPRESS_PX_35_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_35_SHIFT 25U
/*! Slice: compand_compress_px_34:*/
#define  COMPAND_COMPRESS_PX_34
#define  COMPAND_COMPRESS_PX_34_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_34_SHIFT 20U
/*! Slice: compand_compress_px_33:*/
#define  COMPAND_COMPRESS_PX_33
#define  COMPAND_COMPRESS_PX_33_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_33_SHIFT 15U
/*! Slice: compand_compress_px_32:*/
#define  COMPAND_COMPRESS_PX_32
#define  COMPAND_COMPRESS_PX_32_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_32_SHIFT 10U
/*! Slice: compand_compress_px_31:*/
#define  COMPAND_COMPRESS_PX_31
#define  COMPAND_COMPRESS_PX_31_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_31_SHIFT 5U
/*! Slice: compand_compress_px_30:*/
#define  COMPAND_COMPRESS_PX_30
#define  COMPAND_COMPRESS_PX_30_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_30_SHIFT 0U
/*! Register: isp_compand_compress_px_6  (0x00003258)*/
/*! Slice: compand_compress_px_41:*/
#define  COMPAND_COMPRESS_PX_41
#define  COMPAND_COMPRESS_PX_41_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_41_SHIFT 25U
/*! Slice: compand_compress_px_40:*/
#define  COMPAND_COMPRESS_PX_40
#define  COMPAND_COMPRESS_PX_40_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_40_SHIFT 20U
/*! Slice: compand_compress_px_39:*/
#define  COMPAND_COMPRESS_PX_39
#define  COMPAND_COMPRESS_PX_39_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_39_SHIFT 15U
/*! Slice: compand_compress_px_38:*/
#define  COMPAND_COMPRESS_PX_38
#define  COMPAND_COMPRESS_PX_38_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_38_SHIFT 10U
/*! Slice: compand_compress_px_37:*/
#define  COMPAND_COMPRESS_PX_37
#define  COMPAND_COMPRESS_PX_37_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_37_SHIFT 5U
/*! Slice: compand_compress_px_36:*/
#define  COMPAND_COMPRESS_PX_36
#define  COMPAND_COMPRESS_PX_36_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_36_SHIFT 0U
/*! Register: isp_compand_compress_px_7  (0x0000325C)*/
/*! Slice: compand_compress_px_47:*/
#define  COMPAND_COMPRESS_PX_47
#define  COMPAND_COMPRESS_PX_47_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_47_SHIFT 25U
/*! Slice: compand_compress_px_46:*/
#define  COMPAND_COMPRESS_PX_46
#define  COMPAND_COMPRESS_PX_46_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_46_SHIFT 20U
/*! Slice: compand_compress_px_45:*/
#define  COMPAND_COMPRESS_PX_45
#define  COMPAND_COMPRESS_PX_45_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_45_SHIFT 15U
/*! Slice: compand_compress_px_44:*/
#define  COMPAND_COMPRESS_PX_44
#define  COMPAND_COMPRESS_PX_44_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_44_SHIFT 10U
/*! Slice: compand_compress_px_43:*/
#define  COMPAND_COMPRESS_PX_43
#define  COMPAND_COMPRESS_PX_43_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_43_SHIFT 5U
/*! Slice: compand_compress_px_42:*/
#define  COMPAND_COMPRESS_PX_42
#define  COMPAND_COMPRESS_PX_42_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_42_SHIFT 0U
/*! Register: isp_compand_compress_px_8  (0x00003260)*/
/*! Slice: compand_compress_px_53:*/
#define  COMPAND_COMPRESS_PX_53
#define  COMPAND_COMPRESS_PX_53_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_53_SHIFT 25U
/*! Slice: compand_compress_px_52:*/
#define  COMPAND_COMPRESS_PX_52
#define  COMPAND_COMPRESS_PX_52_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_52_SHIFT 20U
/*! Slice: compand_compress_px_51:*/
#define  COMPAND_COMPRESS_PX_51
#define  COMPAND_COMPRESS_PX_51_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_51_SHIFT 15U
/*! Slice: compand_compress_px_50:*/
#define  COMPAND_COMPRESS_PX_50
#define  COMPAND_COMPRESS_PX_50_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_50_SHIFT 10U
/*! Slice: compand_compress_px_49:*/
#define  COMPAND_COMPRESS_PX_49
#define  COMPAND_COMPRESS_PX_49_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_49_SHIFT 5U
/*! Slice: compand_compress_px_48:*/
#define  COMPAND_COMPRESS_PX_48
#define  COMPAND_COMPRESS_PX_48_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_48_SHIFT 0U
/*! Register: isp_compand_compress_px_9  (0x00003264)*/
/*! Slice: compand_compress_px_59:*/
#define  COMPAND_COMPRESS_PX_59
#define  COMPAND_COMPRESS_PX_59_MASK 0x3E000000U
#define  COMPAND_COMPRESS_PX_59_SHIFT 25U
/*! Slice: compand_compress_px_58:*/
#define  COMPAND_COMPRESS_PX_58
#define  COMPAND_COMPRESS_PX_58_MASK 0x01F00000U
#define  COMPAND_COMPRESS_PX_58_SHIFT 20U
/*! Slice: compand_compress_px_57:*/
#define  COMPAND_COMPRESS_PX_57
#define  COMPAND_COMPRESS_PX_57_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_57_SHIFT 15U
/*! Slice: compand_compress_px_56:*/
#define  COMPAND_COMPRESS_PX_56
#define  COMPAND_COMPRESS_PX_56_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_56_SHIFT 10U
/*! Slice: compand_compress_px_55:*/
#define  COMPAND_COMPRESS_PX_55
#define  COMPAND_COMPRESS_PX_55_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_55_SHIFT 5U
/*! Slice: compand_compress_px_54:*/
#define  COMPAND_COMPRESS_PX_54
#define  COMPAND_COMPRESS_PX_54_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_54_SHIFT 0U
/*! Register: isp_compand_compress_px_10  (0x00003268)*/
/*! Slice: compand_compress_px_63:*/
#define  COMPAND_COMPRESS_PX_63
#define  COMPAND_COMPRESS_PX_63_MASK 0x000F8000U
#define  COMPAND_COMPRESS_PX_63_SHIFT 15U
/*! Slice: compand_compress_px_62:*/
#define  COMPAND_COMPRESS_PX_62
#define  COMPAND_COMPRESS_PX_62_MASK 0x00007C00U
#define  COMPAND_COMPRESS_PX_62_SHIFT 10U
/*! Slice: compand_compress_px_61:*/
#define  COMPAND_COMPRESS_PX_61
#define  COMPAND_COMPRESS_PX_61_MASK 0x000003E0U
#define  COMPAND_COMPRESS_PX_61_SHIFT 5U
/*! Slice: compand_compress_px_60:*/
#define  COMPAND_COMPRESS_PX_60
#define  COMPAND_COMPRESS_PX_60_MASK 0x0000001FU
#define  COMPAND_COMPRESS_PX_60_SHIFT 0U
/*! Register: isp_compand_expand_y_addr  (0x0000326C)*/
/*! Slice: compand_expand_y_addr:*/
#define  COMPAND_EXPAND_Y_ADDR
#define  COMPAND_EXPAND_Y_ADDR_MASK 0xFFFFFFFFU
#define  COMPAND_EXPAND_Y_ADDR_SHIFT 0U
/*! Register: isp_compand_expand_y_write_data  (0x00003270)*/
/*! Slice: compand_expand_y_write_data:*/
#define  COMPAND_EXPAND_Y_WRITE_DATA
#define  COMPAND_EXPAND_Y_WRITE_DATA_MASK 0x000FFFFFU
#define  COMPAND_EXPAND_Y_WRITE_DATA_SHIFT 0U
/*! Register: isp_compand_compress_y_addr  (0x00003274)*/
/*! Slice: compand_compress_y_addr:*/
#define  COMPAND_COMPRESS_Y_ADDR
#define  COMPAND_COMPRESS_Y_ADDR_MASK 0xFFFFFFFFU
#define  COMPAND_COMPRESS_Y_ADDR_SHIFT 0U
/*! Register: isp_compand_compress_y_write_data  (0x00003278)*/
/*! Slice: compand_compress_y_write_data:*/
#define  COMPAND_COMPRESS_Y_WRITE_DATA
#define  COMPAND_COMPRESS_Y_WRITE_DATA_MASK 0x0000FFFFU
#define  COMPAND_COMPRESS_Y_WRITE_DATA_SHIFT 0U
/*! Register: isp_compand_expand_x_addr  (0x0000327C)*/
/*! Slice: compand_expand_x_addr:*/
#define  COMPAND_EXPAND_X_ADDR
#define  COMPAND_EXPAND_X_ADDR_MASK 0xFFFFFFFFU
#define  COMPAND_EXPAND_X_ADDR_SHIFT 0U
/*! Register: isp_compand_expand_x_write_data  (0x00003280)*/
/*! Slice: compand_expand_x_write_data:*/
#define  COMPAND_EXPAND_X_WRITE_DATA
#define  COMPAND_EXPAND_X_WRITE_DATA_MASK 0x000FFFFFU
#define  COMPAND_EXPAND_X_WRITE_DATA_SHIFT 0U
/*! Register: isp_compand_compress_x_addr  (0x00003284)*/
/*! Slice: compand_compress_x_addr:*/
#define  COMPAND_COMPRESS_X_ADDR
#define  COMPAND_COMPRESS_X_ADDR_MASK 0xFFFFFFFFU
#define  COMPAND_COMPRESS_X_ADDR_SHIFT 0U
/*! Register: isp_compand_compress_x_write_data  (0x00003288)*/
/*! Slice: compand_compress_x_write_data:*/
#define  COMPAND_COMPRESS_X_WRITE_DATA
#define  COMPAND_COMPRESS_X_WRITE_DATA_MASK 0x000FFFFFU
#define  COMPAND_COMPRESS_X_WRITE_DATA_SHIFT 0U
/*! Register: isp_wdr3_ctrl   (0x00003500)*/
/*! Slice: wdr3_dummmy_blk:*/
#define  WDR3_DUMMY_BLK
#define  WDR3_DUMMY_BLK_MASK 0xffff0000U
#define  WDR3_DUMMY_BLK_SHIFT 16U
/*! Register: isp_wdr3_ctrl   (0x00003500)*/
/*! Slice: wdr3_dummy_blk_en:*/
#define  WDR3_DUMMY_BLK_EN
#define  WDR3_DUMMY_BLK_EN_MASK 0x00008000U
#define  WDR3_DUMMY_BLK_EN_SHIFT 15U
/*! Register: isp_wdr3_ctrl   (0x00003500)*/
/*! Slice: wdr3_interrupt_en:*/
#define  WDR3_INTERRUPT_EN
#define  WDR3_INTERRUPT_EN_MASK 0x00000200U
#define  WDR3_INTERRUPT_EN_SHIFT 9U
/*! Slice: wdr3_soft_reset_flag:*/
#define  WDR3_SOFT_RESET_FLAG
#define  WDR3_SOFT_RESET_FLAG_MASK 0x00000002U
#define  WDR3_SOFT_RESET_FLAG_SHIFT 1U
/*! Slice: wdr3_enable:*/
#define  WDR3_ENABLE
#define  WDR3_ENABLE_MASK 0x00000001U
#define  WDR3_ENABLE_SHIFT 0U
/*! Register: isp_wdr3_shift  (0x00003504)*/
/*! Slice: wdr3_gain_shift_bit:*/
#define  WDR3_GAIN_SHIFT_BIT
#define  WDR3_GAIN_SHIFT_BIT_MASK 0x00FC0000U
#define  WDR3_GAIN_SHIFT_BIT_SHIFT 18U
/*! Slice: wdr3_normalize_shift_bit:*/
#define  WDR3_NORMALIZE_SHIFT_BIT
#define  WDR3_NORMALIZE_SHIFT_BIT_MASK 0x0003F000U
#define  WDR3_NORMALIZE_SHIFT_BIT_SHIFT 12U
/*! Slice: wdr3_output_shift_bit:*/
#define  WDR3_OUTPUT_SHIFT_BIT
#define  WDR3_OUTPUT_SHIFT_BIT_MASK 0x00000FC0U
#define  WDR3_OUTPUT_SHIFT_BIT_SHIFT 6U
/*! Slice: wdr3_pixel_shift_bit:*/
#define  WDR3_PIXEL_SHIFT_BIT
#define  WDR3_PIXEL_SHIFT_BIT_MASK 0x0000003FU
#define  WDR3_PIXEL_SHIFT_BIT_SHIFT 0U
/*! Register: isp_wdr3_block_size  (0x00003508)*/
/*! Slice: wdr3_block_height:*/
#define  WDR3_BLOCK_HEIGHT
#define  WDR3_BLOCK_HEIGHT_MASK 0x0003FE00U
#define  WDR3_BLOCK_HEIGHT_SHIFT 9U
/*! Slice: wdr3_block_width:*/
#define  WDR3_BLOCK_WIDTH
#define  WDR3_BLOCK_WIDTH_MASK 0x000001FFU
#define  WDR3_BLOCK_WIDTH_SHIFT 0U
/*! Register: isp_wdr3_block_area_factor  (0x0000350C)*/
/*! Slice: wdr3_block_area_inverse:*/
#define  WDR3_BLOCK_AREA_INVERSE
#define  WDR3_BLOCK_AREA_INVERSE_MASK 0x000FFFFFU
#define  WDR3_BLOCK_AREA_INVERSE_SHIFT 0U
/*! Register: isp_wdr3_value_weight   (0x00003510)*/
/*! Slice: wdr3_value_weight_3:*/
#define  WDR3_VALUE_WEIGHT_3
#define  WDR3_VALUE_WEIGHT_3_MASK 0x000F8000U
#define  WDR3_VALUE_WEIGHT_3_SHIFT 15U
/*! Slice: wdr3_value_weight_2:*/
#define  WDR3_VALUE_WEIGHT_2
#define  WDR3_VALUE_WEIGHT_2_MASK 0x00007C00U
#define  WDR3_VALUE_WEIGHT_2_SHIFT 10U
/*! Slice: wdr3_value_weight_1:*/
#define  WDR3_VALUE_WEIGHT_1
#define  WDR3_VALUE_WEIGHT_1_MASK 0x000003E0U
#define  WDR3_VALUE_WEIGHT_1_SHIFT 5U
/*! Slice: wdr3_value_weight_0:*/
#define  WDR3_VALUE_WEIGHT_0
#define  WDR3_VALUE_WEIGHT_0_MASK 0x0000001FU
#define  WDR3_VALUE_WEIGHT_0_SHIFT 0U
/*! Register: isp_wdr3_strength          (0x00003514)*/
/*! Slice: wdr3_total_strength:*/
#define  WDR3_TOTAL_STRENGTH
#define  WDR3_TOTAL_STRENGTH_MASK 0xFF000000U
#define  WDR3_TOTAL_STRENGTH_SHIFT 24U
/*! Slice: wdr3_local_strength:*/
#define  WDR3_LOCAL_STRENGTH
#define  WDR3_LOCAL_STRENGTH_MASK 0x00FF0000U
#define  WDR3_LOCAL_STRENGTH_SHIFT 16U
/*! Slice: wdr3_global_strength:*/
#define  WDR3_GLOBAL_STRENGTH
#define  WDR3_GLOBAL_STRENGTH_MASK 0x0000FF00U
#define  WDR3_GLOBAL_STRENGTH_SHIFT 8U
/*! Slice: wdr3_maximum_gain:*/
#define  WDR3_MAXIMUM_GAIN
#define  WDR3_MAXIMUM_GAIN_MASK 0x000000FFU
#define  WDR3_MAXIMUM_GAIN_SHIFT 0U
/*! Register: isp_wdr3_pixel_slope  (0x00003518)*/
/*! Slice: wdr3_pixel_merge_slope:*/
#define  WDR3_PIXEL_MERGE_SLOPE
#define  WDR3_PIXEL_MERGE_SLOPE_MASK 0xFF000000U
#define  WDR3_PIXEL_MERGE_SLOPE_SHIFT 24U
/*! Slice: wdr3_pixel_merge_base:*/
#define  WDR3_PIXEL_MERGE_BASE
#define  WDR3_PIXEL_MERGE_BASE_MASK 0x00FF0000U
#define  WDR3_PIXEL_MERGE_BASE_SHIFT 16U
/*! Slice: wdr3_pixel_adjust_slope:*/
#define  WDR3_PIXEL_ADJUST_SLOPE
#define  WDR3_PIXEL_ADJUST_SLOPE_MASK 0x0000FF00U
#define  WDR3_PIXEL_ADJUST_SLOPE_SHIFT 8U
/*! Slice: wdr3_pixel_adjust_base:*/
#define  WDR3_PIXEL_ADJUST_BASE
#define  WDR3_PIXEL_ADJUST_BASE_MASK 0x000000FFU
#define  WDR3_PIXEL_ADJUST_BASE_SHIFT 0U
/*! Register: isp_wdr3_entropy_slope  (0x0000351C)*/
/*! Slice: wdr3_entropy_slope:*/
#define  WDR3_ENTROPY_SLOPE
#define  WDR3_ENTROPY_SLOPE_MASK 0x000FFC00U
#define  WDR3_ENTROPY_SLOPE_SHIFT 10U
/*! Slice: wdr3_entropy_base:*/
#define  WDR3_ENTROPY_BASE
#define  WDR3_ENTROPY_BASE_MASK 0x000003FFU
#define  WDR3_ENTROPY_BASE_SHIFT 0U
/*! Register: isp_wdr3_sigma_width  (0x00003520)*/
/*! Slice: wdr3_biliteral_width_sigma:*/
#define  WDR3_BILITERAL_WIDTH_SIGMA
#define  WDR3_BILITERAL_WIDTH_SIGMA_MASK 0x000FFFFFU
#define  WDR3_BILITERAL_WIDTH_SIGMA_SHIFT 0U
/*! Register: isp_wdr3_sigma_height  (0x00003524)*/
/*! Slice: wdr3_biliteral_height_sigma:*/
#define  WDR3_BILITERAL_HEIGHT_SIGMA
#define  WDR3_BILITERAL_HEIGHT_SIGMA_MASK 0x000FFFFFU
#define  WDR3_BILITERAL_HEIGHT_SIGMA_SHIFT 0U
/*! Register: isp_wdr3_sigma_value  (0x00003528)*/
/*! Slice: wdr3_biliteral_value_sigma:*/
#define  WDR3_BILITERAL_VALUE_SIGMA
#define  WDR3_BILITERAL_VALUE_SIGMA_MASK 0x000FFFFFU
#define  WDR3_BILITERAL_VALUE_SIGMA_SHIFT 0U
/*! Register: isp_wdr3_block_flag_width  (0x0000352C)*/
/*! Slice: wdr3_block_col_flag:*/
#define  WDR3_BLOCK_COL_FLAG
#define  WDR3_BLOCK_COL_FLAG_MASK 0xFFFFFFFFU
#define  WDR3_BLOCK_COL_FLAG_SHIFT 0U
/*! Register: isp_wdr3_block_flag_height  (0x00003530)*/
/*! Slice: wdr3_block_row_flag:*/
#define  WDR3_BLOCK_ROW_FLAG
#define  WDR3_BLOCK_ROW_FLAG_MASK 0xFFFFFFFFU
#define  WDR3_BLOCK_ROW_FLAG_SHIFT 0U
/*! Register: isp_wdr3_frame_average  (0x00003534)*/
/*! Slice: wdr3_frame_average:*/
#define  WDR3_FRAME_AVERAGE
#define  WDR3_FRAME_AVERAGE_MASK 0xFFFFFFFFU
#define  WDR3_FRAME_AVERAGE_SHIFT 0U
/*! Register: isp_wdr3_frame_std  (0x00003538)*/
/*! Slice: wdr3_frame_std:*/
#define  WDR3_FRAME_STD
#define  WDR3_FRAME_STD_MASK 0xFFFFFFFFU
#define  WDR3_FRAME_STD_SHIFT 0U
/*! Register: isp_wdr3_histogram_0  (0x0000353C)*/
/*! Slice: wdr3_histogram_curve0:*/
#define  WDR3_HISTOGRAM_CURVE0
#define  WDR3_HISTOGRAM_CURVE0_MASK 0x3FF00000U
#define  WDR3_HISTOGRAM_CURVE0_SHIFT 20U
/*! Slice: wdr3_histogram_curve1:*/
#define  WDR3_HISTOGRAM_CURVE1
#define  WDR3_HISTOGRAM_CURVE1_MASK 0x000FFC00U
#define  WDR3_HISTOGRAM_CURVE1_SHIFT 10U
/*! Slice: wdr3_histogram_curve2:*/
#define  WDR3_HISTOGRAM_CURVE2
#define  WDR3_HISTOGRAM_CURVE2_MASK 0x000003FFU
#define  WDR3_HISTOGRAM_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_entropy_0  (0x00003550)*/
/*! Slice: wdr3_entropy_convert0:*/
#define  WDR3_ENTROPY_CONVERT0
#define  WDR3_ENTROPY_CONVERT0_MASK 0x07FC0000U
#define  WDR3_ENTROPY_CONVERT0_SHIFT 18U
/*! Slice: wdr3_entropy_convert1:*/
#define  WDR3_ENTROPY_CONVERT1
#define  WDR3_ENTROPY_CONVERT1_MASK 0x0003FE00U
#define  WDR3_ENTROPY_CONVERT1_SHIFT 9U
/*! Slice: wdr3_entropy_convert2:*/
#define  WDR3_ENTROPY_CONVERT2
#define  WDR3_ENTROPY_CONVERT2_MASK 0x000001FFU
#define  WDR3_ENTROPY_CONVERT2_SHIFT 0U
/*! Register: isp_wdr3_gamma_pre_0  (0x00003564)*/
/*! Slice: wdr3_gamma_pre_curve0:*/
#define  WDR3_GAMMA_PRE_CURVE0
#define  WDR3_GAMMA_PRE_CURVE0_MASK 0x3FF00000U
#define  WDR3_GAMMA_PRE_CURVE0_SHIFT 20U
/*! Slice: wdr3_gamma_pre_curve1:*/
#define  WDR3_GAMMA_PRE_CURVE1
#define  WDR3_GAMMA_PRE_CURVE1_MASK 0x000FFC00U
#define  WDR3_GAMMA_PRE_CURVE1_SHIFT 10U
/*! Slice: wdr3_gamma_pre_curve2:*/
#define  WDR3_GAMMA_PRE_CURVE2
#define  WDR3_GAMMA_PRE_CURVE2_MASK 0x000003FFU
#define  WDR3_GAMMA_PRE_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_gamma_up_0  (0x00003578)*/
/*! Slice: wdr3_gamma_up_curve0:*/
#define  WDR3_GAMMA_UP_CURVE0
#define  WDR3_GAMMA_UP_CURVE0_MASK 0x3FF00000U
#define  WDR3_GAMMA_UP_CURVE0_SHIFT 20U
/*! Slice: wdr3_gamma_up_curve1:*/
#define  WDR3_GAMMA_UP_CURVE1
#define  WDR3_GAMMA_UP_CURVE1_MASK 0x000FFC00U
#define  WDR3_GAMMA_UP_CURVE1_SHIFT 10U
/*! Slice: wdr3_gamma_up_curve2:*/
#define  WDR3_GAMMA_UP_CURVE2
#define  WDR3_GAMMA_UP_CURVE2_MASK 0x000003FFU
#define  WDR3_GAMMA_UP_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_gamma_down_0  (0x0000358C)*/
/*! Slice: wdr3_gamma_down_curve0:*/
#define  WDR3_GAMMA_DOWN_CURVE0
#define  WDR3_GAMMA_DOWN_CURVE0_MASK 0x3FF00000U
#define  WDR3_GAMMA_DOWN_CURVE0_SHIFT 20U
/*! Slice: wdr3_gamma_down_curve1:*/
#define  WDR3_GAMMA_DOWN_CURVE1
#define  WDR3_GAMMA_DOWN_CURVE1_MASK 0x000FFC00U
#define  WDR3_GAMMA_DOWN_CURVE1_SHIFT 10U
/*! Slice: wdr3_gamma_down_curve2:*/
#define  WDR3_GAMMA_DOWN_CURVE2
#define  WDR3_GAMMA_DOWN_CURVE2_MASK 0x000003FFU
#define  WDR3_GAMMA_DOWN_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_distance_weight_0  (0x000035A0)*/
/*! Slice: wdr3_distance_weight_curve0:*/
#define  WDR3_DISTANCE_WEIGHT_CURVE0
#define  WDR3_DISTANCE_WEIGHT_CURVE0_MASK 0x001FC000U
#define  WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT 14U
/*! Slice: wdr3_distance_weight_curve1:*/
#define  WDR3_DISTANCE_WEIGHT_CURVE1
#define  WDR3_DISTANCE_WEIGHT_CURVE1_MASK 0x00003F80U
#define  WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT 7U
/*! Slice: wdr3_distance_weight_curve2:*/
#define  WDR3_DISTANCE_WEIGHT_CURVE2
#define  WDR3_DISTANCE_WEIGHT_CURVE2_MASK 0x0000007FU
#define  WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_difference_weight_0  (0x000035B4)*/
/*! Slice: wdr3_difference_weight_curve0:*/
#define  WDR3_DIFFERENCE_WEIGHT_CURVE0
#define  WDR3_DIFFERENCE_WEIGHT_CURVE0_MASK 0x001FC000U
#define  WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT 14U
/*! Slice: wdr3_difference_weight_curve1:*/
#define  WDR3_DIFFERENCE_WEIGHT_CURVE1
#define  WDR3_DIFFERENCE_WEIGHT_CURVE1_MASK 0x00003F80U
#define  WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT 7U
/*! Slice: wdr3_difference_weight_curve2:*/
#define  WDR3_DIFFERENCE_WEIGHT_CURVE2
#define  WDR3_DIFFERENCE_WEIGHT_CURVE2_MASK 0x0000007FU
#define  WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT 0U
/*! Register: isp_wdr3_invert_curve_0  (0x000035C8)*/
/*! Slice: wdr3_global_curve_invert0:*/
#define  WDR3_GLOBAL_CURVE_INVERT0
#define  WDR3_GLOBAL_CURVE_INVERT0_MASK 0x00FFF000U
#define  WDR3_GLOBAL_CURVE_INVERT0_SHIFT 12U
/*! Slice: wdr3_global_curve_invert1:*/
#define  WDR3_GLOBAL_CURVE_INVERT1
#define  WDR3_GLOBAL_CURVE_INVERT1_MASK 0x00000FFFU
#define  WDR3_GLOBAL_CURVE_INVERT1_SHIFT 0U
/*! Register: isp_wdr3_invert_curve_1  (0x000035CC)*/
/*! Slice: wdr3_global_curve_invert2:*/
#define  WDR3_GLOBAL_CURVE_INVERT2
#define  WDR3_GLOBAL_CURVE_INVERT2_MASK 0x00FFF000U
#define  WDR3_GLOBAL_CURVE_INVERT2_SHIFT 12U
/*! Register: isp_wdr3_invert_linear_0  (0x000035E4)*/
/*! Slice: wdr3_linear_curve_invert0:*/
#define  WDR3_LINEAR_CURVE_INVERT0
#define  WDR3_LINEAR_CURVE_INVERT0_MASK 0x00FFF000U
#define  WDR3_LINEAR_CURVE_INVERT0_SHIFT 12U
/*! Slice: wdr3_linear_curve_invert1:*/
#define  WDR3_LINEAR_CURVE_INVERT1
#define  WDR3_LINEAR_CURVE_INVERT1_MASK 0x00000FFFU
#define  WDR3_LINEAR_CURVE_INVERT1_SHIFT 0U
/*! Register: isp_wdr3_invert_linear_1  (0x000035E8)*/
/*! Slice: wdr3_linear_curve_invert2:*/
#define  WDR3_LINEAR_CURVE_INVERT2
#define  WDR3_LINEAR_CURVE_INVERT2_MASK 0x00FFF000U
#define  WDR3_LINEAR_CURVE_INVERT2_SHIFT 12U
/*! Register: isp_wdr3_shift_0  (0x00003600)*/
/*! Slice: wdr3_histogram_shift0:*/
#define  WDR3_HISTOGRAM_SHIFT0
#define  WDR3_HISTOGRAM_SHIFT0_MASK 0xF0000000U
#define  WDR3_HISTOGRAM_SHIFT0_SHIFT 28U
/*! Slice: wdr3_histogram_shift1:*/
#define  WDR3_HISTOGRAM_SHIFT1
#define  WDR3_HISTOGRAM_SHIFT1_MASK 0x0F000000U
#define  WDR3_HISTOGRAM_SHIFT1_SHIFT 24U
/*! Slice: wdr3_histogram_shift2:*/
#define  WDR3_HISTOGRAM_SHIFT2
#define  WDR3_HISTOGRAM_SHIFT2_MASK 0x00F00000U
#define  WDR3_HISTOGRAM_SHIFT2_SHIFT 20U
/*! Slice: wdr3_histogram_shift3:*/
#define  WDR3_HISTOGRAM_SHIFT3
#define  WDR3_HISTOGRAM_SHIFT3_MASK 0x000F0000U
#define  WDR3_HISTOGRAM_SHIFT3_SHIFT 16U
/*! Slice: wdr3_histogram_shift4:*/
#define  WDR3_HISTOGRAM_SHIFT4
#define  WDR3_HISTOGRAM_SHIFT4_MASK 0x0000F000U
#define  WDR3_HISTOGRAM_SHIFT4_SHIFT 12U
/*! Slice: wdr3_histogram_shift5:*/
#define  WDR3_HISTOGRAM_SHIFT5
#define  WDR3_HISTOGRAM_SHIFT5_MASK 0x00000F00U
#define  WDR3_HISTOGRAM_SHIFT5_SHIFT 8U
/*! Slice: wdr3_histogram_shift6:*/
#define  WDR3_HISTOGRAM_SHIFT6
#define  WDR3_HISTOGRAM_SHIFT6_MASK 0x000000F0U
#define  WDR3_HISTOGRAM_SHIFT6_SHIFT 4U
/*! Slice: wdr3_histogram_shift7:*/
#define  WDR3_HISTOGRAM_SHIFT7
#define  WDR3_HISTOGRAM_SHIFT7_MASK 0x0000000FU
#define  WDR3_HISTOGRAM_SHIFT7_SHIFT 0U
/*! Register: isp_wdr3_shift_1  (0x00003604)*/
/*! Slice: wdr3_histogram_shift8:*/
#define  WDR3_HISTOGRAM_SHIFT8
#define  WDR3_HISTOGRAM_SHIFT8_MASK 0x00F00000U
#define  WDR3_HISTOGRAM_SHIFT8_SHIFT 20U
/*! Slice: wdr3_histogram_shift9:*/
#define  WDR3_HISTOGRAM_SHIFT9
#define  WDR3_HISTOGRAM_SHIFT9_MASK 0x000F0000U
#define  WDR3_HISTOGRAM_SHIFT9_SHIFT 16U
/*! Slice: wdr3_histogram_shift10:*/
#define  WDR3_HISTOGRAM_SHIFT10
#define  WDR3_HISTOGRAM_SHIFT10_MASK 0x0000F000U
#define  WDR3_HISTOGRAM_SHIFT10_SHIFT 12U
/*! Slice: wdr3_histogram_shift11:*/
#define  WDR3_HISTOGRAM_SHIFT11
#define  WDR3_HISTOGRAM_SHIFT11_MASK 0x00000F00U
#define  WDR3_HISTOGRAM_SHIFT11_SHIFT 8U
/*! Slice: wdr3_histogram_shift12:*/
#define  WDR3_HISTOGRAM_SHIFT12
#define  WDR3_HISTOGRAM_SHIFT12_MASK 0x000000F0U
#define  WDR3_HISTOGRAM_SHIFT12_SHIFT 4U
/*! Slice: wdr3_histogram_shift13:*/
#define  WDR3_HISTOGRAM_SHIFT13
#define  WDR3_HISTOGRAM_SHIFT13_MASK 0x0000000FU
#define  WDR3_HISTOGRAM_SHIFT13_SHIFT 0U
/*! Register: isp_wdr3_strength_shd          (0x00003608)*/
/*! Slice: wdr3_total_strength_shd:*/
#define  WDR3_TOTAL_STRENGTH_SHD
#define  WDR3_TOTAL_STRENGTH_SHD_MASK 0xFF000000U
#define  WDR3_TOTAL_STRENGTH_SHD_SHIFT 24U
/*! Slice: wdr3_local_strength_shd:*/
#define  WDR3_LOCAL_STRENGTH_SHD
#define  WDR3_LOCAL_STRENGTH_SHD_MASK 0x00FF0000U
#define  WDR3_LOCAL_STRENGTH_SHD_SHIFT 16U
/*! Slice: wdr3_global_strength_shd:*/
#define  WDR3_GLOBAL_STRENGTH_SHD
#define  WDR3_GLOBAL_STRENGTH_SHD_MASK 0x0000FF00U
#define  WDR3_GLOBAL_STRENGTH_SHD_SHIFT 8U
/*! Slice: wdr3_maximum_gain_shd:*/
#define  WDR3_MAXIMUM_GAIN_SHD
#define  WDR3_MAXIMUM_GAIN_SHD_MASK 0x000000FFU
#define  WDR3_MAXIMUM_GAIN_SHD_SHIFT 0U
/*! Register: isp_wdr3_pixel_slope_shd  (0x0000360C)*/
/*! Slice: wdr3_pixel_merge_slope_shd:*/
#define  WDR3_PIXEL_MERGE_SLOPE_SHD
#define  WDR3_PIXEL_MERGE_SLOPE_SHD_MASK 0xFF000000U
#define  WDR3_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U
/*! Slice: wdr3_pixel_merge_base_shd:*/
#define  WDR3_PIXEL_MERGE_BASE_SHD
#define  WDR3_PIXEL_MERGE_BASE_SHD_MASK 0x00FF0000U
#define  WDR3_PIXEL_MERGE_BASE_SHD_SHIFT 16U
/*! Slice: wdr3_pixel_adjust_slope_shd:*/
#define  WDR3_PIXEL_ADJUST_SLOPE_SHD
#define  WDR3_PIXEL_ADJUST_SLOPE_SHD_MASK 0x0000FF00U
#define  WDR3_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U
/*! Slice: wdr3_pixel_adjust_base_shd:*/
#define  WDR3_PIXEL_ADJUST_BASE_SHD
#define  WDR3_PIXEL_ADJUST_BASE_SHD_MASK 0x000000FFU
#define  WDR3_PIXEL_ADJUST_BASE_SHD_SHIFT 0U
/*! Register: isp_wdr3_entropy_slope_shd  (0x00003610)*/
/*! Slice: wdr3_entropy_slope_shd:*/
#define  WDR3_ENTROPY_SLOPE_SHD
#define  WDR3_ENTROPY_SLOPE_SHD_MASK 0x000FFC00U
#define  WDR3_ENTROPY_SLOPE_SHD_SHIFT 10U
/*! Slice: wdr3_entropy_base_shd:*/
#define  WDR3_ENTROPY_BASE_SHD
#define  WDR3_ENTROPY_BASE_SHD_MASK 0x000003FFU
#define  WDR3_ENTROPY_BASE_SHD_SHIFT 0U
/* TPG */
/*! Register: isp_tpg_ctrl  (0x00000700)*/
/*! Slice: tpg_resolution:*/
#define  TPG_RESOLUTION
#define  TPG_RESOLUTION_MASK 0x00000C00U
#define  TPG_RESOLUTION_SHIFT 10U
/*! Slice: tpg_max_sync:*/
#define  TPG_MAX_SYNC
#define  TPG_MAX_SYNC_MASK 0x00000200U
#define  TPG_MAX_SYNC_SHIFT 9U
/*! Slice: tpg_def_sync:*/
#define  TPG_DEF_SYNC
#define  TPG_DEF_SYNC_MASK 0x00000100U
#define  TPG_DEF_SYNC_SHIFT 8U
/*! Slice: tpg_color_depth:*/
#define  TPG_COLOR_DEPTH
#define  TPG_COLOR_DEPTH_MASK 0x000000C0U
#define  TPG_COLOR_DEPTH_SHIFT 6U
/*! Slice: tpg_cfa_pat:*/
#define  TPG_CFA_PAT
#define  TPG_CFA_PAT_MASK 0x00000030U
#define  TPG_CFA_PAT_SHIFT 4U
/*! Slice: tpg_img_num:*/
#define  TPG_IMG_NUM
#define  TPG_IMG_NUM_MASK 0x0000000EU
#define  TPG_IMG_NUM_SHIFT 1U
/*! Slice: tpg_frame_num:*/
#define  TPG_FRAME_NUM
#define  TPG_FRAME_NUM_MASK 0xFFFF0000U
#define  TPG_FRAME_NUM_SHIFT 16U
/*! Slice: tpg_enable:*/
#define  TPG_ENABLE
#define  TPG_ENABLE_MASK 0x00000001U
#define  TPG_ENABLE_SHIFT 0U
/*! Register: isp_tpg_total_in  (0x00000704)*/
/*! Slice: tpg_htotal_in:*/
#define  TPG_HTOTAL_IN
#define  TPG_HTOTAL_IN_MASK 0x0FFFC000U
#define  TPG_HTOTAL_IN_SHIFT 14U
/*! Slice: tpg_vtotal_in:*/
#define  TPG_VTOTAL_IN
#define  TPG_VTOTAL_IN_MASK 0x00003FFFU
#define  TPG_VTOTAL_IN_SHIFT 0U
/*! Register: isp_tpg_act_in  (0x00000708)*/
/*! Slice: tpg_hact_in:*/
#define  TPG_HACT_IN
#define  TPG_HACT_IN_MASK 0x0FFFC000U
#define  TPG_HACT_IN_SHIFT 14U
/*! Slice: tpg_vact_in:*/
#define  TPG_VACT_IN
#define  TPG_VACT_IN_MASK 0x00003FFFU
#define  TPG_VACT_IN_SHIFT 0U
/*! Register: isp_tpg_fp_in  (0x0000070C)*/
/*! Slice: tpg_fp_h_in:*/
#define  TPG_FP_H_IN
#define  TPG_FP_H_IN_MASK 0x0FFFC000U
#define  TPG_FP_H_IN_SHIFT 14U
/*! Slice: tpg_fp_v_in:*/
#define  TPG_FP_V_IN
#define  TPG_FP_V_IN_MASK 0x00003FFFU
#define  TPG_FP_V_IN_SHIFT 0U
/*! Register: isp_tpg_bp_in  (0x00000710)*/
/*! Slice: tpg_bp_h_in:*/
#define  TPG_BP_H_IN
#define  TPG_BP_H_IN_MASK 0x0FFFC000U
#define  TPG_BP_H_IN_SHIFT 14U
/*! Slice: tpg_bp_v_in:*/
#define  TPG_BP_V_IN
#define  TPG_BP_V_IN_MASK 0x00003FFFU
#define  TPG_BP_V_IN_SHIFT 0U
/*! Register: isp_tpg_w_in  (0x00000714)*/
/*! Slice: tpg_hs_w_in:*/
#define  TPG_HS_W_IN
#define  TPG_HS_W_IN_MASK 0x0FFFC000U
#define  TPG_HS_W_IN_SHIFT 14U
/*! Slice: tpg_vs_w_in:*/
#define  TPG_VS_W_IN
#define  TPG_VS_W_IN_MASK 0x00003FFFU
#define  TPG_VS_W_IN_SHIFT 0U
/*! Register: isp_tpg_gap_in  (0x00000718)*/
/*! Slice: tpg_pix_gap_in:*/
#define  TPG_PIX_GAP_IN
#define  TPG_PIX_GAP_IN_MASK 0x0FFFC000U
#define  TPG_PIX_GAP_IN_SHIFT 14U
/*! Slice: tpg_line_gap_in:*/
#define  TPG_LINE_GAP_IN
#define  TPG_LINE_GAP_IN_MASK 0x00003FFFU
#define  TPG_LINE_GAP_IN_SHIFT 0U
/*! Register: isp_tpg_gap_std_in  (0x0000071C)*/
/*! Slice: tpg_pix_gap_std_in:*/
#define  TPG_PIX_GAP_STD_IN
#define  TPG_PIX_GAP_STD_IN_MASK 0x00003FFFU
#define  TPG_PIX_GAP_STD_IN_SHIFT 0U
/*! Register: isp_tpg_random_seed  (0x00000720)*/
/*! Slice: tpg_random_seed:*/
#define  TPG_RANDOM_SEED
#define  TPG_RANDOM_SEED_MASK 0xFFFFFFFFU
#define  TPG_RANDOM_SEED_SHIFT 0U
/* MCM */
/*! Register: mcm_ctrl  (0x00001200)*/
/*! Slice: MCM_SENSOR_MEM_BYPASS:*/
#define  MCM_SENSOR_MEM_BYPASS
#define  MCM_SENSOR_MEM_BYPASS_MASK 0x00020000U
#define  MCM_SENSOR_MEM_BYPASS_SHIFT 17U
/*! Slice: MCM_G2_WR1_FMT:*/
#define  MCM_G2_WR1_FMT
#define  MCM_G2_WR1_FMT_MASK 0x0001C000U
#define  MCM_G2_WR1_FMT_SHIFT 14U
/*! Slice: MCM_G2_WR0_FMT:*/
#define  MCM_G2_WR0_FMT
#define  MCM_G2_WR0_FMT_MASK 0x00003800U
#define  MCM_G2_WR0_FMT_SHIFT 11U
/*! Slice: MCM_WR1_FMT:*/
#define  MCM_WR1_FMT
#define  MCM_WR1_FMT_MASK 0x00000700U
#define  MCM_WR1_FMT_SHIFT 8U
/*! Slice: MCM_WR0_FMT:*/
#define  MCM_WR0_FMT
#define  MCM_WR0_FMT_MASK 0x000000E0U
#define  MCM_WR0_FMT_SHIFT 5U
/*! Slice: MCM_BYPASS_SWITCH:*/
#define  MCM_BYPASS_SWITCH
#define  MCM_BYPASS_SWITCH_MASK 0x0000001EU
#define  MCM_BYPASS_SWITCH_SHIFT 1U
/*! Slice: MCM_BYPASS_EN:*/
#define  MCM_BYPASS_EN
#define  MCM_BYPASS_EN_MASK 0x00000001U
#define  MCM_BYPASS_EN_SHIFT 0U
/*! Register: mcm_size0  (0x00001204)*/
/*! Slice: MCM_HEIGHT0:*/
#define  MCM_HEIGHT0
#define  MCM_HEIGHT0_MASK 0x3FFF0000U
#define  MCM_HEIGHT0_SHIFT 16U
/*! Slice: MCM_WIDTH0:*/
#define  MCM_WIDTH0
#define  MCM_WIDTH0_MASK 0x00003FFFU
#define  MCM_WIDTH0_SHIFT 0U
/*! Register: mcm_size1  (0x00001208)*/
/*! Slice: MCM_HEIGHT1:*/
#define  MCM_HEIGHT1
#define  MCM_HEIGHT1_MASK 0x3FFF0000U
#define  MCM_HEIGHT1_SHIFT 16U
/*! Slice: MCM_WIDTH1:*/
#define  MCM_WIDTH1
#define  MCM_WIDTH1_MASK 0x00003FFFU
#define  MCM_WIDTH1_SHIFT 0U
/*! Register: mcm_rd_cfg  (0x00001280)*/
/*! Slice: MCM_RD_FMT:*/
#define  MCM_RD_FMT
#define  MCM_RD_FMT_MASK 0x00000007U
#define  MCM_RD_FMT_SHIFT 0U
/*! Register: mcm_retiming0  (0x00001284)*/
/*! Slice: MCM_VSYNC_BLANK:*/
#define  MCM_VSYNC_BLANK
#define  MCM_VSYNC_BLANK_MASK 0xFFFFFF00U
#define  MCM_VSYNC_BLANK_SHIFT 8U
/*! Slice: MCM_VSYNC_DURATION:*/
#define  MCM_VSYNC_DURATION
#define  MCM_VSYNC_DURATION_MASK 0x000000FFU
#define  MCM_VSYNC_DURATION_SHIFT 0U
/*! Register: mcm_retiming1  (0x00001288)*/
/*! Slice: MCM_HSYNC_BLANK:*/
#define  MCM_HSYNC_BLANK
#define  MCM_HSYNC_BLANK_MASK 0xFFFFFF00U
#define  MCM_HSYNC_BLANK_SHIFT 8U
/*! Slice: MCM_HSYNC_PREAMPLE:*/
#define  MCM_HSYNC_PREAMPLE
#define  MCM_HSYNC_PREAMPLE_MASK 0x000000FFU
#define  MCM_HSYNC_PREAMPLE_SHIFT 0U
/*! Register: mcm_hsync_preample_ext  (0x0000128c)*/
/*! Slice: MCM_HSYNC_PREAMPLE_EXT:*/
#define  MCM_HSYNC_PREAMPLE_EXT
#define  MCM_HSYNC_PREAMPLE_EXT_MASK 0x000FFFFFU
#define  MCM_HSYNC_PREAMPLE_EXT_SHIFT 0U
/*! Register: mcm_wr_retiming0  (0x00001290)*/
/*! Slice: MCM_WR_VSYNC_BLANK:*/
#define  MCM_WR_VSYNC_BLANK
#define  MCM_WR_VSYNC_BLANK_MASK 0xFFFFFF00U
#define  MCM_WR_VSYNC_BLANK_SHIFT 8U
/*! Slice: MCM_WR_VSYNC_DURATION:*/
#define  MCM_WR_VSYNC_DURATION
#define  MCM_WR_VSYNC_DURATION_MASK 0x000000FFU
#define  MCM_WR_VSYNC_DURATION_SHIFT 0U
/*! Register: mcm_wr_retiming1  (0x00001294)*/
/*! Slice: MCM_WR_HSYNC_BLANK:*/
#define  MCM_WR_HSYNC_BLANK
#define  MCM_WR_HSYNC_BLANK_MASK 0xFFFFFF00U
#define  MCM_WR_HSYNC_BLANK_SHIFT 8U
/*! Slice: MCM_WR_HSYNC_PREAMPLE:*/
#define  MCM_WR_HSYNC_PREAMPLE
#define  MCM_WR_HSYNC_PREAMPLE_MASK 0x000000FFU
#define  MCM_WR_HSYNC_PREAMPLE_SHIFT 0U

/*Stitching */
/*!Register: isp_stitching_ctrl   (0x00003300) */
/*!Register: isp_stitching_ctrl   (0x00003300) */
/*!Slice: regs_inform_en */
#define STITCHING_REGS_INFORM_EN
#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U
#define STITCHING_REGS_INFORM_EN_SHIFT 22U
/*!Slice: vsync_pol */
#define STITCHING_VSYNC_POL
#define STITCHING_VSYNC_POL_MASK 0x00200000U
#define STITCHING_VSYNC_POL_SHIFT 21U
/*!Slice: hsync_pol */
#define STITCHING_HSYNC_POL
#define STITCHING_HSYNC_POL_MASK 0x00100000U
#define STITCHING_HSYNC_POL_SHIFT 20U
/*!Slice: awb_gain_enable */
#define STITCHING_AWB_GAIN_ENABLE
#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U
#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U
/*!Slice: cfg_upd */
#define STITCHING_CFG_UPD
#define STITCHING_CFG_UPD_MASK 0x00040000U
#define STITCHING_CFG_UPD_SHIFT 18U
/*!Slice: gen_cfg_upd */
#define STITCHING_GEN_CFG_UPD
#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U
#define STITCHING_GEN_CFG_UPD_SHIFT 17U
/*!Slice: gen_cfg_upd_fix */
#define STITCHING_GEN_CFG_UPD_FIX
#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U
#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U
/*!Slice: bypass_select */
#define STITCHING_BYPASS_SELECT
#define STITCHING_BYPASS_SELECT_MASK 0x00006000U
#define STITCHING_BYPASS_SELECT_SHIFT 13U
/*!Slice: linear_combine_enable */
#define STITCHING_LINEAR_COMBINE_ENABLE
#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U
#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U
/*!Slice: base_frame_selection */
#define STITCHING_BASE_FRAME_SELECTION
#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U
#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U
/*!Slice: combination_mode */
#define STITCHING_COMBINATION_MODE
#define STITCHING_COMBINATION_MODE_MASK 0x00000600U
#define STITCHING_COMBINATION_MODE_SHIFT 9U
/*!Slice: channel_config_bit */
#define STITCHING_CHANNEL_CONFIG_BIT
#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U
#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U
/*!Slice: B10_enable_bit */
#define STITCHING_B10_ENABLE_BIT
#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U
#define STITCHING_B10_ENABLE_BIT_SHIFT 7U
/*!Slice: lin_enable_bit */
#define STITCHING_LIN_ENABLE_BIT
#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U
#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U
/*!Slice: VS_enable_bit */
#define STITCHING_VS_ENABLE_BIT
#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U
#define STITCHING_VS_ENABLE_BIT_SHIFT 5U
/*!Slice: bayer_pattern */
#define STITCHING_BAYER_PATTERN
#define STITCHING_BAYER_PATTERN_MASK 0x00000018U
#define STITCHING_BAYER_PATTERN_SHIFT 3U
/*!Slice: soft_reset_flag */
#define STITCHING_SOFT_RESET_FLAG
#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U
#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U
/*!Slice: mono_input_flag */
#define STITCHING_MONO_INPUT_FLAG
#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U
#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U
/*!Slice: combine_enable_bit */
#define STITCHING_COMBINE_ENABLE_BIT
#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U
#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U
/*!Slice: regs_inform_en */
#define STITCHING_REGS_INFORM_EN
#define STITCHING_REGS_INFORM_EN_MASK 0x00400000U
#define STITCHING_REGS_INFORM_EN_SHIFT 22U
/*!Slice: vsync_pol */
#define STITCHING_VSYNC_POL
#define STITCHING_VSYNC_POL_MASK 0x00200000U
#define STITCHING_VSYNC_POL_SHIFT 21U
/*!Slice: hsync_pol */
#define STITCHING_HSYNC_POL
#define STITCHING_HSYNC_POL_MASK 0x00100000U
#define STITCHING_HSYNC_POL_SHIFT 20U
/*!Slice: awb_gain_enable */
#define STITCHING_AWB_GAIN_ENABLE
#define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U
#define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U
/*!Slice: cfg_upd */
#define STITCHING_CFG_UPD
#define STITCHING_CFG_UPD_MASK 0x00040000U
#define STITCHING_CFG_UPD_SHIFT 18U
/*!Slice: gen_cfg_upd */
#define STITCHING_GEN_CFG_UPD
#define STITCHING_GEN_CFG_UPD_MASK 0x00020000U
#define STITCHING_GEN_CFG_UPD_SHIFT 17U
/*!Slice: gen_cfg_upd_fix */
#define STITCHING_GEN_CFG_UPD_FIX
#define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U
#define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U
/*!Slice: bypass_select */
#define STITCHING_BYPASS_SELECT
#define STITCHING_BYPASS_SELECT_MASK 0x00006000U
#define STITCHING_BYPASS_SELECT_SHIFT 13U
/*!Slice: linear_combine_enable */
#define STITCHING_LINEAR_COMBINE_ENABLE
#define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U
#define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U
/*!Slice: base_frame_selection */
#define STITCHING_BASE_FRAME_SELECTION
#define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U
#define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U
/*!Slice: combination_mode */
#define STITCHING_COMBINATION_MODE
#define STITCHING_COMBINATION_MODE_MASK 0x00000600U
#define STITCHING_COMBINATION_MODE_SHIFT 9U
/*!Slice: channel_config_bit */
#define STITCHING_CHANNEL_CONFIG_BIT
#define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U
#define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U
/*!Slice: B10_enable_bit */
#define STITCHING_B10_ENABLE_BIT
#define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U
#define STITCHING_B10_ENABLE_BIT_SHIFT 7U
/*!Slice: lin_enable_bit */
#define STITCHING_LIN_ENABLE_BIT
#define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U
#define STITCHING_LIN_ENABLE_BIT_SHIFT 6U
/*!Slice: VS_enable_bit */
#define STITCHING_VS_ENABLE_BIT
#define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U
#define STITCHING_VS_ENABLE_BIT_SHIFT 5U
/*!Slice: bayer_pattern */
#define STITCHING_BAYER_PATTERN
#define STITCHING_BAYER_PATTERN_MASK 0x00000018U
#define STITCHING_BAYER_PATTERN_SHIFT 3U
/*!Slice: soft_reset_flag */
#define STITCHING_SOFT_RESET_FLAG
#define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U
#define STITCHING_SOFT_RESET_FLAG_SHIFT 2U
/*!Slice: mono_input_flag */
#define STITCHING_MONO_INPUT_FLAG
#define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U
#define STITCHING_MONO_INPUT_FLAG_SHIFT 1U
/*!Slice: combine_enable_bit */
#define STITCHING_COMBINE_ENABLE_BIT
#define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U
#define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U
/*!Register: isp_stitching_frame_width   (0x00003304) */
/*!Slice: stitching_frame_width */
#define STITCHING_FRAME_WIDTH
#define STITCHING_FRAME_WIDTH_MASK 0x00003FFFU
#define STITCHING_FRAME_WIDTH_SHIFT 0U
/*!Register: isp_stitching_ctrl   (0x00003300)*/
/*!Slice: digital_gain_en_2 */
#define STITCHING_DIGITAL_GAIN_EN2
#define STITCHING_DIGITAL_GAIN_EN2_MASK 0x02000000U
#define STITCHING_DIGITAL_GAIN_EN2_SHIFT 25U
/*!Register: isp_stitching_ctrl   (0x00003300)*/
/*!Slice: digital_gain_en_1 */
#define STITCHING_DIGITAL_GAIN_EN1
#define STITCHING_DIGITAL_GAIN_EN1_MASK 0x01000000U
#define STITCHING_DIGITAL_GAIN_EN1_SHIFT 24U
/*!Register: isp_stitching_ctrl   (0x00003300)*/
/*!Slice: digital_gain_en_0 */
#define STITCHING_DIGITAL_GAIN_EN0
#define STITCHING_DIGITAL_GAIN_EN0_MASK 0x00800000U
#define STITCHING_DIGITAL_GAIN_EN0_SHIFT 23U
/*!Register: isp_stitching_ctrl   (0x00003300)*/
/*!Slice: digital_gain_en */
#define STITCHING_DIGITAL_GAIN_EN
#define STITCHING_DIGITAL_GAIN_EN_MASK 0x00400000U
#define STITCHING_DIGITAL_GAIN_EN_SHIFT 22U
/*!Register: isp_stitching_frame_height   (0x00003308) */
/*!Slice: stitching_frame_height */
#define STITCHING_FRAME_HEIGHT
#define STITCHING_FRAME_HEIGHT_MASK 0x00003FFFU
#define STITCHING_FRAME_HEIGHT_SHIFT 0U
/*Register: isp_stitching_exposure_bit    (0x0000330C) */
/*!Slice: stitching_l_bit_depth */
#define STITCHING_L_BIT_DEPTH
#define STITCHING_L_BIT_DEPTH_MASK 0xFF000000U
#define STITCHING_L_BIT_DEPTH_SHIFT 24U
/*!Slice: stitching_s_bit_depth */
#define STITCHING_S_BIT_DEPTH
#define STITCHING_S_BIT_DEPTH_MASK 0x00FF0000U
#define STITCHING_S_BIT_DEPTH_SHIFT 16U
/*!Slice: stitching_vs_bit_depth */
#define STITCHING_VS_BIT_DEPTH
#define STITCHING_VS_BIT_DEPTH_MASK 0x0000FF00U
#define STITCHING_VS_BIT_DEPTH_SHIFT 8U
/*!Slice: stitching_ls_bit_depth */
#define STITCHING_LS_BIT_DEPTH
#define STITCHING_LS_BIT_DEPTH_MASK 0x000000FFU
#define STITCHING_LS_BIT_DEPTH_SHIFT 0U
/*!Register: isp_stitching_color_weight */
/*!Slice: stitching_color_weight_2 */
#define STITCHING_COLOR_WEIGHT_2
#define STITCHING_COLOR_WEIGHT_2_MASK 0x00FF0000U
#define STITCHING_COLOR_WEIGHT_2_SHIFT 16U
/*!Slice: stitching_color_weight_1 */
#define STITCHING_COLOR_WEIGHT_1
#define STITCHING_COLOR_WEIGHT_1_MASK 0x0000FF00U
#define STITCHING_COLOR_WEIGHT_1_SHIFT 8U
/*!Slice: stitching_color_weight_0 */
#define STITCHING_COLOR_WEIGHT_0
#define STITCHING_COLOR_WEIGHT_0_MASK 0x000000FFU
#define STITCHING_COLOR_WEIGHT_0_SHIFT 0U
/*!Register: isp_stitching_bls_exp_0_a    (0x00003314)*/
/*!Slice: stitching_digital_gain_exp_0_r */
#define STITCHING_DIGITAL_GAIN_EXP_0_R
#define STITCHING_DIGITAL_GAIN_EXP_0_R_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_0_R_SHIFT 16U
/*!Register: isp_stitching_bls_exp_0_a    (0x00003314)*/
/*!Slice: stitching_bls_exp_0_a */
#define STITCHING_BLS_EXP_0_A
#define STITCHING_BLS_EXP_0_A_MASK 0x000000FFFU
#define STITCHING_BLS_EXP_0_A_SHIFT 0U
/*!Register: isp_stitching_bls_exp_0_b    (0x00003318)*/
/*!Slice: stitching_digital_gain_exp_0_g */
#define STITCHING_DIGITAL_GAIN_EXP_0_G
#define STITCHING_DIGITAL_GAIN_EXP_0_G_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_0_G_SHIFT 16U
/*!Register: isp_stitching_bls_exp_0_b    (0x00003318)*/
/*!Slice: stitching_bls_exp_0_b */
#define STITCHING_BLS_EXP_0_B
#define STITCHING_BLS_EXP_0_B_MASK 0x000000FFFU
#define STITCHING_BLS_EXP_0_B_SHIFT 0U
/*!Register: isp_stitching_bls_exp_0_c    (0x0000331c)*/
/*!Slice: stitching_digital_gain_exp_0_gr */
#define STITCHING_DIGITAL_GAIN_EXP_0_GR
#define STITCHING_DIGITAL_GAIN_EXP_0_GR_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_0_GR_SHIFT 16U
/*!Register: isp_stitching_bls_exp_0_c     (0x0000331C)*/
/*!Slice: stitching_bls_exp_0_c */
#define STITCHING_BLS_EXP_0_C
#define STITCHING_BLS_EXP_0_C_MASK 0x000000FFFU
#define STITCHING_BLS_EXP_0_C_SHIFT 0U
/*!Register: isp_stitching_bls_exp_0_d    (0x00003320)*/
/*!Slice: stitching_digital_gain_exp_0_gb */
#define STITCHING_DIGITAL_GAIN_EXP_0_GB
#define STITCHING_DIGITAL_GAIN_EXP_0_GB_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_0_GB_SHIFT 16U
/*!Register: isp_stitching_bls_exp_0_d     (0x00003320)*/
/*!Slice: stitching_bls_exp_0_d */
#define STITCHING_BLS_EXP_0_D
#define STITCHING_BLS_EXP_0_D_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_0_D_SHIFT 0U
/*!Register: isp_stitching_bls_exp_1_a    (0x00003324)*/
/*!Slice: stitching_digital_gain_exp_1_r */
#define STITCHING_DIGITAL_GAIN_EXP_1_R
#define STITCHING_DIGITAL_GAIN_EXP_1_R_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_1_R_SHIFT 16U
/*!Register: isp_stitching_bls_exp_1_a     (0x00003324)*/
/*!Slice: stitching_bls_exp_1_a */
#define STITCHING_BLS_EXP_1_A
#define STITCHING_BLS_EXP_1_A_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_1_A_SHIFT 0U
/*!Register: isp_stitching_bls_exp_1_b    (0x00003328)*/
/*!Slice: stitching_digital_gain_exp_1_g */
#define STITCHING_DIGITAL_GAIN_EXP_1_G
#define STITCHING_DIGITAL_GAIN_EXP_1_G_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_1_G_SHIFT 16U
/*!Register: isp_stitching_bls_exp_1_b     (0x00003328)*/
/*!Slice: stitching_bls_exp_1_b */
#define STITCHING_BLS_EXP_1_B
#define STITCHING_BLS_EXP_1_B_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_1_B_SHIFT 0U
/*!Register: isp_stitching_bls_exp_1_c   (0x0000332c)*/
/*!Slice: stitching_digital_gain_exp_1_gr */
#define STITCHING_DIGITAL_GAIN_EXP_1_GR
#define STITCHING_DIGITAL_GAIN_EXP_1_GR_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_1_GR_SHIFT 16U
/*!Register: isp_stitching_bls_exp_1_c      (0x0000332C)*/
/*!Slice: stitching_bls_exp_1_c */
#define STITCHING_BLS_EXP_1_C
#define STITCHING_BLS_EXP_1_C_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_1_C_SHIFT 0U
/*!Register: isp_stitching_bls_exp_1_d    (0x00003330)*/
/*!Slice: stitching_digital_gain_exp_1_gb */
#define STITCHING_DIGITAL_GAIN_EXP_1_GB
#define STITCHING_DIGITAL_GAIN_EXP_1_GB_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_1_GB_SHIFT 16U
/*!Register: isp_stitching_bls_exp_1_d      (0x00003330)*/
/*!Slice: stitching_bls_exp_1_d */
#define STITCHING_BLS_EXP_1_D
#define STITCHING_BLS_EXP_1_D_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_1_D_SHIFT 0U
/*!Register: isp_stitching_bls_exp_2_a    (0x00003334)*/
/*!Slice: stitching_digital_gain_exp_2_r */
#define STITCHING_DIGITAL_GAIN_EXP_2_R
#define STITCHING_DIGITAL_GAIN_EXP_2_R_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_2_R_SHIFT 16U
/*!Register: isp_stitching_bls_exp_2_a      (0x00003334)*/
/*!Slice: stitching_bls_exp_2_a */
#define STITCHING_BLS_EXP_2_A
#define STITCHING_BLS_EXP_2_A_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_2_A_SHIFT 0U
/*!Register: isp_stitching_bls_exp_2_b    (0x00003338)*/
/*!Slice: stitching_digital_gain_exp_2_g */
#define STITCHING_DIGITAL_GAIN_EXP_2_G
#define STITCHING_DIGITAL_GAIN_EXP_2_G_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_2_G_SHIFT 16U
/*!Register: isp_stitching_bls_exp_2_b      (0x00003338)*/
/*!Slice: stitching_bls_exp_2_b */
#define STITCHING_BLS_EXP_2_B
#define STITCHING_BLS_EXP_2_B_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_2_B_SHIFT 0U
/*!Register: isp_stitching_bls_exp_2_c    (0x0000333c)*/
/*!Slice: stitching_digital_gain_exp_2_gr */
#define STITCHING_DIGITAL_GAIN_EXP_2_GR
#define STITCHING_DIGITAL_GAIN_EXP_2_GR_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_2_GR_SHIFT 16U
/*!Register: isp_stitching_bls_exp_2_c       (0x0000333C)*/
/*!Slice: stitching_bls_exp_2_c */
#define STITCHING_BLS_EXP_2_C
#define STITCHING_BLS_EXP_2_C_MASK 0x0000FFFU
#define STITCHING_BLS_EXP_2_C_SHIFT 0U
/*!Register: isp_stitching_bls_exp_2_d    (0x00003340)*/
/*!Slice: stitching_digital_gain_exp_2_gb */
#define STITCHING_DIGITAL_GAIN_EXP_2_GB
#define STITCHING_DIGITAL_GAIN_EXP_2_GB_MASK 0XFFFFF0000U
#define STITCHING_DIGITAL_GAIN_EXP_2_GB_SHIFT 16U
/*!Register: isp_stitching_bls_exp_2_d        (0x00003340)*/
/*!Slice: stitching_bls_exp_2_d */
#define STITCHING_BLS_EXP_2_D
#define STITCHING_BLS_EXP_2_D_MASK 0x000000FFFU
#define STITCHING_BLS_EXP_2_D_SHIFT 0U
/*!Reister: isp_stitching_ratio_ls     (0x00003344)*/
/*!Slice: stitching_ratio_long_short_1 */
#define STITCHING_RATIO_LONG_SHORT_1
#define STITCHING_RATIO_LONG_SHORT_1_MASK 0x00FFF000U
#define STITCHING_RATIO_LONG_SHORT_1_SHIFT 12U
/*!Slice: stitching_ratio_long_short_0 */
#define STITCHING_RATIO_LONG_SHORT_0
#define STITCHING_RATIO_LONG_SHORT_0_MASK 0x00000FFFU
#define STITCHING_RATIO_LONG_SHORT_0_SHIFT 0U
/*!Reister: isp_stitching_ratio_vs     (0x00003348) */
/*!Slice: stitching_ratio_veryshort_short_1 */
#define STITCHING_RATIO_VERYSHORT_SHORT_1
#define STITCHING_RATIO_VERYSHORT_SHORT_1_MASK 0x00FFF000U
#define STITCHING_RATIO_VERYSHORT_SHORT_1_SHIFT 12U
/*!Slice: stitching_ratio_veryshort_short_0 */
#define STITCHING_RATIO_VERYSHORT_SHORT_0
#define STITCHING_RATIO_VERYSHORT_SHORT_0_MASK 0x00000FFFU
#define STITCHING_RATIO_VERYSHORT_SHORT_0_SHIFT 0U
/*!Reister: isp_stitching_ratio_ls_shd     (0x0000334C) */
/*!Slice: stitching_ratio_long_short_shd_1 */
#define STITCHING_RATIO_LONG_SHORT_SHD_1
#define STITCHING_RATIO_LONG_SHORT_SHD_1_MASK 0x00FFF000U
#define STITCHING_RATIO_LONG_SHORT_SHD_1_SHIFT 12U
/*!Slice: stitching_ratio_long_short_shd_0 */
#define STITCHING_RATIO_LONG_SHORT_SHD_0
#define STITCHING_RATIO_LONG_SHORT_SHD_0_MASK 0x00000FFFU
#define STITCHING_RATIO_LONG_SHORT_SHD_0_SHIFT 0U
/*!Reister: isp_stitching_ratio_vs_shd     (0x00003350) */
/*!Slice: stitching_ratio_veryshort_short_shd_1 */
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_MASK 0x00FFF000U
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_SHIFT 12U
/*!Slice: stitching_ratio_veryshort_short_shd_0 */
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_MASK 0x00000FFFU
#define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_SHIFT 0U
/*!Register: isp_sitching_trans_range_linear     (0x00003354) */
/*!Slice: stitching_trans_range_start_linear */
#define STITCHING_TRANS_RANGE_START_LINEAR
#define STITCHING_TRANS_RANGE_START_LINEAR_MASK 0xFFFF0000U
#define STITCHING_TRANS_RANGE_START_LINEAR_SHIFT 16U
/*!Slice:stitching_trans_range_norm_factor_mul_linear */
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_MASK 0x0000FFFFU
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_SHIFT 0U
/*!Register: isp_sitching_trans_range_nonlinear     (0x00003358) */
/*!Slice: stitching_trans_range_start_nonlinear */
#define STITCHING_TRANS_RANGE_START_NONLINEAR
#define STITCHING_TRANS_RANGE_START_NONLINEAR_MASK 0xFFFF0000U
#define STITCHING_TRANS_RANGE_START_NONLINEAR_SHIFT 16U
/*!Slice:stitching_trans_range_norm_factor_mul_nonlinear */
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_MASK 0x0000FFFFU
#define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_SHIFT 0U
/*!Register: isp_stitching_sat_level     (0x0000335C) */
//Version-11 Stitching only support one type extend bit
//!Slice: stitching_short_vs_extend_bit
#define STITCHING_SHORT_EXTEND_BIT
#define STITCHING_SHORT_EXTEND_BIT_MASK 0xFF000000U
#define STITCHING_SHORT_EXTEND_BIT_SHIFT 24U
//Version-12 Stitching support two type extend bit
//!Slice: stitching_short_ls_extend_bit
#define STITCHING_SHORT_LS_EXTEND_BIT
#define STITCHING_SHORT_LS_EXTEND_BIT_MASK 0xF0000000U
#define STITCHING_SHORT_LS_EXTEND_BIT_SHIFT 28U
//!Slice: stitching_short_vs_extend_bit
#define STITCHING_SHORT_VS_EXTEND_BIT
#define STITCHING_SHORT_VS_EXTEND_BIT_MASK 0x0F000000U
#define STITCHING_SHORT_VS_EXTEND_BIT_SHIFT 24U
/*!Slice: stitching_veryshort_valid_thresh */
#define STITCHING_VERYSHORT_VALID_THRESH
#define STITCHING_VERYSHORT_VALID_THRESH_MASK 0x00FFF000U
#define STITCHING_VERYSHORT_VALID_THRESH_SHIFT 12U
/*!Slice: stitching_veryshort_offset_val */
#define STITCHING_VERYSHORT_OFFSET_VAL
#define STITCHING_VERYSHORT_OFFSET_VAL_MASK 0x00000FFFU
#define STITCHING_VERYSHORT_OFFSET_VAL_SHIFT 0U
/*!Register: isp_stitching_long_exposure        (0x00003360) */
/*!Slice: stitching_long_exposure_time */
#define STITCHING_LONG_EXPOSURE_TIME
#define STITCHING_LONG_EXPOSURE_TIME_MASK 0x00000FFFU
#define STITCHING_LONG_EXPOSURE_TIME_SHIFT 0U
/*!Register: isp_stitching_short_exposure       (0x00003364) */
/*!Slice: stitching_short_exposure_time */
#define STITCHING_SHORT_EXPOSURE_TIME
#define STITCHING_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU
#define STITCHING_SHORT_EXPOSURE_TIME_SHIFT 0U
/*!Register: isp_stitching_very_short_exposure  (0x00003368) */
/*!Slice: stitching_very_short_exposure_time */
#define STITCHING_VERY_SHORT_EXPOSURE_TIME
#define STITCHING_VERY_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU
#define STITCHING_VERY_SHORT_EXPOSURE_TIME_SHIFT 0U
/*!Register: isp_stitching_hdr_mode     (0x0000336C) */
/*!Slice: stitching_hdr_mode */
#define STITCHING_HDR_MODE_BIT
#define STITCHING_HDR_MODE_BIT_MASK 0x0000000FU
#define STITCHING_HDR_MODE_BIT_SHIFT 0U
/*!Register: isp_stitching_out_hblank     (0x00003370) */
/*!Slice: stitching_dummy_s_hblank */
#define STITCHING_DUMMY_S_HBLANK
#define STITCHING_DUMMY_S_HBLANK_MASK 0xFFFF0000U
#define STITCHING_DUMMY_S_HBLANK_SHIFT 16U
/*!Slice: stitching_out_hblank */
#define STITCHING_OUT_HBLANK
#define STITCHING_OUT_HBLANK_MASK 0x00003FFFU
#define STITCHING_OUT_HBLANK_SHIFT 0U
/*!Register: isp_stitching_out_vblank     (0x00003374) */
/*!Slice: stitching_dummy_vs_hblank */
#define STITCHING_DUMMY_VS_HBLANK
#define STITCHING_DUMMY_VS_HBLANK_MASK 0xFFFF0000U
#define STITCHING_DUMMY_VS_HBLANK_SHIFT 16U
/*!Slice: stitching_out_vblank */
#define STITCHING_OUT_VBLANK
#define STITCHING_OUT_VBLANK_MASK 0x00000FFFU
#define STITCHING_OUT_VBLANK_SHIFT 0U
/*!Register:ISP_STITCHING_OUT_HBLANK         (0x00003370)*/
/* Slice:stiching_dummy_hblank */
#define STITCHING_DUMMY_HBLANK
#define STITCHING_DUMMY_HBLANK_MASK 0xFFFF0000U
#define STITCHING_DUMMY_HBLANK_SHIFT 16U
/*!Register: isp_stitching_interrupt_status     (0x00003378) */
/*!Slice: stitching_interrupt_status */
#define STITCHING_INTERRUPT_STATUS
#define STITCHING_INTERRUPT_STATUS_MASK 0x00000007U
#define STITCHING_INTERRUPT_STATUS_SHIFT 0U
/*!Register: isp_stitching_compress_x0    (0x0000337C) */
/*!Slice: stitching_compress_x0 */
#define STITCHING_COMPRESS_X0
#define STITCHING_COMPRESS_X0_MASK 0x000003FFU
#define STITCHING_COMPRESS_X0_SHIFT 0U
/*!Register: isp_stitching_compress_lut_0    (0x000033A0) */
/*!Slice: stitching_compress_lut_2 */
#define STITCHING_COMPRESS_LUT_2
#define STITCHING_COMPRESS_LUT_2_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_2_SHIFT 20U
/*!Slice: stitching_compress_lut_1 */
#define STITCHING_COMPRESS_LUT_1
#define STITCHING_COMPRESS_LUT_1_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_1_SHIFT 10U
/*!Slice: stitching_compress_lut_0 */
#define STITCHING_COMPRESS_LUT_0
#define STITCHING_COMPRESS_LUT_0_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_0_SHIFT 0U
/*!Register: isp_stitching_compress_lut_1     (0x000033A4) */
/*!Slice: stitching_compress_lut_5 */
#define STITCHING_COMPRESS_LUT_5
#define STITCHING_COMPRESS_LUT_5_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_5_SHIFT 20U
/*!Slice: stitching_compress_lut_4 */
#define STITCHING_COMPRESS_LUT_4
#define STITCHING_COMPRESS_LUT_4_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_4_SHIFT 10U
/*!Slice: stitching_compress_lut_3 */
#define STITCHING_COMPRESS_LUT_3
#define STITCHING_COMPRESS_LUT_3_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_3_SHIFT 0U
/*!Register: isp_stitching_compress_lut_2     (0x000033A8) */
/*!Slice: stitching_compress_lut_8 */
#define STITCHING_COMPRESS_LUT_8
#define STITCHING_COMPRESS_LUT_8_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_8_SHIFT 20U
/*!Slice: stitching_compress_lut_7 */
#define STITCHING_COMPRESS_LUT_7
#define STITCHING_COMPRESS_LUT_7_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_7_SHIFT 10U
/*!Slice: stitching_compress_lut_6 */
#define STITCHING_COMPRESS_LUT_6
#define STITCHING_COMPRESS_LUT_6_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_6_SHIFT 0U
/*!Register: isp_stitching_compress_lut_3     (0x000033AC) */
/*!Slice: stitching_compress_lut_11 */
#define STITCHING_COMPRESS_LUT_11
#define STITCHING_COMPRESS_LUT_11_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_11_SHIFT 20U
/*!Slice: stitching_compress_lut_10 */
#define STITCHING_COMPRESS_LUT_10
#define STITCHING_COMPRESS_LUT_10_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_10_SHIFT 10U
/*!Slice: stitching_compress_lut_9 */
#define STITCHING_COMPRESS_LUT_9
#define STITCHING_COMPRESS_LUT_9_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_9_SHIFT 0U
/*!Register: isp_stitching_compress_lut_4     (0x000033B0) */
/*!Slice: stitching_compress_lut_14 */
#define STITCHING_COMPRESS_LUT_14
#define STITCHING_COMPRESS_LUT_14_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_14_SHIFT 20U
/*!Slice: stitching_compress_lut_13 */
#define STITCHING_COMPRESS_LUT_13
#define STITCHING_COMPRESS_LUT_13_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_13_SHIFT 10U
/*!Slice: stitching_compress_lut_12 */
#define STITCHING_COMPRESS_LUT_12
#define STITCHING_COMPRESS_LUT_12_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_12_SHIFT 0U
/*/*!Register: isp_stitching_compress_lut_shd_0     (0x000033B4) */
/*!Slice: stitching_compress_lut_shd_2 */
#define STITCHING_COMPRESS_LUT_SHD_2
#define STITCHING_COMPRESS_LUT_SHD_2_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_SHD_2_SHIFT 20U
/*!Slice: stitching_compress_lut_shd_1 */
#define STITCHING_COMPRESS_LUT_SHD_1
#define STITCHING_COMPRESS_LUT_SHD_1_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_SHD_1_SHIFT 10U
/*!Slice: stitching_compress_lut_shd_0 */
#define STITCHING_COMPRESS_LUT_SHD_0
#define STITCHING_COMPRESS_LUT_SHD_0_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_SHD_0_SHIFT 0U
/*!Register: isp_stitching_compress_lut_shd_1     (0x000033B8) */
/*!Slice: stitching_compress_lut_shd_5 */
#define STITCHING_COMPRESS_LUT_SHD_5
#define STITCHING_COMPRESS_LUT_SHD_5_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_SHD_5_SHIFT 20U
/*!Slice: stitching_compress_lut_shd_4 */
#define STITCHING_COMPRESS_LUT_SHD_4
#define STITCHING_COMPRESS_LUT_SHD_4_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_SHD_4_SHIFT 10U
/*!Slice: stitching_compress_lut_shd_3 */
#define STITCHING_COMPRESS_LUT_SHD_3
#define STITCHING_COMPRESS_LUT_SHD_3_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_SHD_3_SHIFT 0U
/*!Register: isp_stitching_compress_lut_shd_2     (0x000033BC) */
/*!Slice: stitching_compress_lut_shd_8 */
#define STITCHING_COMPRESS_LUT_SHD_8
#define STITCHING_COMPRESS_LUT_SHD_8_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_SHD_8_SHIFT 20U
/*!Slice: stitching_compress_lut_shd_7 */
#define STITCHING_COMPRESS_LUT_SHD_7
#define STITCHING_COMPRESS_LUT_SHD_7_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_SHD_7_SHIFT 10U
/*!Slice: stitching_compress_lut_shd_6 */
#define STITCHING_COMPRESS_LUT_SHD_6
#define STITCHING_COMPRESS_LUT_SHD_6_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_SHD_6_SHIFT 0U
/*!Register: isp_stitching_compress_lut_shd_3     (0x000033C0) */
/*!Slice: stitching_compress_lut_shd_11 */
#define STITCHING_COMPRESS_LUT_SHD_11
#define STITCHING_COMPRESS_LUT_SHD_11_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_SHD_11_SHIFT 20U
/*!Slice: stitching_compress_lut_shd_10 */
#define STITCHING_COMPRESS_LUT_SHD_10
#define STITCHING_COMPRESS_LUT_SHD_10_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_SHD_10_SHIFT 10U
/*!Slice: stitching_compress_lut_shd_9 */
#define STITCHING_COMPRESS_LUT_SHD_9
#define STITCHING_COMPRESS_LUT_SHD_9_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_SHD_9_SHIFT 0U
/*!Register: isp_stitching_compress_lut_shd_4     (0x000033C4) */
/*!Slice: stitching_compress_lut_shd_14 */
#define STITCHING_COMPRESS_LUT_SHD_14
#define STITCHING_COMPRESS_LUT_SHD_14_MASK 0x3FF00000U
#define STITCHING_COMPRESS_LUT_SHD_14_SHIFT 20U
/*!Slice: stitching_compress_lut_shd_13 */
#define STITCHING_COMPRESS_LUT_SHD_13
#define STITCHING_COMPRESS_LUT_SHD_13_MASK 0x000FFC00U
#define STITCHING_COMPRESS_LUT_SHD_13_SHIFT 10U
/*!Slice: stitching_compress_lut_shd_12 */
#define STITCHING_COMPRESS_LUT_SHD_12
#define STITCHING_COMPRESS_LUT_SHD_12_MASK 0x000003FFU
#define STITCHING_COMPRESS_LUT_SHD_12_SHIFT 0U
/*!Register:isp_stitching_exp0_awb_gain_g         (0x000033C8) */
/*Slice:stiching_exp0_awb_gain_gr */
#define STITCHING_EXP0_AWB_GAIN_GR
#define STITCHING_EXP0_AWB_GAIN_GR_MASK 0x03FF0000U
#define STITCHING_EXP0_AWB_GAIN_GR_SHIFT 16U
/*Slice:stiching_exp0_awb_gain_gb */
#define STITCHING_EXP0_AWB_GAIN_GB
#define STITCHING_EXP0_AWB_GAIN_GB_MASK 0x000003FFU
#define STITCHING_EXP0_AWB_GAIN_GB_SHIFT 0U
/*Slice:stiching_exp0_awb_gain_r */
#define STITCHING_EXP0_AWB_GAIN_R
#define STITCHING_EXP0_AWB_GAIN_R_MASK 0x03FF0000U
#define STITCHING_EXP0_AWB_GAIN_R_SHIFT 16U
/*Slice:stiching_exp0_awb_gain_b */
#define STITCHING_EXP0_AWB_GAIN_B
#define STITCHING_EXP0_AWB_GAIN_B_MASK 0x000003FFU
#define STITCHING_EXP0_AWB_GAIN_B_SHIFT 0U
/*Slice:stiching_exp1_awb_gain_gr */
#define STITCHING_EXP1_AWB_GAIN_GR
#define STITCHING_EXP1_AWB_GAIN_GR_MASK 0x03FF0000U
#define STITCHING_EXP1_AWB_GAIN_GR_SHIFT 16U
/*Slice:stiching_exp1_awb_gain_gb */
#define STITCHING_EXP1_AWB_GAIN_GB
#define STITCHING_EXP1_AWB_GAIN_GB_MASK 0x000003FFU
#define STITCHING_EXP1_AWB_GAIN_GB_SHIFT 0U
/*Slice:stiching_exp1_awb_gain_r */
#define STITCHING_EXP1_AWB_GAIN_R
#define STITCHING_EXP1_AWB_GAIN_R_MASK 0x03FF0000U
#define STITCHING_EXP1_AWB_GAIN_R_SHIFT 16U
/*Slice:stiching_exp1_awb_gain_b */
#define STITCHING_EXP1_AWB_GAIN_B
#define STITCHING_EXP1_AWB_GAIN_B_MASK 0x000003FFU
#define STITCHING_EXP1_AWB_GAIN_B_SHIFT 0U
/*Slice:stiching_exp2_awb_gain_gr */
#define STITCHING_EXP2_AWB_GAIN_GR
#define STITCHING_EXP2_AWB_GAIN_GR_MASK 0x03FF0000U
#define STITCHING_EXP2_AWB_GAIN_GR_SHIFT 16U
/*Slice:stiching_exp2_awb_gain_gb */
#define STITCHING_EXP2_AWB_GAIN_GB
#define STITCHING_EXP2_AWB_GAIN_GB_MASK 0x000003FFU
#define STITCHING_EXP2_AWB_GAIN_GB_SHIFT 0U
/*Slice:stiching_exp0_awb_gain_r */
#define STITCHING_EXP2_AWB_GAIN_R
#define STITCHING_EXP2_AWB_GAIN_R_MASK 0x03FF0000U
#define STITCHING_EXP2_AWB_GAIN_R_SHIFT 16U
/*Slice:stiching_exp0_awb_gain_b */
#define STITCHING_EXP2_AWB_GAIN_B
#define STITCHING_EXP2_AWB_GAIN_B_MASK 0x000003FFU
#define STITCHING_EXP2_AWB_GAIN_B_SHIFT 0U
/*Register: isp_stitching_long_sat_params */
/*!Slice: stitching_long_sat_thresh */
#define STITCHING_LONG_SAT_THRESH
#define STITCHING_LONG_SAT_THRESH_MASK 0x00FFF000U
#define STITCHING_LONG_SAT_THRESH_SHIFT 12U
/*!Slice: stitching_long_sat_combine_weight */
#define STITCHING_LONG_SAT_COMBINE_WEIGHT
#define STITCHING_LONG_SAT_COMBINE_WEIGHT_MASK 0x000001FF
#define STITCHING_LONG_SAT_COMBINE_WEIGHT_SHIFT 0U
//!Register: isp_stitching_bls_exp_out_0                (0x000033F8)
//! Slice: stitching_bls_exp_out_a:
#define  STITCHING_BLS_EXP_OUT_A
#define  STITCHING_BLS_EXP_OUT_A_MASK 0x0FFF0000U
#define  STITCHING_BLS_EXP_OUT_A_SHIFT 16U
//! Slice: stitching_bls_exp_out_b:
#define  STITCHING_BLS_EXP_OUT_B
#define  STITCHING_BLS_EXP_OUT_B_MASK 0x00000FFFU
#define  STITCHING_BLS_EXP_OUT_B_SHIFT 0U
//!Register: isp_stitching_bls_exp_out_1                (0x000033FC)
//! Slice: stitching_bls_exp_out_c:
#define  STITCHING_BLS_EXP_OUT_C
#define  STITCHING_BLS_EXP_OUT_C_MASK 0x0FFF0000U
#define  STITCHING_BLS_EXP_OUT_C_SHIFT 16U
//! Slice: stitching_bls_exp_out_d:
#define  STITCHING_BLS_EXP_OUT_D
#define  STITCHING_BLS_EXP_OUT_D_MASK 0x00000FFFU
#define  STITCHING_BLS_EXP_OUT_D_SHIFT 0U

/*! Slice: ISP_STITCHING0_EXP_IMSC:*/
#define STITCHING_MIS_HDR_EXP_COMPLETE_L
#define STITCHING_MIS_HDR_EXP_COMPLETE_L_MASK 0x00000008U
#define STITCHING_MIS_HDR_EXP_COMPLETE_L_SHIFT 3U
#define STITCHING_MIS_HDR_EXP_COMPLETE_S
#define STITCHING_MIS_HDR_EXP_COMPLETE_S_MASK 0x00000010U
#define STITCHING_MIS_HDR_EXP_COMPLETE_S_SHIFT 4U
#define STITCHING_MIS_HDR_EXP_COMPLETE_VS
#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_MASK 0x00000020U
#define STITCHING_MIS_HDR_EXP_COMPLETE_VS_SHIFT 5U

/*! Slice: ISP_STITCHING0_HIST_MIS:*/
#define STITCHING_MIS_HDR_HIST_COMPLETE_VS
#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_MASK 0x00000100U
#define STITCHING_MIS_HDR_HIST_COMPLETE_VS_SHIFT 8U
#define STITCHING_MIS_HDR_HIST_COMPLETE_S
#define STITCHING_MIS_HDR_HIST_COMPLETE_S_MASK 0x00000080U
#define STITCHING_MIS_HDR_HIST_COMPLETE_S_SHIFT 7U
#define STITCHING_MIS_HDR_HIST_COMPLETE_L
#define STITCHING_MIS_HDR_HIST_COMPLETE_L_MASK 0x00000040U
#define STITCHING_MIS_HDR_HIST_COMPLETE_L_SHIFT 6U

/*!Slice: 2DNR ENABLE */
#define ISP_2DNR_ENABLE
#define ISP_2DNR_ENABLE_MASK 0x00000001
#define ISP_2DNR_ENABLE_SHIFT 0U
/*!Slice: 2DNR PRGAMMA STRENGTH */
#define ISP_2DNR_PRGAMMA_STRENGTH
#define ISP_2DNR_PRGAMMA_STRENGTH_MASK 0x00003F80
#define ISP_2DNR_PRGAMMA_STRENGTH_SHIFT 7U
/*!Slice: 2DNR STRENGTH */
#define ISP_2DNR_STRENGTH
#define ISP_2DNR_STRENGTH_MASK 0x0000007F
#define ISP_2DNR_STRENGTH_SHIFT 0U
/*!Slice: 2DNR SIGMAY0 */
#define ISP_2DNR_SIGMAY0
#define ISP_2DNR_SIGMAY0_MASK 0x00000FFF
#define ISP_2DNR_SIGMAY0_SHIFT 0U
/*!Slice: 2DNR SIGMAY1 */
#define ISP_2DNR_SIGMAY1
#define ISP_2DNR_SIGMAY1_MASK 0x00FFF000
#define ISP_2DNR_SIGMAY1_SHIFT 12U
/*!Slice: 2DNR SIGMAY2A */
#define ISP_2DNR_SIGMAY2A
#define ISP_2DNR_SIGMAY2A_MASK 0x3F000000
#define ISP_2DNR_SIGMAY2A_SHIFT 24U
/*!Slice: 2DNR SIGMAY2B */
#define ISP_2DNR_SIGMAY2B
#define ISP_2DNR_SIGMAY2B_MASK 0x3F000000
#define ISP_2DNR_SIGMAY2B_SHIFT 24U
/*!Slice: 2DNR SIGMAY3 */
#define ISP_2DNR_SIGMAY3
#define ISP_2DNR_SIGMAY3_MASK 0x00000FFF
#define ISP_2DNR_SIGMAY3_SHIFT 0U
/*!Slice: 2DNR SIGMAY4 */
#define ISP_2DNR_SIGMAY4
#define ISP_2DNR_SIGMAY4_MASK 0x00FFF000
#define ISP_2DNR_SIGMAY4_SHIFT 12U
/*!Slice: 2DNR denoise2d_dummy_hblank */
#define ISP_2DNR_DUMMY_HBLANK
#define ISP_2DNR_DUMMY_HBLANK_MASK 0x0000FFFF
#define ISP_2DNR_DUMMY_HBLANK_SHIFT 0U

/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
#define DENOISE3D_V20_NLM_STRENGTH_OFFSET
#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_MASK 0X3FF80000
#define DENOISE3D_V20_NLM_STRENGTH_OFFSET_SHIFT 19U

/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
#define DENOISE3D_V20_NLM_STRENGTH_MAX
#define DENOISE3D_V20_NLM_STRENGTH_MAX_MASK 0X0007ff00
#define DENOISE3D_V20_NLM_STRENGTH_MAX_SHIFT 8U

/*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
#define DENOISE3D_V20_NLM_STRENGTH_SLOPE
#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_MASK 0X000000ff
#define DENOISE3D_V20_NLM_STRENGTH_SLOPE_SHIFT 0U

/* Register: ISP_DENOISE3D_CTRL 	0x00003700 */
/* Slice: 10:10 denoise3d_read_ref_en */
#define DENOISE3D_READ_REF_EN
#define DENOISE3D_READ_REF_EN_MASK 0x00000400U
#define DENOISE3D_READ_REF_EN_SHIFT 10U

/* Slice: 9:9 denoise3d_raw_decompress_en */
#define DENOISE3D_RAW_DECOMPRESS_EN
#define DENOISE3D_RAW_DECOMPRESS_EN_MASK 0x00000200U
#define DENOISE3D_RAW_DECOMPRESS_EN_SHIFT 9U

/* Slice: 8:8 denoise3d_rew_compress_en */
#define DENOISE3D_RAW_COMPRESS_EN
#define DENOISE3D_RAW_COMPRESS_EN_MASK 0x00000100U
#define DENOISE3D_RAW_COMPRESS_EN_SHIFT 8U

/* Slice: 7:7 denoise3d_write_ref_en */
#define DENOISE3D_WRITE_REF_EN
#define DENOISE3D_WRITE_REF_EN_MASK 0x00000080U
#define DENOISE3D_WRITE_REF_EN_SHIFT 7U
/* Register: ISP_DENOISE3D_CTRL 	0x00003700 */
/* Slice: 5:5 denoise3d_soft_reset */
#define DENOISE3D_SOFT_RESET
#define DENOISE3D_SOFT_RESET_MASK  0x00000020U
#define DENOISE3D_SOFT_RESET_SHIFT 5U
/* Slice: 4:4 denoise3d_horizontal_en */
#define DENOISE3D_HORIZONTAL_EN
#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U
#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U
/* Slice: 3:3 denoise3d_vertical_en */
#define DENOISE3D_VERTICAL_EN
#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U
#define DENOISE3D_VERTICAL_EN_SHIFT 3U
/* Slice: 2:2 denoise3d_temperal_en */
#define DENOISE3D_TEMPERAL_EN
#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U
#define DENOISE3D_TEMPERAL_EN_SHIFT 2U
/* Slice: 1:1 denoise3d_dilate_en */
#define DENOISE3D_DILATE_EN
#define DENOISE3D_DILATE_EN_MASK 0x00000002U
#define DENOISE3D_DILATE_EN_SHIFT 1U
/* Slice: 0:0 denoise3d_enable */
#define DENOISE3D_ENABLE
#define DENOISE3D_ENABLE_MASK 0x00000001U
#define DENOISE3D_ENABLE_SHIFT 0U
/* Register: ISP_DENOISE3D_STRENGTH     0x00003704       */
/* Slice: 29:19 denoise3d_update_temperal */
#define DENOISE3D_UPDATE_TEMPERAL
#define DENOISE3D_UPDATE_TEMPERAL_MASK  0x3FF80000U
#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U
/* Slice: 18 : 8 denoise3d_update_spacial */
#define DENOISE3D_UPDATE_SPACIAL
#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U
#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U
/* Slice: 7 : 0 denoise3d_strength */
#define DENOISE3D_STRENGTH
#define DENOISE3D_STRENGTH_MASK 0x000000FFU
#define DENOISE3D_STRENGTH_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_H       0x00003708 */
/* Slice: 27:20 denoise3d_strength_curve_spacial */
#define DENOISE3D_STRENGTH_CURVE_SPACIAL
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U
/* Slice: 19 : 0        denoise3d_thr_edge_h_inv */
#define DENOISE3D_THR_EDGE_H_INV
#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_V       0x0000370C       */
/* Slice: 27:20 denoise3d_strength_curve_temperal */
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U
/* Slice: 19 : 0        denoise3d_thr_edge_v_inv */
#define DENOISE3D_THR_EDGE_V_INV
#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_S      0x00003710       */
/* Slice: 19:0  denoise3d_range_s_inv */
#define DENOISE3D_RANGE_S_INV
#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_S_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_T      0x00003714       */
/* Slice: 29:25 denoise3d_range_t_h */
#define DENOISE3D_RANGE_T_H
#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U
#define DENOISE3D_RANGE_T_H_SHIFT 25U
/* Slice: 24:20 denoise3d_range_t_v */
#define DENOISE3D_RANGE_T_V
#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U
#define DENOISE3D_RANGE_T_V_SHIFT 20U
/* Slice: 19 : 0        denoise3d_range_t_inv */
#define DENOISE3D_RANGE_T_INV
#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_T_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_MOTION       0x00003718 */
/* Slice: 24:20 denoise3d_range_d */
#define DENOISE3D_RANGE_D
#define DENOISE3D_RANGE_D_MASK 0x01F00000U
#define DENOISE3D_RANGE_D_SHIFT 20U
/* Slice: 19 : 0        denoise3d_motion_inv */
#define DENOISE3D_MOTION_INV
#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU
#define DENOISE3D_MOTION_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_DELTA_INV    0x0000371C       */
/* Slice: 29:20 denoise3d_delta_h_inv */
#define DENOISE3D_DELTA_H_INV
#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U
#define DENOISE3D_DELTA_H_INV_SHIFT 20U
/* Slice: 19 : 10       denoise3d_delta_v_inv */
#define DENOISE3D_DELTA_V_INV
#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U
#define DENOISE3D_DELTA_V_INV_SHIFT 10U
/* Slice: 9 : 0 denoise3d_delta_t_inv */
#define DENOISE3D_DELTA_T_INV
#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU
#define DENOISE3D_DELTA_T_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_0    0x00003720       */
/* Slice: 29:20 denoise3d_spacial_curve0 */
#define DENOISE3D_SPACIAL_CURVE0
#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U
/* Slice: 19 : 10       denoise3d_spacial_curve1 */
#define DENOISE3D_SPACIAL_CURVE1
#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve2 */
#define DENOISE3D_SPACIAL_CURVE2
#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_1    0x00003724       */
/* Slice: 29 : 20       denoise3d_spacial_curve3 */
#define DENOISE3D_SPACIAL_CURVE3
#define DENOISE3D_SPACIAL_CURVE3_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE3_SHIFT 20U
/* Slice: 19 : 10       denoise3d_spacial_curve4 */
#define DENOISE3D_SPACIAL_CURVE4
#define DENOISE3D_SPACIAL_CURVE4_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE4_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve5 */
#define DENOISE3D_SPACIAL_CURVE5
#define DENOISE3D_SPACIAL_CURVE5_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE5_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_2    0x00003728       */
/* Slice: 29 : 20       denoise3d_spacial_curve6 */
#define DENOISE3D_SPACIAL_CURVE6
#define DENOISE3D_SPACIAL_CURVE6_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE6_SHIFT 20U
/* Slice: 19 : 10       denoise3d_spacial_curve7 */
#define DENOISE3D_SPACIAL_CURVE7
#define DENOISE3D_SPACIAL_CURVE7_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE7_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve8 */
#define DENOISE3D_SPACIAL_CURVE8
#define DENOISE3D_SPACIAL_CURVE8_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE8_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_3    0x0000372C       */
/* Slice: 29 : 20       denoise3d_spacial_curve9 */
#define DENOISE3D_SPACIAL_CURVE9
#define DENOISE3D_SPACIAL_CURVE9_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE9_SHIFT 20U
/* Slice: 19 : 10       denoise3d_spacial_curve10 */
#define DENOISE3D_SPACIAL_CURVE10
#define DENOISE3D_SPACIAL_CURVE10_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE10_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve11 */
#define DENOISE3D_SPACIAL_CURVE11
#define DENOISE3D_SPACIAL_CURVE11_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE11_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_4    0x00003730       */
/* Slice: 29 : 20       denoise3d_spacial_curve12 */
#define DENOISE3D_SPACIAL_CURVE12
#define DENOISE3D_SPACIAL_CURVE12_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE12_SHIFT 20U
/* Slice: 19 : 10       denoise3d_spacial_curve13 */
#define DENOISE3D_SPACIAL_CURVE13
#define DENOISE3D_SPACIAL_CURVE13_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE13_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve14 */
#define DENOISE3D_SPACIAL_CURVE14
#define DENOISE3D_SPACIAL_CURVE14_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE14_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_5    0x00003734       */
/* Slice: 19 : 10       denoise3d_spacial_curve15 */
#define DENOISE3D_SPACIAL_CURVE15
#define DENOISE3D_SPACIAL_CURVE15_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE15_SHIFT 10U
/* Slice: 9 : 0 denoise3d_spacial_curve16 */
#define DENOISE3D_SPACIAL_CURVE16
#define DENOISE3D_SPACIAL_CURVE16_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE16_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_0    0x00003738       */
/* Slice: 29 : 20       denoise3d_temperal_curve0 */
#define DENOISE3D_TEMPERAL_CURVE0
#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U
/* Slice: 19 : 10       denoise3d_temperal_curve1 */
#define DENOISE3D_TEMPERAL_CURVE1
#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve2 */
#define DENOISE3D_TEMPERAL_CURVE2
#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_1    0x0000373C       */
/* Slice: 29 : 20       denoise3d_temperal_curve3 */
#define DENOISE3D_TEMPERAL_CURVE3
#define DENOISE3D_TEMPERAL_CURVE3_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE3_SHIFT 20U
/* Slice: 19 : 10       denoise3d_temperal_curve4 */
#define DENOISE3D_TEMPERAL_CURVE4
#define DENOISE3D_TEMPERAL_CURVE4_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE4_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve5 */
#define DENOISE3D_TEMPERAL_CURVE5
#define DENOISE3D_TEMPERAL_CURVE5_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE5_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_2    0x00003740       */
/* Slice: 29 : 20       denoise3d_temperal_curve6 */
#define DENOISE3D_TEMPERAL_CURVE6
#define DENOISE3D_TEMPERAL_CURVE6_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE6_SHIFT 20U
/* Slice: 19 : 10       denoise3d_temperal_curve7 */
#define DENOISE3D_TEMPERAL_CURVE7
#define DENOISE3D_TEMPERAL_CURVE7_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE7_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve8 */
#define DENOISE3D_TEMPERAL_CURVE8
#define DENOISE3D_TEMPERAL_CURVE8_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE8_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_3    0x00003744       */
/* Slice: 29 : 20       denoise3d_temperal_curve9 */
#define DENOISE3D_TEMPERAL_CURVE9
#define DENOISE3D_TEMPERAL_CURVE9_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE9_SHIFT 20U
/* Slice: 19 : 10       denoise3d_temperal_curve10 */
#define DENOISE3D_TEMPERAL_CURVE10
#define DENOISE3D_TEMPERAL_CURVE10_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE10_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve11 */
#define DENOISE3D_TEMPERAL_CURVE11
#define DENOISE3D_TEMPERAL_CURVE11_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE11_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_4    0x00003748       */
/* Slice: 29 : 20       denoise3d_temperal_curve12 */
#define DENOISE3D_TEMPERAL_CURVE12
#define DENOISE3D_TEMPERAL_CURVE12_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE12_SHIFT 20U
/* Slice: 19 : 10       denoise3d_temperal_curve13 */
#define DENOISE3D_TEMPERAL_CURVE13
#define DENOISE3D_TEMPERAL_CURVE13_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE13_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve14 */
#define DENOISE3D_TEMPERAL_CURVE14
#define DENOISE3D_TEMPERAL_CURVE14_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE14_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_5    0x0000374C       */
/* Slice: 19 : 10       denoise3d_temperal_curve15 */
#define DENOISE3D_TEMPERAL_CURVE15
#define DENOISE3D_TEMPERAL_CURVE15_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE15_SHIFT 10U
/* Slice: 9 : 0 denoise3d_temperal_curve16 */
#define DENOISE3D_TEMPERAL_CURVE16
#define DENOISE3D_TEMPERAL_CURVE16_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE16_SHIFT 0U
/* Register: ISP_DENOISE3D_AVERAGE      0x00003750       */
/* Slice: 31 : 0        denoise3d_frame_average */
#define DENOISE3D_FRAME_AVERAGE
#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU
#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U
/* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754       */
/* Slice: 29 : 19       denoise3d_update_temperal_shd */
#define DENOISE3D_UPDATE_TEMPERAL_SHD
#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U
#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U
/* Slice: 18 : 8        denoise3d_update_spacial_shd */
#define DENOISE3D_UPDATE_SPACIAL_SHD
#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U
#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U
/* Slice: 7 : 0 denoise3d_strength_shd */
#define DENOISE3D_STRENGTH_SHD
#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU
#define DENOISE3D_STRENGTH_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_H_SHD   0x00003758       */
/* Slice: 27 : 20       denoise3d_strength_curve_spacial_shd */
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U
/* Slice: 19 : 0        denoise3d_thr_edge_h_inv_shd */
#define DENOISE3D_THR_EDGE_H_INV_SHD
#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_V_SHD   0x0000375C       */
/* Slice: 27 : 20       denoise3d_strength_curve_temperal_shd */
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U
/* Slice: 19 : 0        denoise3d_thr_edge_v_inv_shd */
#define DENOISE3D_THR_EDGE_V_INV_SHD
#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_S_SHD  0x00003760       */
/* Slice: 19 : 0        denoise3d_range_s_inv_shd */
#define DENOISE3D_RANGE_S_INV_SHD
#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_T_SHD  0x00003764       */
/* Slice: 29 : 25       denoise3d_range_t_h_shd */
#define DENOISE3D_RANGE_T_H_SHD
#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U
#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U
/* Slice: 24 : 20       denoise3d_range_t_v_shd */
#define DENOISE3D_RANGE_T_V_SHD
#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U
#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U
/* Slice: 19 : 0        denoise3d_range_t_inv_shd */
#define DENOISE3D_RANGE_T_INV_SHD
#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_MOTION_SHD   0x00003768       */
/* Slice: 24 : 20       denoise3d_range_d_shd */
#define DENOISE3D_RANGE_D_SHD
#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U
#define DENOISE3D_RANGE_D_SHD_SHIFT 20U
/* Slice: 19 : 0        denoise3d_motion_inv_shd */
#define DENOISE3D_MOTION_INV_SHD
#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_DELTA_INV_SHD        0x0000376C       */
/* Slice: 29 : 20       denoise3d_delta_h_inv_shd */
#define DENOISE3D_DELTA_H_INV_SHD
#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U
#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U
/* Slice: 19 : 10       denoise3d_delta_v_inv_shd */
#define DENOISE3D_DELTA_V_INV_SHD
#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U
/* Slice: 9 : 0 denoise3d_delta_t_inv_shd */
#define DENOISE3D_DELTA_T_INV_SHD
#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU
#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770       */
/* Slice: 14 : 0        denoise3d_H_Blank */
#define DENOISE3D_H_BLANK
#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU
#define DENOISE3D_H_BLANK_SHIFT 0U
/* Register: ISP_DENOISE3D_CTRL         0x00003700 */
/* Slice: 5:5 denoise3d_soft_reset */
#define DENOISE3D_SOFT_RESET
#define DENOISE3D_SOFT_RESET_MASK  0x00000020U
#define DENOISE3D_SOFT_RESET_SHIFT 5U
/* Slice: 4:4 denoise3d_horizontal_en */
#define DENOISE3D_HORIZONTAL_EN
#define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U
#define DENOISE3D_HORIZONTAL_EN_SHIFT 4U
/* Slice: 3:3 denoise3d_vertical_en */
#define DENOISE3D_VERTICAL_EN
#define DENOISE3D_VERTICAL_EN_MASK 0x00000008U
#define DENOISE3D_VERTICAL_EN_SHIFT 3U
/* Slice: 2:2 denoise3d_temperal_en */
#define DENOISE3D_TEMPERAL_EN
#define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U
#define DENOISE3D_TEMPERAL_EN_SHIFT 2U
/* Slice: 1:1 denoise3d_dilate_en */
#define DENOISE3D_DILATE_EN
#define DENOISE3D_DILATE_EN_MASK 0x00000002U
#define DENOISE3D_DILATE_EN_SHIFT 1U
/* Slice: 0:0 denoise3d_enable */
#define DENOISE3D_ENABLE
#define DENOISE3D_ENABLE_MASK 0x00000001U
#define DENOISE3D_ENABLE_SHIFT 0U
/* Register: ISP_DENOISE3D_STRENGTH	0x00003704 */
/* Slice: 29:19	denoise3d_update_temperal */
#define DENOISE3D_UPDATE_TEMPERAL
#define DENOISE3D_UPDATE_TEMPERAL_MASK  0x3FF80000U
#define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U
/* Slice: 18 : 8 denoise3d_update_spacial */
#define DENOISE3D_UPDATE_SPACIAL
#define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U
#define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U
/* Slice: 7 : 0	denoise3d_strength */
#define DENOISE3D_STRENGTH
#define DENOISE3D_STRENGTH_MASK 0x000000FFU
#define DENOISE3D_STRENGTH_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_H	0x00003708 */
/* Slice: 27:20	denoise3d_strength_curve_spacial */
#define DENOISE3D_STRENGTH_CURVE_SPACIAL
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U
/* Slice: 19 : 0	denoise3d_thr_edge_h_inv */
#define DENOISE3D_THR_EDGE_H_INV
#define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_V	0x0000370C */
/* Slice: 27:20	denoise3d_strength_curve_temperal */
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U
/* Slice: 19 : 0	denoise3d_thr_edge_v_inv */
#define DENOISE3D_THR_EDGE_V_INV
#define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_S	0x00003710 */
/* Slice: 19:0	denoise3d_range_s_inv */
#define DENOISE3D_RANGE_S_INV
#define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_S_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_T	0x00003714 */
/* Slice: 29:25	denoise3d_range_t_h */
#define DENOISE3D_RANGE_T_H
#define DENOISE3D_RANGE_T_H_MASK 0x3E000000U
#define DENOISE3D_RANGE_T_H_SHIFT 25U
/* Slice: 24:20	denoise3d_range_t_v */
#define DENOISE3D_RANGE_T_V
#define DENOISE3D_RANGE_T_V_MASK 0x01F00000U
#define DENOISE3D_RANGE_T_V_SHIFT 20U
/* Slice: 19 : 0	denoise3d_range_t_inv */
#define DENOISE3D_RANGE_T_INV
#define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_T_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_MOTION	0x00003718 */
/* Slice: 24:20	denoise3d_range_d */
#define DENOISE3D_RANGE_D
#define DENOISE3D_RANGE_D_MASK 0x01F00000U
#define DENOISE3D_RANGE_D_SHIFT 20U
/* Slice: 19 : 0	denoise3d_motion_inv */
#define DENOISE3D_MOTION_INV
#define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU
#define DENOISE3D_MOTION_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_DELTA_INV	0x0000371C */
/* Slice: 29:20	denoise3d_delta_h_inv */
#define DENOISE3D_DELTA_H_INV
#define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U
#define DENOISE3D_DELTA_H_INV_SHIFT 20U
/* Slice: 19 : 10	denoise3d_delta_v_inv */
#define DENOISE3D_DELTA_V_INV
#define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U
#define DENOISE3D_DELTA_V_INV_SHIFT 10U
/* Slice: 9 : 0	denoise3d_delta_t_inv */
#define DENOISE3D_DELTA_T_INV
#define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU
#define DENOISE3D_DELTA_T_INV_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_S_0	0x00003720 */
/* Slice: 29:20	denoise3d_spacial_curve0 */
#define DENOISE3D_SPACIAL_CURVE0
#define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U
#define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U
/* Slice: 19 : 10	denoise3d_spacial_curve1 */
#define DENOISE3D_SPACIAL_CURVE1
#define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U
#define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U
/* Slice: 9 : 0	denoise3d_spacial_curve2 */
#define DENOISE3D_SPACIAL_CURVE2
#define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU
#define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U
/* Register: ISP_DENOISE3D_CURVE_T_0	0x00003738 */
/* Slice: 29 : 20	denoise3d_temperal_curve0 */
#define DENOISE3D_TEMPERAL_CURVE0
#define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U
#define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U
/* Slice: 19 : 10	denoise3d_temperal_curve1 */
#define DENOISE3D_TEMPERAL_CURVE1
#define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U
#define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U
/* Slice: 9 : 0	denoise3d_temperal_curve2 */
#define DENOISE3D_TEMPERAL_CURVE2
#define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU
#define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U
/* Register: ISP_DENOISE3D_AVERAGE	0x00003750 */
/* Slice: 31 : 0	denoise3d_frame_average */
#define DENOISE3D_FRAME_AVERAGE
#define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU
#define DENOISE3D_FRAME_AVERAGE_SHIFT 0U
/* Register: ISP_DENOISE3D_STRENGTH_SHD	0x00003754 */
/* Slice: 29 : 19	denoise3d_update_temperal_shd */
#define DENOISE3D_UPDATE_TEMPERAL_SHD
#define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U
#define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U
/* Slice: 18 : 8	denoise3d_update_spacial_shd */
#define DENOISE3D_UPDATE_SPACIAL_SHD
#define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U
#define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U
/* Slice: 7 : 0	denoise3d_strength_shd */
#define DENOISE3D_STRENGTH_SHD
#define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU
#define DENOISE3D_STRENGTH_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_H_SHD	0x00003758 */
/* Slice: 27 : 20	denoise3d_strength_curve_spacial_shd */
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U
/* Slice: 19 : 0	denoise3d_thr_edge_h_inv_shd */
#define DENOISE3D_THR_EDGE_H_INV_SHD
#define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_EDGE_V_SHD	0x0000375C */
/* Slice: 27 : 20	denoise3d_strength_curve_temperal_shd */
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U
#define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U
/* Slice: 19 : 0	denoise3d_thr_edge_v_inv_shd */
#define DENOISE3D_THR_EDGE_V_INV_SHD
#define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_S_SHD	0x00003760 */
/* Slice: 19 : 0	denoise3d_range_s_inv_shd */
#define DENOISE3D_RANGE_S_INV_SHD
#define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_RANGE_T_SHD	0x00003764 */
/* Slice: 29 : 25	denoise3d_range_t_h_shd */
#define DENOISE3D_RANGE_T_H_SHD
#define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U
#define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U
/* Slice: 24 : 20	denoise3d_range_t_v_shd */
#define DENOISE3D_RANGE_T_V_SHD
#define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U
#define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U
/* Slice: 19 : 0	denoise3d_range_t_inv_shd */
#define DENOISE3D_RANGE_T_INV_SHD
#define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_MOTION_SHD	0x00003768 */
/* Slice: 24 : 20	denoise3d_range_d_shd */
#define DENOISE3D_RANGE_D_SHD
#define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U
#define DENOISE3D_RANGE_D_SHD_SHIFT 20U
/* Slice: 19 : 0	denoise3d_motion_inv_shd */
#define DENOISE3D_MOTION_INV_SHD
#define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_MOTION_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_DELTA_INV_SHD	0x0000376C */
/* Slice: 29 : 20	denoise3d_delta_h_inv_shd */
#define DENOISE3D_DELTA_H_INV_SHD
#define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U
#define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U
/* Slice: 19 : 10	denoise3d_delta_v_inv_shd */
#define DENOISE3D_DELTA_V_INV_SHD
#define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU
#define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U
/* Slice: 9 : 0	denoise3d_delta_t_inv_shd */
#define DENOISE3D_DELTA_T_INV_SHD
#define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU
#define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U
/* Register: ISP_DENOISE3D_DUMMY_HBLANK	0x00003770 */
/* Slice: 14 : 0	denoise3d_H_Blank */
#define DENOISE3D_H_BLANK
#define DENOISE3D_H_BLANK_MASK 0x0000FFFFU
#define DENOISE3D_H_BLANK_SHIFT 0U
/* Register: ISP_DENOISE3D_WEIGHT1 0x00003778 */
/* Slice:  denoise3d_weight_up_y0 */
#define DENOISE3D_WEIGHT_UP_Y0
#define DENOISE3D_WEIGHT_UP_Y0_MASK 0x00F00000U
#define DENOISE3D_WEIGHT_UP_Y0_SHIFT 20U
#define DENOISE3D_WEIGHT_UP_Y1
#define DENOISE3D_WEIGHT_UP_Y1_MASK 0x000F0000U
#define DENOISE3D_WEIGHT_UP_Y1_SHIFT 16U
#define DENOISE3D_WEIGHT
#define DENOISE3D_WEIGHT_MASK 0x0000000FU
#define DENOISE3D_WEIGHT_SHIFT 0U
/*! for miv2 by shenchao */
/*! Register: miv2_ctrl (0x00001300)*/
/*! Slice: sp2_raw2_continous:*/
#define SP2_RAW2_CONTINUOUS
#define SP2_RAW2_CONTINUOUS_MASK 0x1 << 24
#define SP2_RAW2_CONTINUOUS_SHIFT 24U

#define SP2_RAW2_START
#define SP2_RAW2_START_MASK 0x1 << 23
#define SP2_RAW2_START_SHIFT 23U

#define PP_DMA_CONTINUOUS
#define PP_DMA_CONTINUOUS_MASK 0x1 << 22
#define PP_DMA_CONTINUOUS_SHIFT 22U

#define PP_DMA_START
#define PP_DMA_START_MASK 0x1 << 21
#define PP_DMA_START_SHIFT 21U

#define SP2_RAW2_WRITE_PATH_ENABLE
#define SP2_RAW2_WRITE_PATH_ENABLE_MASK 0x1 << 20
#define SP2_RAW2_WRITE_PATH_ENABLE_SHIFT 20U

#define PP_WRITE_PATH_ENABLE
#define PP_WRITE_PATH_ENABLE_MASK 0x1 << 19
#define PP_WRITE_PATH_ENABLE_SHIFT 19U

#define MCM_G2_RAW1_PATH_ENABLE
#define MCM_G2_RAW1_PATH_ENABLE_MASK 0x1 << 18
#define MCM_G2_RAW1_PATH_ENABLE_SHIFT 18U

#define MCM_G2_RAW0_PATH_ENABLE
#define MCM_G2_RAW0_PATH_ENABLE_MASK 0x1 << 17
#define MCM_G2_RAW0_PATH_ENABLE_SHIFT 17U

//! Register: isp_hdr_exp_conf: Exposure control (0x00000000)
//! Slice: exp_meas_mode:
//! '1' luminance calculation according to
// Y=(R+G+B) x 0.332 (85/256)
// '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
#define MRV_HDR_EXP_MEAS_MODE
#define MRV_HDR_EXP_MEAS_MODE_MASK 0x80000000U
#define MRV_HDR_EXP_MEAS_MODE_SHIFT 31U
//! Slice: src_select:
#define MRV_HDR_EXP_SRC_SEL
#define MRV_HDR_EXP_SRC_SEL_MASK 0x00000004U
#define MRV_HDR_EXP_SRC_SEL_SHIFT 2U
//! Slice: autostop:
//! '1' stop measuring after a complete frame
// '0' continous measurement
#define MRV_HDR_EXP_AUTOSTOP
#define MRV_HDR_EXP_AUTOSTOP_MASK 0x00000002U
#define MRV_HDR_EXP_AUTOSTOP_SHIFT 1U
//! Slice: exp_start:
//! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.
#define MRV_HDR_EXP_START
#define MRV_HDR_EXP_START_MASK 0x00000001U
#define MRV_HDR_EXP_START_SHIFT 0U

//! Register: isp_hdr_exp_h_offset: Horizontal offset for first block (0x00000004)
#define MRV_ISP_HDR_EXP_H_OFFSET
#define MRV_ISP_HDR_EXP_H_OFFSET_MASK 0x00001FFFU
#define MRV_ISP_HDR_EXP_H_OFFSET_SHIFT 0U

//! Register: isp_hdr_exp_v_offset: Vertical offset for first block (0x00000008)
#define MRV_ISP_HDR_EXP_V_OFFSET
#define MRV_ISP_HDR_EXP_V_OFFSET_MASK 0x00001FFFU
#define MRV_ISP_HDR_EXP_V_OFFSET_SHIFT 0U

//! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)
#define MRV_ISP_HDR_EXP_H_SIZE
#define MRV_ISP_HDR_EXP_H_SIZE_MASK 0x000007FFU
#define MRV_ISP_HDR_EXP_H_SIZE_SHIFT 0U

//! Register: isp_exp_v_size: Vertical size of one block (0x00000010)
#define MRV_ISP_HDR_EXP_V_SIZE
#define MRV_ISP_HDR_EXP_V_SIZE_MASK 0x000007FEU
#define MRV_ISP_HDR_EXP_V_SIZE_SHIFT 0U
/*! for miv2 by shenchao */
/*! Register: miv2_ctrl (0x00001300)*/
/*! Slice: mcm_raw_rdma_start_con:*/
#define MCM_RAW_RDMA_START_CON
#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U
#define MCM_RAW_RDMA_START_CON_SHIFT 16U
/*! Slice: mcm_raw_rdma_start:*/
#define MCM_RAW_RDMA_START
#define MCM_RAW_RDMA_START_MASK 0x00008000U
#define MCM_RAW_RDMA_START_SHIFT 15U
/*! Slice: mcm_raw_rdma_path_enable:*/
#define MCM_RAW_RDMA_PATH_ENABLE
#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U
#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U
/*! Slice: sp2_raw2_rdma_start_con:*/
#define SP2_RAW2_RDMA_START_CON
#define SP2_RAW2_RDMA_START_CON_MASK 0x01000000U
#define SP2_RAW2_RDMA_START_CON_SHIFT 24U
/*! Slice: sp2_raw2_rdma_start:*/
#define SP2_RAW2_RDMA_START
#define SP2_RAW2_RDMA_START_MASK 0x00800000U
#define SP2_RAW2_RDMA_START_SHIFT 23U
/*! Slice: sp2_raw_rdma_start_con:*/
#define SP2_RAW_RDMA_START_CON
#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U
#define SP2_RAW_RDMA_START_CON_SHIFT 13U
/*! Slice: sp2_raw_rdma_start:*/
#define SP2_RAW_RDMA_START
#define SP2_RAW_RDMA_START_MASK 0x00001000U
#define SP2_RAW_RDMA_START_SHIFT 12U
/*! Slice: sp2_raw_rdma_path_enable:*/
#define SP2_RAW_RDMA_PATH_ENABLE
#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U
#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U
/*! Slice: sp2_ycbcr_rdma_start_con:*/
#define SP2_YCBCR_RDMA_START_CON
#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U
#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U
/*! Slice: sp2_ycbcr_rdma_start:*/
#define SP2_YCBCR_RDMA_START
#define SP2_YCBCR_RDMA_START_MASK 0x00000200U
#define SP2_YCBCR_RDMA_START_SHIFT 9U
/*! Slice: sp2_ycbcr_rdma_path_enable:*/
#define SP2_YCBCR_RDMA_PATH_ENABLE
#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U
#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U
/*! Slice: mcm_raw1_path_enable:*/
#define MCM_RAW1_PATH_ENABLE
#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U
#define MCM_RAW1_PATH_ENABLE_SHIFT 7U
/*! Slice: mcm_raw0_path_enable:*/
#define MCM_RAW0_PATH_ENABLE
#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U
#define MCM_RAW0_PATH_ENABLE_SHIFT 6U
/*! Slice: sp2_raw_path_enable:*/
#define SP2_RAW_PATH_ENABLE
#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U
#define SP2_RAW_PATH_ENABLE_SHIFT 5U
/*! Slice: sp2_ycbcr_path_enable:*/
#define SP2_YCBCR_PATH_ENABLE
#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U
#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U
/*! Slice: sp1_ycbcr_path_enable:*/
#define SP1_YCBCR_PATH_ENABLE
#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U
#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U
/*! Slice: mp_jdp_path_enable:*/
#define MP_JDP_PATH_ENABLE
#define MP_JDP_PATH_ENABLE_MASK 0x00000004U
#define MP_JDP_PATH_ENABLE_SHIFT 2U
/*! Slice: mp_raw_path_enable:*/
#define MP_RAW_PATH_ENABLE
#define MP_RAW_PATH_ENABLE_MASK 0x00000002U
#define MP_RAW_PATH_ENABLE_SHIFT 1U
/*! Slice: mp_ycbcr_path_enable:*/
#define MP_YCBCR_PATH_ENABLE
#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U
#define MP_YCBCR_PATH_ENABLE_SHIFT 0U
/*! Register: miv2_ctrl_shd (0x00001304)*/
/*! Slice: mcm_raw_rdma_start_con:*/
#define MCM_RAW_RDMA_START_CON
#define MCM_RAW_RDMA_START_CON_MASK 0x00010000U
#define MCM_RAW_RDMA_START_CON_SHIFT 16U
/*! Slice: mcm_raw_rdma_start:*/
#define MCM_RAW_RDMA_START
#define MCM_RAW_RDMA_START_MASK 0x00008000U
#define MCM_RAW_RDMA_START_SHIFT 15U
/*! Slice: mcm_raw_rdma_path_enable:*/
#define MCM_RAW_RDMA_PATH_ENABLE
#define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U
#define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U
/*! Slice: sp2_raw_rdma_start_con:*/
#define SP2_RAW_RDMA_START_CON
#define SP2_RAW_RDMA_START_CON_MASK 0x00002000U
#define SP2_RAW_RDMA_START_CON_SHIFT 13U
/*! Slice: sp2_raw_rdma_start:*/
#define SP2_RAW_RDMA_START
#define SP2_RAW_RDMA_START_MASK 0x00001000U
#define SP2_RAW_RDMA_START_SHIFT 12U
/*! Slice: sp2_raw_rdma_path_enable:*/
#define SP2_RAW_RDMA_PATH_ENABLE
#define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U
#define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U
/*! Slice: sp2_ycbcr_rdma_start_con:*/
#define SP2_YCBCR_RDMA_START_CON
#define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U
#define SP2_YCBCR_RDMA_START_CON_SHIFT 10U
/*! Slice: sp2_ycbcr_rdma_start:*/
#define SP2_YCBCR_RDMA_START
#define SP2_YCBCR_RDMA_START_MASK 0x00000200U
#define SP2_YCBCR_RDMA_START_SHIFT 9U
/*! Slice: sp2_ycbcr_rdma_path_enable:*/
#define SP2_YCBCR_RDMA_PATH_ENABLE
#define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U
#define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U
/*! Slice: mcm_raw1_path_enable:*/
#define MCM_RAW1_PATH_ENABLE
#define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U
#define MCM_RAW1_PATH_ENABLE_SHIFT 7U
/*! Slice: mcm_raw0_path_enable:*/
#define MCM_RAW0_PATH_ENABLE
#define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U
#define MCM_RAW0_PATH_ENABLE_SHIFT 6U
/*! Slice: sp2_raw_path_enable:*/
#define SP2_RAW_PATH_ENABLE
#define SP2_RAW_PATH_ENABLE_MASK 0x00000020U
#define SP2_RAW_PATH_ENABLE_SHIFT 5U
/*! Slice: sp2_ycbcr_path_enable:*/
#define SP2_YCBCR_PATH_ENABLE
#define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U
#define SP2_YCBCR_PATH_ENABLE_SHIFT 4U
/*! Slice: sp1_ycbcr_path_enable:*/
#define SP1_YCBCR_PATH_ENABLE
#define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U
#define SP1_YCBCR_PATH_ENABLE_SHIFT 3U
/*! Slice: mp_jdp_path_enable:*/
#define MP_JDP_PATH_ENABLE
#define MP_JDP_PATH_ENABLE_MASK 0x00000004U
#define MP_JDP_PATH_ENABLE_SHIFT 2U
/*! Slice: mp_raw_path_enable:*/
#define MP_RAW_PATH_ENABLE
#define MP_RAW_PATH_ENABLE_MASK 0x00000002U
#define MP_RAW_PATH_ENABLE_SHIFT 1U
/*! Slice: mp_ycbcr_path_enable:*/
#define MP_YCBCR_PATH_ENABLE
#define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U
#define MP_YCBCR_PATH_ENABLE_SHIFT 0U
/*! Register: miv2_mp_ctrl (0x00001310)*/
/*! Slice: mp_init_offset_en:*/
#define MP_INIT_OFFSET_EN
#define MP_INIT_OFFSET_EN_MASK 0x00000020U
#define MP_INIT_OFFSET_EN_SHIFT 5U
/*! Slice: mp_init_base_en:*/
#define MP_INIT_BASE_EN
#define MP_INIT_BASE_EN_MASK 0x00000010U
#define MP_INIT_BASE_EN_SHIFT 4U
/*! Slice: mp_miv2_cfg_upd:*/
#define MP_MI_CFG_UPD
#define MP_MI_CFG_UPD_MASK 0x00000008U
#define MP_MI_CFG_UPD_SHIFT 3U
/*! Slice: mp_miv2_skip:*/
#define MP_MI_SKIP
#define MP_MI_SKIP_MASK 0x00000004U
#define MP_MI_SKIP_SHIFT 2U
/*! Slice: mp_auto_update:*/
#define MP_AUTO_UPDATE
#define MP_AUTO_UPDATE_MASK 0x00000002U
#define MP_AUTO_UPDATE_SHIFT 1U
/*! Slice: mp_pingpong_enable:*/
#define MP_PINGPONG_ENABLE
#define MP_PINGPONG_ENABLE_MASK 0x00000001U
#define MP_PINGPONG_ENABLE_SHIFT 0U
/*! Register: miv2_mp_fmt (0x00001314)*/
/*! Slice: mp_wr_jdp_dp_bit:*/
#define MP_WR_JDP_DP_BIT
#define MP_WR_JDP_DP_BIT_MASK 0x000020000U
#define MP_WR_JDP_DP_BIT_SHIFT 17U

/*! Slice: mp_wr_yuv_nvy:*/
#define MP_WR_YUV_NVY
#define MP_WR_YUV_NVY_MASK 0x00006000U
#define MP_WR_YUV_NVY_SHIFT 13U
/*! Slice: mp_wr_yuv_nv21:*/
#define MP_WR_YUV_NV21
#define MP_WR_YUV_NV21_MASK 0x00001000U
#define MP_WR_YUV_NV21_SHIFT 12U
/*! Slice: mp_wr_raw_aligned:*/
#define MP_WR_RAW_ALIGNED
#define MP_WR_RAW_ALIGNED_MASK 0x00000C00U
#define MP_WR_RAW_ALIGNED_SHIFT 10U
/*! Slice: mp_wr_yuv_aligned:*/
#define MP_WR_YUV_ALIGNED
#define MP_WR_YUV_ALIGNED_MASK 0x00000200U
#define MP_WR_YUV_ALIGNED_SHIFT 9U
/*! Slice: mp_wr_raw_bit:*/
#define MP_WR_RAW_BIT
#define MP_WR_RAW_BIT_MASK 0x000001C0U
#define MP_WR_RAW_BIT_SHIFT 6U
/*! Slice: mp_wr_yuv_str:*/
#define MP_WR_YUV_STR
#define MP_WR_YUV_STR_MASK 0x00000030U
#define MP_WR_YUV_STR_SHIFT 4U
/*! Slice: mp_wr_yuv_fmt:*/
#define MP_WR_YUV_FMT
#define MP_WR_YUV_FMT_MASK 0x0000000CU
#define MP_WR_YUV_FMT_SHIFT 2U
/*! Slice: mp_wr_yuv_bit:*/
#define MP_WR_YUV_BIT
#define MP_WR_YUV_BIT_MASK 0x00000002U
#define MP_WR_YUV_BIT_SHIFT 1U
/*! Slice: mp_wr_jdp_fmt:*/
#define MP_WR_JDP_FMT
#define MP_WR_JDP_FMT_MASK 0x00000001U
#define MP_WR_JDP_FMT_SHIFT 0U
/*! Register: miv2_mp_bus_cfg (0x00001318)*/
/*! Slice: mp_wr_swap_jdp:*/
#define MP_WR_SWAP_JDP
#define MP_WR_SWAP_JDP_MASK 0x0F000000U
#define MP_WR_SWAP_JDP_SHIFT 24U
/*! Slice: mp_wr_swap_raw:*/
#define MP_WR_SWAP_RAW
#define MP_WR_SWAP_RAW_MASK 0x00F00000U
#define MP_WR_SWAP_RAW_SHIFT 20U
/*! Slice: mp_wr_swap_v:*/
#define MP_WR_SWAP_V
#define MP_WR_SWAP_V_MASK 0x000F0000U
#define MP_WR_SWAP_V_SHIFT 16U
/*! Slice: mp_wr_swap_u:*/
#define MP_WR_SWAP_U
#define MP_WR_SWAP_U_MASK 0x0000F000U
#define MP_WR_SWAP_U_SHIFT 12U
/*! Slice: mp_wr_swap_y:*/
#define MP_WR_SWAP_Y
#define MP_WR_SWAP_Y_MASK 0x00000F00U
#define MP_WR_SWAP_Y_SHIFT 8U
/*! Slice: mp_rd_issue_cap:*/
#define MP_RD_ISSUE_CAP
#define MP_RD_ISSUE_CAP_MASK 0x000000C0U
#define MP_RD_ISSUE_CAP_SHIFT 6U
/*! Slice: mp_wr_issue_cap:*/
#define MP_WR_ISSUE_CAP
#define MP_WR_ISSUE_CAP_MASK 0x00000030U
#define MP_WR_ISSUE_CAP_SHIFT 4U
/*! Slice: mp_rd_burst_len:*/
#define MP_RD_BURST_LEN
#define MP_RD_BURST_LEN_MASK 0x0000000CU
#define MP_RD_BURST_LEN_SHIFT 2U
/*! Slice: mp_wr_burst_len:*/
#define MP_WR_BURST_LEN
#define MP_WR_BURST_LEN_MASK 0x00000003U
#define MP_WR_BURST_LEN_SHIFT 0U
/*! Register: miv2_mp_bus_id (0x0000131c)*/
/*! Slice: mp_bus_sw_en:*/
#define MP_BUS_SW_EN
#define MP_BUS_SW_EN_MASK 0x02000000U
#define MP_BUS_SW_EN_SHIFT 25U
/*! Slice: mp_rd_id_en:*/
#define MP_RD_ID_EN
#define MP_RD_ID_EN_MASK 0x01000000U
#define MP_RD_ID_EN_SHIFT 24U
/*! Slice: mp_rd_id_cfg:*/
#define MP_RD_ID_CFG
#define MP_RD_ID_CFG_MASK 0x00FF0000U
#define MP_RD_ID_CFG_SHIFT 16U
/*! Slice: mp_wr_id_en:*/
#define MP_WR_ID_EN
#define MP_WR_ID_EN_MASK 0x00000100U
#define MP_WR_ID_EN_SHIFT 8U
/*! Slice: mp_wr_id_cfg:*/
#define MP_WR_ID_CFG
#define MP_WR_ID_CFG_MASK 0x000000FFU
#define MP_WR_ID_CFG_SHIFT 0U
/*! Register: miv2_mp_bus_timeo (0x00001320)*/
/*! Slice: mp_bus_timeo_en:*/
#define MP_BUS_TIMEO_EN
#define MP_BUS_TIMEO_EN_MASK 0x80000000U
#define MP_BUS_TIMEO_EN_SHIFT 31U
/*! Slice: mp_bus_timeo:*/
#define MP_BUS_TIMEO
#define MP_BUS_TIMEO_MASK 0x7FFFFFFEU
#define MP_BUS_TIMEO_SHIFT 1U

/*! Slice: mp_bus_timeo_interrupt_disable:*/
/*! 0 enable 1 disable*/
#define MP_BUS_TIMEO_INTERRUPT_DISABLE
#define MP_BUS_TIMEO_INTERRUPT_DISABLE_MASK 1U
#define MP_BUS_TIMEO_INTERRUPT_DISABLE_SHIFT 0U
/*! Register: miv2_mp_y_base_ad_init (0x00001324)*/
/*! Slice: mp_y_base_ad_init:*/
#define MP_Y_BASE_AD_INIT
#define MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MP_Y_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mp_y_size_init (0x00001328)*/
/*! Slice: mp_y_size_init:*/
#define MP_Y_SIZE_INIT
#define MP_Y_SIZE_INIT_MASK 0x1FFFFFF0U
#define MP_Y_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mp_y_offs_cnt_init (0x0000132c)*/
/*! Slice: mp_y_offs_cnt_init:*/
#define MP_Y_OFFS_CNT_INIT
#define MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define MP_Y_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mp_y_llength (0x00001330)*/
/*! Slice: mp_y_llengh:*/
#define MP_Y_LLENGH
#define MP_Y_LLENGH_MASK 0x00007FFFU
#define MP_Y_LLENGH_SHIFT 0U
/*! Register: miv2_mp_y_pic_width (0x00001334)*/
/*! Slice: mp_y_pic_width:*/
#define MP_Y_PIC_WIDTH
#define MP_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MP_Y_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mp_y_pic_height (0x00001338)*/
/*! Slice: mp_y_pic_height:*/
#define MP_Y_PIC_HEIGHT
#define MP_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MP_Y_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_mp_y_pic_size (0x0000133c)*/
/*! Slice: mp_y_pic_size:*/
#define MP_Y_PIC_SIZE
#define MP_Y_PIC_SIZE_MASK 0xFFFFFFFFU
#define MP_Y_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mp_cb_base_ad_init (0x00001340)*/
/*! Slice: mp_cb_base_ad_init:*/
#define MP_CB_BASE_AD_INIT
#define MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MP_CB_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mp_cb_size_init (0x00001344)*/
/*! Slice: mp_cb_size_init:*/
#define MP_CB_SIZE_INIT
#define MP_CB_SIZE_INIT_MASK 0x0FFFFFF0U
#define MP_CB_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mp_cb_offs_cnt_init (0x00001348)*/
/*! Slice: mp_cb_offs_cnt_init:*/
#define MP_CB_OFFS_CNT_INIT
#define MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define MP_CB_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mp_cr_base_ad_init (0x0000134c)*/
/*! Slice: mp_cr_base_ad_init:*/
#define MP_CR_BASE_AD_INIT
#define MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MP_CR_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mp_cr_size_init (0x00001350)*/
/*! Slice: mp_cr_size_init:*/
#define MP_CR_SIZE_INIT
#define MP_CR_SIZE_INIT_MASK 0x0FFFFFF0U
#define MP_CR_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mp_cr_offs_cnt_init (0x00001354)*/
/*! Slice: mp_cr_offs_cnt_init:*/
#define MP_CR_OFFS_CNT_INIT
#define MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define MP_CR_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mp_y_base_ad_init2 (0x00001358)*/
/*! Slice: mp_y_base_ad_init2:*/
#define MP_Y_BASE_AD_INIT2
#define MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define MP_Y_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_mp_cb_base_ad_init2 (0x0000135c)*/
/*! Slice: mp_cb_base_ad_init2:*/
#define MP_CB_BASE_AD_INIT2
#define MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define MP_CB_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_mp_cr_base_ad_init2 (0x00001360)*/
/*! Slice: mp_cr_base_ad_init2:*/
#define MP_CR_BASE_AD_INIT2
#define MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define MP_CR_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_mp_y_offs_cnt_start (0x00001364)*/
/*! Slice: mp_y_offs_cnt_start:*/
#define MP_Y_OFFS_CNT_START
#define MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define MP_Y_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mp_cb_offs_cnt_start (0x00001368)*/
/*! Slice: mp_cb_offs_cnt_start:*/
#define MP_CB_OFFS_CNT_START
#define MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define MP_CB_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mp_cr_offs_cnt_start (0x0000136c)*/
/*! Slice: mp_cr_offs_cnt_start:*/
#define MP_CR_OFFS_CNT_START
#define MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define MP_CR_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mp_y_base_ad_shd (0x00001370)*/
/*! Slice: mp_y_base_ad:*/
#define MP_Y_BASE_AD
#define MP_Y_BASE_AD_MASK 0xFFFFFFF0U
#define MP_Y_BASE_AD_SHIFT 4U
/*! Register: miv2_mp_y_size_shd (0x00001374)*/
/*! Slice: mp_y_size:*/
#define MP_Y_SIZE
#define MP_Y_SIZE_MASK 0x1FFFFFF0U
#define MP_Y_SIZE_SHIFT 4U
/*! Register: miv2_mp_y_offs_cnt_shd (0x00001378)*/
/*! Slice: mp_y_offs_cnt:*/
#define MP_Y_OFFS_CNT
#define MP_Y_OFFS_CNT_MASK 0x1FFFFFF0U
#define MP_Y_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mp_cb_base_ad_shd (0x0000137c)*/
/*! Slice: mp_cb_base_ad:*/
#define MP_CB_BASE_AD
#define MP_CB_BASE_AD_MASK 0xFFFFFFF0U
#define MP_CB_BASE_AD_SHIFT 4U
/*! Register: miv2_mp_cb_size_shd (0x00001380)*/
/*! Slice: mp_cb_size:*/
#define MP_CB_SIZE
#define MP_CB_SIZE_MASK 0x0FFFFFF0U
#define MP_CB_SIZE_SHIFT 4U
/*! Register: miv2_mp_cb_offs_cnt_shd (0x00001384)*/
/*! Slice: mp_cb_offs_cnt:*/
#define MP_CB_OFFS_CNT
#define MP_CB_OFFS_CNT_MASK 0x0FFFFFF0U
#define MP_CB_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mp_cr_base_ad_shd (0x00001388)*/
/*! Slice: mp_cr_base_ad:*/
#define MP_CR_BASE_AD
#define MP_CR_BASE_AD_MASK 0xFFFFFFF0U
#define MP_CR_BASE_AD_SHIFT 4U
/*! Register: miv2_mp_cr_size_shd (0x0000138c)*/
/*! Slice: mp_cr_size:*/
#define MP_CR_SIZE
#define MP_CR_SIZE_MASK 0x0FFFFFF0U
#define MP_CR_SIZE_SHIFT 4U
/*! Register: miv2_mp_cr_offs_cnt_shd (0x00001390)*/
/*! Slice: mp_cr_offs_cnt:*/
#define MP_CR_OFFS_CNT
#define MP_CR_OFFS_CNT_MASK 0x0FFFFFF0U
#define MP_CR_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mp_raw_base_ad_init (0x00001394)*/
/*! Slice: mp_raw_base_ad_init:*/
#define MP_RAW_BASE_AD_INIT
#define MP_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MP_RAW_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mp_raw_size_init (0x00001398)*/
/*! Slice: mp_raw_size_init:*/
#define MP_RAW_SIZE_INIT
#define MP_RAW_SIZE_INIT_MASK 0x1FFFFFF0U
#define MP_RAW_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mp_raw_offs_cnt_init (0x0000139c)*/
/*! Slice: mp_raw_offs_cnt_init:*/
#define MP_RAW_OFFS_CNT_INIT
#define MP_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define MP_RAW_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mp_raw_llength (0x000013a0)*/
/*! Slice: mp_raw_llengh:*/
#define MP_RAW_LLENGH
#define MP_RAW_LLENGH_MASK 0x00007FFFU
#define MP_RAW_LLENGH_SHIFT 0U
/*! Register: miv2_mp_raw_pic_width (0x000013a4)*/
/*! Slice: mp_raw_pic_width:*/
#define MP_RAW_PIC_WIDTH
#define MP_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MP_RAW_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mp_raw_pic_height (0x000013a8)*/
/*! Slice: mp_raw_pic_height:*/
#define MP_RAW_PIC_HEIGHT
#define MP_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MP_RAW_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_mp_raw_pic_size (0x000013ac)*/
/*! Slice: mp_raw_pic_size:*/
#define MP_RAW_PIC_SIZE
#define MP_RAW_PIC_SIZE_MASK 0xFFFFFFFFU
#define MP_RAW_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mp_raw_offs_cnt_start (0x000013b0)*/
/*! Slice: mp_raw_offs_cnt_start:*/
#define MP_RAW_OFFS_CNT_START
#define MP_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define MP_RAW_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mp_raw_base_ad_shd (0x000013b4)*/
/*! Slice: mp_raw_base_ad:*/
#define MP_RAW_BASE_AD
#define MP_RAW_BASE_AD_MASK 0xFFFFFFF0U
#define MP_RAW_BASE_AD_SHIFT 4U
/*! Register: miv2_mp_raw_size_shd (0x000013b8)*/
/*! Slice: mp_raw_size:*/
#define MP_RAW_SIZE
#define MP_RAW_SIZE_MASK 0x1FFFFFF0U
#define MP_RAW_SIZE_SHIFT 4U
/*! Register: miv2_mp_raw_offs_cnt_shd (0x000013bc)*/
/*! Slice: mp_raw_offs_cnt:*/
#define MP_RAW_OFFS_CNT
#define MP_RAW_OFFS_CNT_MASK 0x1FFFFFF0U
#define MP_RAW_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mp_jdp_base_ad_init (0x000013c0)*/
/*! Slice: mp_jdp_base_ad_init:*/
#define MP_JDP_BASE_AD_INIT
#define MP_JDP_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MP_JDP_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mp_jdp_size_init (0x000013c4)*/
/*! Slice: mp_jdp_size_init:*/
#define MP_JDP_SIZE_INIT
#define MP_JDP_SIZE_INIT_MASK 0x1FFFFFF0U
#define MP_JDP_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mp_jdp_offs_cnt_init (0x000013c8)*/
/*! Slice: mp_jdp_offs_cnt_init:*/
#define MP_JDP_OFFS_CNT_INIT
#define MP_JDP_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define MP_JDP_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mp_jdp_llength (0x000013cc)*/
/*! Slice: mp_jdp_llengh:*/
#define MP_JDP_LLENGH
#define MP_JDP_LLENGH_MASK 0x00007FFFU
#define MP_JDP_LLENGH_SHIFT 0U
/*! Register: miv2_mp_jdp_pic_width (0x000013d0)*/
/*! Slice: mp_jdp_pic_width:*/
#define MP_JDP_PIC_WIDTH
#define MP_JDP_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MP_JDP_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mp_jdp_pic_height (0x000013d4)*/
/*! Slice: mp_jdp_pic_height:*/
#define MP_JDP_PIC_HEIGHT
#define MP_JDP_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MP_JDP_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_mp_jdp_pic_size (0x000013d8)*/
/*! Slice: mp_jdp_pic_size:*/
#define MP_JDP_PIC_SIZE
#define MP_JDP_PIC_SIZE_MASK 0xFFFFFFFFU
#define MP_JDP_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mp_jdp_offs_cnt_start (0x000013dc)*/
/*! Slice: mp_jdp_offs_cnt_start:*/
#define MP_JDP_OFFS_CNT_START
#define MP_JDP_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define MP_JDP_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mp_jdp_base_ad_shd (0x000013e0)*/
/*! Slice: mp_jdp_base_ad:*/
#define MP_JDP_BASE_AD
#define MP_JDP_BASE_AD_MASK 0xFFFFFFF0U
#define MP_JDP_BASE_AD_SHIFT 4U
/*! Register: miv2_mp_jdp_size_shd (0x000013e4)*/
/*! Slice: mp_jdp_size:*/
#define MP_JDP_SIZE
#define MP_JDP_SIZE_MASK 0x1FFFFFF0U
#define MP_JDP_SIZE_SHIFT 4U
/*! Register: miv2_mp_jdp_offs_cnt_shd (0x000013e8)*/
/*! Slice: mp_jdp_offs_cnt:*/
#define MP_JDP_OFFS_CNT
#define MP_JDP_OFFS_CNT_MASK 0x1FFFFFF0U
#define MP_JDP_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mp_status_clr (0x000013ec) */
/*! Slice: mp_jdp_fifo_full: */
#define MP_JDP_FIFO_FULL
#define MP_JDP_FIFO_FULL_MASK 0x00000010U
#define MP_JDP_FIFO_FULL_SHIFT 4U
/*! Slice: mp_raw_fifo_full:*/
#define MP_RAW_FIFO_FULL
#define MP_RAW_FIFO_FULL_MASK 0x00000008U
#define MP_RAW_FIFO_FULL_SHIFT 3U
/*! Slice: mp_cr_fifo_full:*/
#define MP_CR_FIFO_FULL
#define MP_CR_FIFO_FULL_MASK 0x00000004U
#define MP_CR_FIFO_FULL_SHIFT 2U
/*! Slice: mp_cb_fifo_full:*/
#define MP_CB_FIFO_FULL
#define MP_CB_FIFO_FULL_MASK 0x00000002U
#define MP_CB_FIFO_FULL_SHIFT 1U
/*! Slice: mp_y_fifo_full:*/
#define MP_Y_FIFO_FULL
#define MP_Y_FIFO_FULL_MASK 0x00000001U
#define MP_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_mp_ctrl_status (0x000013f0) */
/*! Slice: mp_jdp_fifo_full: */
#define MP_JDP_FIFO_FULL
#define MP_JDP_FIFO_FULL_MASK 0x00000010U
#define MP_JDP_FIFO_FULL_SHIFT 4U
/*! Slice: mp_raw_fifo_full: */
#define MP_RAW_FIFO_FULL
#define MP_RAW_FIFO_FULL_MASK 0x00000008U
#define MP_RAW_FIFO_FULL_SHIFT 3U
/*! Slice: mp_cr_fifo_full: */
#define MP_CR_FIFO_FULL
#define MP_CR_FIFO_FULL_MASK 0x00000004U
#define MP_CR_FIFO_FULL_SHIFT 2U
/*! Slice: mp_cb_fifo_full: */
#define MP_CB_FIFO_FULL
#define MP_CB_FIFO_FULL_MASK 0x00000002U
#define MP_CB_FIFO_FULL_SHIFT 1U
/*! Slice: mp_y_fifo_full: */
#define MP_Y_FIFO_FULL
#define MP_Y_FIFO_FULL_MASK 0x00000001U
#define MP_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_mp_axi_status (0x000013f4) */
/*! Slice: agsw_enc_pic_rdy: */
#define AGSW_ENC_PIC_RDY
#define AGSW_ENC_PIC_RDY_MASK 0x00000002U
#define AGSW_ENC_PIC_RDY_SHIFT 1U
/*! Slice: agsw_enc_buf_full:*/
#define AGSW_ENC_BUF_FULL
#define AGSW_ENC_BUF_FULL_MASK 0x00000001U
#define AGSW_ENC_BUF_FULL_SHIFT 0U
/*! Register: miv2_mp_raw_byte_cnt_status (0x000013f8)*/
/*! Slice: mp_raw_byte_cnt_status:*/
#define MP_RAW_BYTE_CNT_STATUS
#define MP_RAW_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
#define MP_RAW_BYTE_CNT_STATUS_SHIFT 0U
/*! Register: miv2_mp_jdp_byte_cnt_status (0x000013fc)*/
/*! Slice: mp_jdp_byte_cnt_status:*/
#define MP_JDP_BYTE_CNT_STATUS
#define MP_JDP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
#define MP_JDP_BYTE_CNT_STATUS_SHIFT 0U
/*! Register: miv2_mp_dp_byte_cnt_status (0x00001400)*/
/*! Slice: mp_dp_byte_cnt_status:*/
#define MP_DP_BYTE_CNT_STATUS
#define MP_DP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
#define MP_DP_BYTE_CNT_STATUS_SHIFT 0U
/*! Register: miv2_sp1_ctrl (0x0000142c)*/
/*! Slice: sp1_init_offset_en:*/
#define SP1_INIT_OFFSET_EN
#define SP1_INIT_OFFSET_EN_MASK 0x00000020U
#define SP1_INIT_OFFSET_EN_SHIFT 5U
/*! Slice: sp1_init_base_en:*/
#define SP1_INIT_BASE_EN
#define SP1_INIT_BASE_EN_MASK 0x00000010U
#define SP1_INIT_BASE_EN_SHIFT 4U
/*! Slice: sp1_miv2_cfg_upd:*/
#define SP1_MI_CFG_UPD
#define SP1_MI_CFG_UPD_MASK 0x00000008U
#define SP1_MI_CFG_UPD_SHIFT 3U
/*! Slice: sp1_miv2_skip:*/
#define SP1_MI_SKIP
#define SP1_MI_SKIP_MASK 0x00000004U
#define SP1_MI_SKIP_SHIFT 2U
/*! Slice: sp1_auto_update:*/
#define SP1_AUTO_UPDATE
#define SP1_AUTO_UPDATE_MASK 0x00000002U
#define SP1_AUTO_UPDATE_SHIFT 1U
/*! Slice: sp1_pingpong_enable:*/
#define SP1_PINGPONG_ENABLE
#define SP1_PINGPONG_ENABLE_MASK 0x00000001U
#define SP1_PINGPONG_ENABLE_SHIFT 0U
/*! Register: miv2_sp1_fmt (0x00001430)*/
/*! Slice: sp1_wr_yuv_nvy:*/
#define SP1_WR_YUV_NVY
#define SP1_WR_YUV_NVY_MASK 0x00000180U
#define SP1_WR_YUV_NVY_SHIFT 7U
/*! Slice: sp1_wr_yuv_nv21:*/
#define SP1_WR_YUV_NV21
#define SP1_WR_YUV_NV21_MASK 0x00000040U
#define SP1_WR_YUV_NV21_SHIFT 6U
/*! Slice: sp1_wr_yuv_aligned:*/
#define SP1_WR_YUV_ALIGNED
#define SP1_WR_YUV_ALIGNED_MASK 0x00000020U
#define SP1_WR_YUV_ALIGNED_SHIFT 5U
/*! Slice: sp1_wr_yuv_str:*/
#define SP1_WR_YUV_STR
#define SP1_WR_YUV_STR_MASK 0x00000018U
#define SP1_WR_YUV_STR_SHIFT 3U
/*! Slice: sp1_wr_yuv_fmt:*/
#define SP1_WR_YUV_FMT
#define SP1_WR_YUV_FMT_MASK 0x00000006U
#define SP1_WR_YUV_FMT_SHIFT 1U
/*! Slice: sp1_wr_yuv_bit:*/
#define SP1_WR_YUV_BIT
#define SP1_WR_YUV_BIT_MASK 0x00000001U
#define SP1_WR_YUV_BIT_SHIFT 0U
/*! Register: miv2_sp1_bus_cfg (0x00001434)*/
/*! Slice: sp1_wr_swap_v:*/
#define SP1_WR_SWAP_V
#define SP1_WR_SWAP_V_MASK 0x000F0000U
#define SP1_WR_SWAP_V_SHIFT 16U
/*! Slice: sp1_wr_swap_u:*/
#define SP1_WR_SWAP_U
#define SP1_WR_SWAP_U_MASK 0x0000F000U
#define SP1_WR_SWAP_U_SHIFT 12U
/*! Slice: sp1_wr_swap_y:*/
#define SP1_WR_SWAP_Y
#define SP1_WR_SWAP_Y_MASK 0x00000F00U
#define SP1_WR_SWAP_Y_SHIFT 8U
/*! Slice: sp1_rd_issue_cap:*/
#define SP1_RD_ISSUE_CAP
#define SP1_RD_ISSUE_CAP_MASK 0x000000C0U
#define SP1_RD_ISSUE_CAP_SHIFT 6U
/*! Slice: sp1_wr_issue_cap:*/
#define SP1_WR_ISSUE_CAP
#define SP1_WR_ISSUE_CAP_MASK 0x00000030U
#define SP1_WR_ISSUE_CAP_SHIFT 4U
/*! Slice: sp1_rd_burst_len:*/
#define SP1_RD_BURST_LEN
#define SP1_RD_BURST_LEN_MASK 0x0000000CU
#define SP1_RD_BURST_LEN_SHIFT 2U
/*! Slice: sp1_wr_burst_len:*/
#define SP1_WR_BURST_LEN
#define SP1_WR_BURST_LEN_MASK 0x00000003U
#define SP1_WR_BURST_LEN_SHIFT 0U
/*! Register: miv2_sp1_bus_id (0x00001438)*/
/*! Slice: sp1_bus_sw_en:*/
#define SP1_BUS_SW_EN
#define SP1_BUS_SW_EN_MASK 0x02000000U
#define SP1_BUS_SW_EN_SHIFT 25U

/*! Slice: sp1_rd_id_en:*/
#define SP1_RD_ID_EN
#define SP1_RD_ID_EN_MASK 0x01000000U
#define SP1_RD_ID_EN_SHIFT 24U
/*! Slice: sp1_rd_id_cfg:*/
#define SP1_RD_ID_CFG
#define SP1_RD_ID_CFG_MASK 0x00FF0000U
#define SP1_RD_ID_CFG_SHIFT 16U
/*! Slice: sp1_wr_id_en:*/
#define SP1_WR_ID_EN
#define SP1_WR_ID_EN_MASK 0x00000100U
#define SP1_WR_ID_EN_SHIFT 8U
/*! Slice: sp1_wr_id_cfg:*/
#define SP1_WR_ID_CFG
#define SP1_WR_ID_CFG_MASK 0x000000FFU
#define SP1_WR_ID_CFG_SHIFT 0U
/*! Register: miv2_sp1_bus_timeo (0x0000143c)*/
/*! Slice: sp1_bus_timeo_en:*/
#define SP1_BUS_TIMEO_EN
#define SP1_BUS_TIMEO_EN_MASK 0x80000000U
#define SP1_BUS_TIMEO_EN_SHIFT 31U
/*! Slice: sp1_bus_timeo:*/
#define SP1_BUS_TIMEO
#define SP1_BUS_TIMEO_MASK 0x7FFFFFFFU
#define SP1_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_sp1_y_base_ad_init (0x00001440)*/
/*! Slice: sp1_y_base_ad_init:*/
#define SP1_Y_BASE_AD_INIT
#define SP1_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP1_Y_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp1_y_size_init (0x00001444)*/
/*! Slice: sp1_y_size_init:*/
#define SP1_Y_SIZE_INIT
#define SP1_Y_SIZE_INIT_MASK 0x1FFFFFF0U
#define SP1_Y_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp1_y_offs_cnt_init (0x00001448)*/
/*! Slice: sp1_y_offs_cnt_init:*/
#define SP1_Y_OFFS_CNT_INIT
#define SP1_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define SP1_Y_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp1_y_llength (0x0000144c)*/
/*! Slice: sp1_y_llengh:*/
#define SP1_Y_LLENGH
#define SP1_Y_LLENGH_MASK 0x00007FFFU
#define SP1_Y_LLENGH_SHIFT 0U
/*! Register: miv2_sp1_y_pic_width (0x00001450)*/
/*! Slice: sp1_y_pic_width:*/
#define SP1_Y_PIC_WIDTH
#define SP1_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
#define SP1_Y_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_sp1_y_pic_height (0x00001454)*/
/*! Slice: sp1_y_pic_height:*/
#define SP1_Y_PIC_HEIGHT
#define SP1_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define SP1_Y_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_sp1_y_pic_size (0x00001458)*/
/*! Slice: sp1_y_pic_size:*/
#define SP1_Y_PIC_SIZE
#define SP1_Y_PIC_SIZE_MASK 0xFFFFFFFFU
#define SP1_Y_PIC_SIZE_SHIFT 0U
/*! Register: miv2_sp1_cb_base_ad_init (0x0000145c)*/
/*! Slice: sp1_cb_base_ad_init:*/
#define SP1_CB_BASE_AD_INIT
#define SP1_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP1_CB_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp1_cb_size_init (0x00001460)*/
/*! Slice: sp1_cb_size_init:*/
#define SP1_CB_SIZE_INIT
#define SP1_CB_SIZE_INIT_MASK 0x0FFFFFF0U
#define SP1_CB_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp1_cb_offs_cnt_init (0x00001464)*/
/*! Slice: sp1_cb_offs_cnt_init:*/
#define SP1_CB_OFFS_CNT_INIT
#define SP1_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define SP1_CB_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp1_cr_base_ad_init (0x00001468)*/
/*! Slice: sp1_cr_base_ad_init:*/
#define SP1_CR_BASE_AD_INIT
#define SP1_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP1_CR_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp1_cr_size_init (0x0000146c)*/
/*! Slice: sp1_cr_size_init:*/
#define SP1_CR_SIZE_INIT
#define SP1_CR_SIZE_INIT_MASK 0x0FFFFFF0U
#define SP1_CR_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp1_cr_offs_cnt_init (0x00001470)*/
/*! Slice: sp1_cr_offs_cnt_init:*/
#define SP1_CR_OFFS_CNT_INIT
#define SP1_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define SP1_CR_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp1_y_base_ad_init2 (0x00001474)*/
/*! Slice: sp1_y_base_ad_init2:*/
#define SP1_Y_BASE_AD_INIT2
#define SP1_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP1_Y_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp1_cb_base_ad_init2 (0x00001478)*/
/*! Slice: sp1_cb_base_ad_init2:*/
#define SP1_CB_BASE_AD_INIT2
#define SP1_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP1_CB_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp1_cr_base_ad_init2 (0x0000147c)*/
/*! Slice: sp1_cr_base_ad_init2:*/
#define SP1_CR_BASE_AD_INIT2
#define SP1_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP1_CR_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp1_y_offs_cnt_start (0x00001480)*/
/*! Slice: sp1_y_offs_cnt_start:*/
#define SP1_Y_OFFS_CNT_START
#define SP1_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define SP1_Y_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp1_cb_offs_cnt_start (0x00001484)*/
/*! Slice: sp1_cb_offs_cnt_start:*/
#define SP1_CB_OFFS_CNT_START
#define SP1_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define SP1_CB_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp1_cr_offs_cnt_start (0x00001488)*/
/*! Slice: sp1_cr_offs_cnt_start:*/
#define SP1_CR_OFFS_CNT_START
#define SP1_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define SP1_CR_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp1_y_base_ad_shd (0x0000148c)*/
/*! Slice: sp1_y_base_ad:*/
#define SP1_Y_BASE_AD
#define SP1_Y_BASE_AD_MASK 0xFFFFFFF0U
#define SP1_Y_BASE_AD_SHIFT 4U
/*! Register: miv2_sp1_y_size_shd (0x00001490)*/
/*! Slice: sp1_y_size:*/
#define SP1_Y_SIZE
#define SP1_Y_SIZE_MASK 0x1FFFFFF0U
#define SP1_Y_SIZE_SHIFT 4U
/*! Register: miv2_sp1_y_offs_cnt_shd (0x00001494)*/
/*! Slice: sp1_y_offs_cnt:*/
#define SP1_Y_OFFS_CNT
#define SP1_Y_OFFS_CNT_MASK 0x1FFFFFF0U
#define SP1_Y_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp1_cb_base_ad_shd (0x00001498)*/
/*! Slice: sp1_cb_base_ad:*/
#define SP1_CB_BASE_AD
#define SP1_CB_BASE_AD_MASK 0xFFFFFFF0U
#define SP1_CB_BASE_AD_SHIFT 4U
/*! Register: miv2_sp1_cb_size_shd (0x0000149c)*/
/*! Slice: sp1_cb_size:*/
#define SP1_CB_SIZE
#define SP1_CB_SIZE_MASK 0x0FFFFFF0U
#define SP1_CB_SIZE_SHIFT 4U
/*! Register: miv2_sp1_cb_offs_cnt_shd (0x000014a0)*/
/*! Slice: sp1_cb_offs_cnt:*/
#define SP1_CB_OFFS_CNT
#define SP1_CB_OFFS_CNT_MASK 0x0FFFFFF0U
#define SP1_CB_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp1_cr_base_ad_shd (0x000014a4)*/
/*! Slice: sp1_cr_base_ad:*/
#define SP1_CR_BASE_AD
#define SP1_CR_BASE_AD_MASK 0xFFFFFFF0U
#define SP1_CR_BASE_AD_SHIFT 4U
/*! Register: miv2_sp1_cr_size_shd (0x000014a8)*/
/*! Slice: sp1_cr_size:*/
#define SP1_CR_SIZE
#define SP1_CR_SIZE_MASK 0x0FFFFFF0U
#define SP1_CR_SIZE_SHIFT 4U
/*! Register: miv2_sp1_cr_offs_cnt_shd (0x000014ac)*/
/*! Slice: sp1_cr_offs_cnt:*/
#define SP1_CR_OFFS_CNT
#define SP1_CR_OFFS_CNT_MASK 0x0FFFFFF0U
#define SP1_CR_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp1_status_clr (0x000014b0)*/
/*! Slice: sp1_cr_fifo_full:*/
#define SP1_CR_FIFO_FULL
#define SP1_CR_FIFO_FULL_MASK 0x00000004U
#define SP1_CR_FIFO_FULL_SHIFT 2U
/*! Slice: sp1_cb_fifo_full:*/
#define SP1_CB_FIFO_FULL
#define SP1_CB_FIFO_FULL_MASK 0x00000002U
#define SP1_CB_FIFO_FULL_SHIFT 1U
/*! Slice: sp1_y_fifo_full:*/
#define SP1_Y_FIFO_FULL
#define SP1_Y_FIFO_FULL_MASK 0x00000001U
#define SP1_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_sp1_ctrl_status (0x000014b4)*/
/*! Slice: sp1_cr_fifo_full:*/
#define SP1_CR_FIFO_FULL
#define SP1_CR_FIFO_FULL_MASK 0x00000004U
#define SP1_CR_FIFO_FULL_SHIFT 2U
/*! Slice: sp1_cb_fifo_full:*/
#define SP1_CB_FIFO_FULL
#define SP1_CB_FIFO_FULL_MASK 0x00000002U
#define SP1_CB_FIFO_FULL_SHIFT 1U
/*! Slice: sp1_y_fifo_full:*/
#define SP1_Y_FIFO_FULL
#define SP1_Y_FIFO_FULL_MASK 0x00000001U
#define SP1_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_sp1_axi_status (0x000014b8)*/
/*! Slice: agsw_enc_pic_rdy:*/
#define AGSW_ENC_PIC_RDY
#define AGSW_ENC_PIC_RDY_MASK 0x00000002U
#define AGSW_ENC_PIC_RDY_SHIFT 1U
/*! Slice: agsw_enc_buf_full:*/
#define AGSW_ENC_BUF_FULL
#define AGSW_ENC_BUF_FULL_MASK 0x00000001U
#define AGSW_ENC_BUF_FULL_SHIFT 0U
/*! Register: miv2_sp2_ctrl (0x000014e4)*/
/*! Slice: sp2_rd_raw_cfg_update */
#define SP2_RD_RAW_CFG_UPDATE
#define SP2_RD_RAW_CFG_UPDATE_MASK 0x00000200U
#define SP2_RD_RAW_CFG_UPDATE_SHIFT 9U
/*! Slice: sp2_rd_raw_auto_update */
#define SP2_RD_RAW_AUTO_UPDATE
#define SP2_RD_RAW_AUTO_UPDATE_MASK 0x00000100U
#define SP2_RD_RAW_AUTO_UPDATE_SHIFT 8U
/*! Slice: sp2_rd_yuv_cfg_update */
#define SP2_RD_YUV_CFG_UPDATE
#define SP2_RD_YUV_CFG_UPDATE_MASK 0x00000080U
#define SP2_RD_YUV_CFG_UPDATE_SHIFT 7U
/*! Slice: sp2_rd_yuv_auto_update */
#define SP2_RD_YUV_AUTO_UPDATE
#define SP2_RD_YUV_AUTO_UPDATE_MASK 0x00000040U
#define SP2_RD_YUV_AUTO_UPDATE_SHIFT 6U
/*! Slice: sp2_init_offset_en:*/
#define SP2_INIT_OFFSET_EN
#define SP2_INIT_OFFSET_EN_MASK 0x00000020U
#define SP2_INIT_OFFSET_EN_SHIFT 5U
/*! Slice: sp2_init_base_en:*/
#define SP2_INIT_BASE_EN
#define SP2_INIT_BASE_EN_MASK 0x00000010U
#define SP2_INIT_BASE_EN_SHIFT 4U
/*! Slice: sp2_miv2_cfg_upd:*/
#define SP2_MI_CFG_UPD
#define SP2_MI_CFG_UPD_MASK 0x00000008U
#define SP2_MI_CFG_UPD_SHIFT 3U
/*! Slice: sp2_miv2_skip:*/
#define SP2_MI_SKIP
#define SP2_MI_SKIP_MASK 0x00000004U
#define SP2_MI_SKIP_SHIFT 2U
/*! Slice: sp2_auto_update:*/
#define SP2_AUTO_UPDATE
#define SP2_AUTO_UPDATE_MASK 0x00000002U
#define SP2_AUTO_UPDATE_SHIFT 1U
/*! Slice: sp2_pingpong_enable:*/
#define SP2_PINGPONG_ENABLE
#define SP2_PINGPONG_ENABLE_MASK 0x00000001U
#define SP2_PINGPONG_ENABLE_SHIFT 0U
/*! Register: miv2_sp2_fmt (0x000014e8)*/
/*! Slice: sp2_rd_yuv_nvy:*/
#define SP2_RD_YUV_NVY
#define SP2_RD_YUV_NVY_MASK 0x0C000000U
#define SP2_RD_YUV_NVY_SHIFT 26U
/*! Slice: sp2_rd_yuv_nv21:*/
#define SP2_RD_YUV_NV21
#define SP2_RD_YUV_NV21_MASK 0x02000000U
#define SP2_RD_YUV_NV21_SHIFT 25U
/*! Slice: sp2_rd_raw_aligned:*/
#define SP2_RD_RAW_ALIGNED
#define SP2_RD_RAW_ALIGNED_MASK 0x01800000U
#define SP2_RD_RAW_ALIGNED_SHIFT 23U
/*! Slice: sp2_rd_yuv_aligned:*/
#define SP2_RD_YUV_ALIGNED
#define SP2_RD_YUV_ALIGNED_MASK 0x00400000U
#define SP2_RD_YUV_ALIGNED_SHIFT 22U
/*! Slice: sp2_rd_raw_bit:*/
#define SP2_RD_RAW_BIT
#define SP2_RD_RAW_BIT_MASK 0x00380000U
#define SP2_RD_RAW_BIT_SHIFT 19U
/*! Slice: sp2_rd_yuv_str:*/
#define SP2_RD_YUV_STR
#define SP2_RD_YUV_STR_MASK 0x00060000U
#define SP2_RD_YUV_STR_SHIFT 17U
/*! Slice: sp2_rd_yuv_fmt:*/
#define SP2_RD_YUV_FMT
#define SP2_RD_YUV_FMT_MASK 0x00018000U
#define SP2_RD_YUV_FMT_SHIFT 15U
/*! Slice: sp2_rd_yuv_bit:*/
#define SP2_RD_YUV_BIT
#define SP2_RD_YUV_BIT_MASK 0x00004000U
#define SP2_RD_YUV_BIT_SHIFT 14U
/*! Slice: sp2_wr_yuv_nvy:*/
#define SP2_WR_YUV_NVY
#define SP2_WR_YUV_NVY_MASK 0x00003000U
#define SP2_WR_YUV_NVY_SHIFT 12U
/*! Slice: sp2_wr_yuv_nv21:*/
#define SP2_WR_YUV_NV21
#define SP2_WR_YUV_NV21_MASK 0x00000800U
#define SP2_WR_YUV_NV21_SHIFT 11U
/*! Slice: sp2_wr_raw_aligned:*/
#define SP2_WR_RAW_ALIGNED
#define SP2_WR_RAW_ALIGNED_MASK 0x00000600U
#define SP2_WR_RAW_ALIGNED_SHIFT 9U
/*! Slice: sp2_wr_yuv_aligned:*/
#define SP2_WR_YUV_ALIGNED
#define SP2_WR_YUV_ALIGNED_MASK 0x00000100U
#define SP2_WR_YUV_ALIGNED_SHIFT 8U
/*! Slice: sp2_wr_raw_bit:*/
#define SP2_WR_RAW_BIT
#define SP2_WR_RAW_BIT_MASK 0x000000E0U
#define SP2_WR_RAW_BIT_SHIFT 5U
/*! Slice: sp2_wr_yuv_str:*/
#define SP2_WR_YUV_STR
#define SP2_WR_YUV_STR_MASK 0x00000018U
#define SP2_WR_YUV_STR_SHIFT 3U
/*! Slice: sp2_wr_yuv_fmt:*/
#define SP2_WR_YUV_FMT
#define SP2_WR_YUV_FMT_MASK 0x00000006U
#define SP2_WR_YUV_FMT_SHIFT 1U
/*! Slice: sp2_wr_yuv_bit:*/
#define SP2_WR_YUV_BIT
#define SP2_WR_YUV_BIT_MASK 0x00000001U
#define SP2_WR_YUV_BIT_SHIFT 0U
/*! Register: miv2_sp2_bus_cfg (0x000014ec)*/
/*! Slice: sp2_rd_swap_raw:*/
#define SP2_RD_SWAP_RAW
#define SP2_RD_SWAP_RAW_MASK 0xF0000000U
#define SP2_RD_SWAP_RAW_SHIFT 28U
/*! Slice: sp2_rd_swap_v:*/
#define SP2_RD_SWAP_V
#define SP2_RD_SWAP_V_MASK 0x0F000000U
#define SP2_RD_SWAP_V_SHIFT 24U
/*! Slice: sp2_rd_swap_u:*/
#define SP2_RD_SWAP_U
#define SP2_RD_SWAP_U_MASK 0x00F00000U
#define SP2_RD_SWAP_U_SHIFT 20U
/*! Slice: sp2_rd_swap_y:*/
#define SP2_RD_SWAP_Y
#define SP2_RD_SWAP_Y_MASK 0x000F0000U
#define SP2_RD_SWAP_Y_SHIFT 16U
/*! Slice: sp2_wr_swap_raw:*/
#define SP2_WR_SWAP_RAW
#define SP2_WR_SWAP_RAW_MASK 0x0000F000U
#define SP2_WR_SWAP_RAW_SHIFT 12U
/*! Slice: sp2_wr_swap_v:*/
#define SP2_WR_SWAP_V
#define SP2_WR_SWAP_V_MASK 0x00000F00U
#define SP2_WR_SWAP_V_SHIFT 8U
/*! Slice: sp2_wr_swap_u:*/
#define SP2_WR_SWAP_U
#define SP2_WR_SWAP_U_MASK 0x000000F0U
#define SP2_WR_SWAP_U_SHIFT 4U
/*! Slice: sp2_wr_swap_y:*/
#define SP2_WR_SWAP_Y
#define SP2_WR_SWAP_Y_MASK 0x0000000FU
#define SP2_WR_SWAP_Y_SHIFT 0U
/*! Register: miv2_sp2_bus_id (0x000014f0)*/
/*! Slice: sp2_bus_sw_en:*/
#define SP2_BUS_SW_EN
#define SP2_BUS_SW_EN_MASK 0x08000000U
#define SP2_BUS_SW_EN_SHIFT 27U
/*! Slice: sp2_rd_issue_cap:*/
#define SP2_RD_ISSUE_CAP
#define SP2_RD_ISSUE_CAP_MASK 0x06000000U
#define SP2_RD_ISSUE_CAP_SHIFT 25U
/*! Slice: sp2_wr_issue_cap:*/
#define SP2_WR_ISSUE_CAP
#define SP2_WR_ISSUE_CAP_MASK 0x01800000U
#define SP2_WR_ISSUE_CAP_SHIFT 23U
/*! Slice: sp2_rd_burst_len:*/
#define SP2_RD_BURST_LEN
#define SP2_RD_BURST_LEN_MASK 0x00600000U
#define SP2_RD_BURST_LEN_SHIFT 21U
/*! Slice: sp2_wr_burst_len:*/
#define SP2_WR_BURST_LEN
#define SP2_WR_BURST_LEN_MASK 0x00180000U
#define SP2_WR_BURST_LEN_SHIFT 19U
/*! Slice: sp2_rd_id_en:*/
#define SP2_RD_ID_EN
#define SP2_RD_ID_EN_MASK 0x00040000U
#define SP2_RD_ID_EN_SHIFT 18U
/*! Slice: sp2_rd_id_cfg:*/
#define SP2_RD_ID_CFG
#define SP2_RD_ID_CFG_MASK 0x0003FC00U
#define SP2_RD_ID_CFG_SHIFT 10U
/*! Slice: sp2_wr_id_en:*/
#define SP2_WR_ID_EN
#define SP2_WR_ID_EN_MASK 0x00000100U
#define SP2_WR_ID_EN_SHIFT 8U
/*! Slice: sp2_wr_id_cfg:*/
#define SP2_WR_ID_CFG
#define SP2_WR_ID_CFG_MASK 0x000000FFU
#define SP2_WR_ID_CFG_SHIFT 0U
/*! Register: miv2_sp2_bus_timeo (0x000014f4)*/
/*! Slice: sp2_bus_timeo_en:*/
#define SP2_BUS_TIMEO_EN
#define SP2_BUS_TIMEO_EN_MASK 0x80000000U
#define SP2_BUS_TIMEO_EN_SHIFT 31U
/*! Slice: sp2_bus_timeo:*/
#define SP2_BUS_TIMEO
#define SP2_BUS_TIMEO_MASK 0x7FFFFFFFU
#define SP2_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_sp2_y_base_ad_init (0x000014f8)*/
/*! Slice: sp2_y_base_ad_init:*/
#define SP2_Y_BASE_AD_INIT
#define SP2_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP2_Y_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp2_y_size_init (0x000014fc)*/
/*! Slice: sp2_y_size_init:*/
#define SP2_Y_SIZE_INIT
#define SP2_Y_SIZE_INIT_MASK 0x1FFFFFF0U
#define SP2_Y_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp2_y_offs_cnt_init (0x00001500)*/
/*! Slice: sp2_y_offs_cnt_init:*/
#define SP2_Y_OFFS_CNT_INIT
#define SP2_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define SP2_Y_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp2_y_llength (0x00001504)*/
/*! Slice: sp2_y_llengh:*/
#define SP2_Y_LLENGH
#define SP2_Y_LLENGH_MASK 0x00007FFFU
#define SP2_Y_LLENGH_SHIFT 0U
/*! Register: miv2_sp2_y_pic_width (0x00001508)*/
/*! Slice: sp2_y_pic_width:*/
#define SP2_Y_PIC_WIDTH
#define SP2_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
#define SP2_Y_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_sp2_y_pic_height (0x0000150c)*/
/*! Slice: sp2_y_pic_height:*/
#define SP2_Y_PIC_HEIGHT
#define SP2_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define SP2_Y_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_sp2_y_pic_size (0x00001510)*/
/*! Slice: sp2_y_pic_size:*/
#define SP2_Y_PIC_SIZE
#define SP2_Y_PIC_SIZE_MASK 0xFFFFFFFFU
#define SP2_Y_PIC_SIZE_SHIFT 0U
/*! Register: miv2_sp2_cb_base_ad_init (0x00001514)*/
/*! Slice: sp2_cb_base_ad_init:*/
#define SP2_CB_BASE_AD_INIT
#define SP2_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP2_CB_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp2_cb_size_init (0x00001518)*/
/*! Slice: sp2_cb_size_init:*/
#define SP2_CB_SIZE_INIT
#define SP2_CB_SIZE_INIT_MASK 0x0FFFFFF0U
#define SP2_CB_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp2_cb_offs_cnt_init (0x0000151c)*/
/*! Slice: sp2_cb_offs_cnt_init:*/
#define SP2_CB_OFFS_CNT_INIT
#define SP2_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define SP2_CB_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp2_cr_base_ad_init (0x00001520)*/
/*! Slice: sp2_cr_base_ad_init:*/
#define SP2_CR_BASE_AD_INIT
#define SP2_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP2_CR_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp2_cr_size_init (0x00001524)*/
/*! Slice: sp2_cr_size_init:*/
#define SP2_CR_SIZE_INIT
#define SP2_CR_SIZE_INIT_MASK 0x0FFFFFF0U
#define SP2_CR_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp2_cr_offs_cnt_init (0x00001528)*/
/*! Slice: sp2_cr_offs_cnt_init:*/
#define SP2_CR_OFFS_CNT_INIT
#define SP2_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
#define SP2_CR_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp2_y_base_ad_init2 (0x0000152c)*/
/*! Slice: sp2_y_base_ad_init2:*/
#define SP2_Y_BASE_AD_INIT2
#define SP2_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP2_Y_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp2_cb_base_ad_init2 (0x00001530)*/
/*! Slice: sp2_cb_base_ad_init2:*/
#define SP2_CB_BASE_AD_INIT2
#define SP2_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP2_CB_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp2_cr_base_ad_init2 (0x00001534)*/
/*! Slice: sp2_cr_base_ad_init2:*/
#define SP2_CR_BASE_AD_INIT2
#define SP2_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
#define SP2_CR_BASE_AD_INIT2_SHIFT 4U
/*! Register: miv2_sp2_y_offs_cnt_start (0x00001538)*/
/*! Slice: sp2_y_offs_cnt_start:*/
#define SP2_Y_OFFS_CNT_START
#define SP2_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define SP2_Y_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp2_cb_offs_cnt_start (0x0000153c)*/
/*! Slice: sp2_cb_offs_cnt_start:*/
#define SP2_CB_OFFS_CNT_START
#define SP2_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define SP2_CB_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp2_cr_offs_cnt_start (0x00001540)*/
/*! Slice: sp2_cr_offs_cnt_start:*/
#define SP2_CR_OFFS_CNT_START
#define SP2_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
#define SP2_CR_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp2_y_base_ad_shd (0x00001544)*/
/*! Slice: sp2_y_base_ad:*/
#define SP2_Y_BASE_AD
#define SP2_Y_BASE_AD_MASK 0xFFFFFFF0U
#define SP2_Y_BASE_AD_SHIFT 4U
/*! Register: miv2_sp2_y_size_shd (0x00001548)*/
/*! Slice: sp2_y_size:*/
#define SP2_Y_SIZE
#define SP2_Y_SIZE_MASK 0x1FFFFFF0U
#define SP2_Y_SIZE_SHIFT 4U
/*! Register: miv2_sp2_y_offs_cnt_shd (0x0000154c)*/
/*! Slice: sp2_y_offs_cnt:*/
#define SP2_Y_OFFS_CNT
#define SP2_Y_OFFS_CNT_MASK 0x1FFFFFF0U
#define SP2_Y_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp2_cb_base_ad_shd (0x00001550)*/
/*! Slice: sp2_cb_base_ad:*/
#define SP2_CB_BASE_AD
#define SP2_CB_BASE_AD_MASK 0xFFFFFFF0U
#define SP2_CB_BASE_AD_SHIFT 4U
/*! Register: miv2_sp2_cb_size_shd (0x00001554)*/
/*! Slice: sp2_cb_size:*/
#define SP2_CB_SIZE
#define SP2_CB_SIZE_MASK 0x0FFFFFF0U
#define SP2_CB_SIZE_SHIFT 4U
/*! Register: miv2_sp2_cb_offs_cnt_shd (0x00001558)*/
/*! Slice: sp2_cb_offs_cnt:*/
#define SP2_CB_OFFS_CNT
#define SP2_CB_OFFS_CNT_MASK 0x0FFFFFF0U
#define SP2_CB_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp2_cr_base_ad_shd (0x0000155c)*/
/*! Slice: sp2_cr_base_ad:*/
#define SP2_CR_BASE_AD
#define SP2_CR_BASE_AD_MASK 0xFFFFFFF0U
#define SP2_CR_BASE_AD_SHIFT 4U
/*! Register: miv2_sp2_cr_size_shd (0x00001560)*/
/*! Slice: sp2_cr_size:*/
#define SP2_CR_SIZE
#define SP2_CR_SIZE_MASK 0x0FFFFFF0U
#define SP2_CR_SIZE_SHIFT 4U
/*! Register: miv2_sp2_cr_offs_cnt_shd (0x00001564)*/
/*! Slice: sp2_cr_offs_cnt:*/
#define SP2_CR_OFFS_CNT
#define SP2_CR_OFFS_CNT_MASK 0x0FFFFFF0U
#define SP2_CR_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp2_raw_base_ad_init (0x00001568)*/
/*! Slice: sp2_raw_base_ad_init:*/
#define SP2_RAW_BASE_AD_INIT
#define SP2_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define SP2_RAW_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_sp2_raw_size_init (0x0000156c)*/
/*! Slice: sp2_raw_size_init:*/
#define SP2_RAW_SIZE_INIT
#define SP2_RAW_SIZE_INIT_MASK 0x1FFFFFF0U
#define SP2_RAW_SIZE_INIT_SHIFT 4U
/*! Register: miv2_sp2_raw_offs_cnt_init (0x00001570)*/
/*! Slice: sp2_raw_offs_cnt_init:*/
#define SP2_RAW_OFFS_CNT_INIT
#define SP2_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define SP2_RAW_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_sp2_raw_llength (0x00001574)*/
/*! Slice: sp2_raw_llengh:*/
#define SP2_RAW_LLENGH
#define SP2_RAW_LLENGH_MASK 0x00007FFFU
#define SP2_RAW_LLENGH_SHIFT 0U
/*! Register: miv2_sp2_raw_pic_width (0x00001578)*/
/*! Slice: sp2_raw_pic_width:*/
#define SP2_RAW_PIC_WIDTH
#define SP2_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU
#define SP2_RAW_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_sp2_raw_pic_height (0x0000157c)*/
/*! Slice: sp2_raw_pic_height:*/
#define SP2_RAW_PIC_HEIGHT
#define SP2_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define SP2_RAW_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_sp2_raw_pic_size (0x00001580)*/
/*! Slice: sp2_raw_pic_size:*/
#define SP2_RAW_PIC_SIZE
#define SP2_RAW_PIC_SIZE_MASK 0xFFFFFFFFU
#define SP2_RAW_PIC_SIZE_SHIFT 0U
/*! Register: miv2_sp2_raw_offs_cnt_start (0x00001584)*/
/*! Slice: sp2_raw_offs_cnt_start:*/
#define SP2_RAW_OFFS_CNT_START
#define SP2_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define SP2_RAW_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_sp2_raw_base_ad_shd (0x0000158c)*/
/*! Slice: sp2_raw_base_ad:*/
#define SP2_RAW_BASE_AD
#define SP2_RAW_BASE_AD_MASK 0xFFFFFFF0U
#define SP2_RAW_BASE_AD_SHIFT 4U
/*! Register: miv2_sp2_raw_size_shd (0x00001590)*/
/*! Slice: sp2_raw_size:*/
#define SP2_RAW_SIZE
#define SP2_RAW_SIZE_MASK 0x1FFFFFF0U
#define SP2_RAW_SIZE_SHIFT 4U
/*! Register: miv2_sp2_raw_offs_cnt_shd (0x00001594)*/
/*! Slice: sp2_raw_offs_cnt:*/
#define SP2_RAW_OFFS_CNT
#define SP2_RAW_OFFS_CNT_MASK 0x1FFFFFF0U
#define SP2_RAW_OFFS_CNT_SHIFT 4U
/*! Register: miv2_sp2_dma_y_pic_start_ad (0x00001598)*/
/*! Slice: sp2_dma_y_pic_start_ad:*/
#define SP2_DMA_Y_PIC_START_AD
#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_y_pic_width (0x0000159c)*/
/*! Slice: sp2_dma_y_pic_width:*/
#define SP2_DMA_Y_PIC_WIDTH
#define SP2_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU
#define SP2_DMA_Y_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_sp2_dma_y_pic_llength (0x000015a0)*/
/*! Slice: sp2_dma_y_pic_llength:*/
#define SP2_DMA_Y_PIC_LLENGTH
#define SP2_DMA_Y_PIC_LLENGTH_MASK 0x00007FFFU
#define SP2_DMA_Y_PIC_LLENGTH_SHIFT 0U
/*! Register: miv2_sp2_dma_y_pic_size (0x000015a4)*/
/*! Slice: sp2_dma_y_pic_size:*/
#define SP2_DMA_Y_PIC_SIZE
#define SP2_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU
#define SP2_DMA_Y_PIC_SIZE_SHIFT 0U
/*! Register: miv2_sp2_dma_cb_pic_start_ad (0x000015a8)*/
/*! Slice: sp2_dma_cb_pic_start_ad:*/
#define SP2_DMA_CB_PIC_START_AD
#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_cr_pic_start_ad (0x000015ac)*/
/*! Slice: sp2_dma_cr_pic_start_ad:*/
#define SP2_DMA_CR_PIC_START_AD
#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_y_pic_start_ad_shd (0x000015b0)*/
/*! Slice: sp2_dma_y_pic_start_ad:*/
#define SP2_DMA_Y_PIC_START_AD
#define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_Y_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_cb_pic_start_ad_shd (0x000015b4)*/
/*! Slice: sp2_dma_cb_pic_start_ad:*/
#define SP2_DMA_CB_PIC_START_AD
#define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_CB_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_cr_pic_start_ad_shd (0x000015b8)*/
/*! Slice: sp2_dma_cr_pic_start_ad:*/
#define SP2_DMA_CR_PIC_START_AD
#define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_CR_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_raw_pic_start_ad (0x000015bc)*/
/*! Slice: sp2_dma_raw_pic_start_ad:*/
#define SP2_DMA_RAW_PIC_START_AD
#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_dma_raw_pic_width (0x000015c0)*/
/*! Slice: sp2_dma_raw_pic_width:*/
#define SP2_DMA_RAW_PIC_WIDTH
#define SP2_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU
#define SP2_DMA_RAW_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_sp2_dma_raw_pic_llength (0x000015c4)*/
/*! Slice: sp2_dma_raw_pic_llength:*/
#define SP2_DMA_RAW_PIC_LLENGTH
#define SP2_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU
#define SP2_DMA_RAW_PIC_LLENGTH_SHIFT 0U
/*! Register: miv2_sp2_dma_raw_pic_size (0x000015c8)*/
/*! Slice: sp2_dma_raw_pic_size:*/
#define SP2_DMA_RAW_PIC_SIZE
#define SP2_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU
#define SP2_DMA_RAW_PIC_SIZE_SHIFT 0U
/*! Register: miv2_sp2_dma_raw_pic_start_ad_shd (0x000015cc)*/
/*! Slice: sp2_dma_raw_pic_start_ad:*/
#define SP2_DMA_RAW_PIC_START_AD
#define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
#define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U
/*! Register: miv2_sp2_status_clr (0x000015d0)*/
/*! Slice: sp2_jdp_fifo_full:*/
#define SP2_JDP_FIFO_FULL
#define SP2_JDP_FIFO_FULL_MASK 0x00000010U
#define SP2_JDP_FIFO_FULL_SHIFT 4U
/*! Slice: sp2_raw_fifo_full:*/
#define SP2_RAW_FIFO_FULL
#define SP2_RAW_FIFO_FULL_MASK 0x00000008U
#define SP2_RAW_FIFO_FULL_SHIFT 3U
/*! Slice: sp2_cr_fifo_full:*/
#define SP2_CR_FIFO_FULL
#define SP2_CR_FIFO_FULL_MASK 0x00000004U
#define SP2_CR_FIFO_FULL_SHIFT 2U
/*! Slice: sp2_cb_fifo_full:*/
#define SP2_CB_FIFO_FULL
#define SP2_CB_FIFO_FULL_MASK 0x00000002U
#define SP2_CB_FIFO_FULL_SHIFT 1U
/*! Slice: sp2_y_fifo_full:*/
#define SP2_Y_FIFO_FULL
#define SP2_Y_FIFO_FULL_MASK 0x00000001U
#define SP2_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_sp2_ctrl_status (0x000015d4)*/
/*! Slice: sp2_jdp_fifo_full:*/
#define SP2_JDP_FIFO_FULL
#define SP2_JDP_FIFO_FULL_MASK 0x00000010U
#define SP2_JDP_FIFO_FULL_SHIFT 4U
/*! Slice: sp2_raw_fifo_full:*/
#define SP2_RAW_FIFO_FULL
#define SP2_RAW_FIFO_FULL_MASK 0x00000008U
#define SP2_RAW_FIFO_FULL_SHIFT 3U
/*! Slice: sp2_cr_fifo_full:*/
#define SP2_CR_FIFO_FULL
#define SP2_CR_FIFO_FULL_MASK 0x00000004U
#define SP2_CR_FIFO_FULL_SHIFT 2U
/*! Slice: sp2_cb_fifo_full:*/
#define SP2_CB_FIFO_FULL
#define SP2_CB_FIFO_FULL_MASK 0x00000002U
#define SP2_CB_FIFO_FULL_SHIFT 1U
/*! Slice: sp2_y_fifo_full:*/
#define SP2_Y_FIFO_FULL
#define SP2_Y_FIFO_FULL_MASK 0x00000001U
#define SP2_Y_FIFO_FULL_SHIFT 0U
/*! Register: miv2_sp2_axi_status (0x000015d8)*/
/*! Slice: agsw_enc_pic_rdy:*/
#define AGSW_ENC_PIC_RDY
#define AGSW_ENC_PIC_RDY_MASK 0x00000002U
#define AGSW_ENC_PIC_RDY_SHIFT 1U
/*! Slice: agsw_enc_buf_full:*/
#define AGSW_ENC_BUF_FULL
#define AGSW_ENC_BUF_FULL_MASK 0x00000001U
#define AGSW_ENC_BUF_FULL_SHIFT 0U
/*! Register: miv2_sp2_dma_yuv_status (0x000015dc)*/
/*! Slice: sp2_dma_yuv_active:*/
#define SP2_DMA_YUV_ACTIVE
#define SP2_DMA_YUV_ACTIVE_MASK 0x00000001U
#define SP2_DMA_YUV_ACTIVE_SHIFT 0U
/*! Register: miv2_sp2_dma_raw_status (0x000015e0)*/
/*! Slice: sp2_dma_raw_active:*/
#define SP2_DMA_RAW_ACTIVE
#define SP2_DMA_RAW_ACTIVE_MASK 0x00000001U
#define SP2_DMA_RAW_ACTIVE_SHIFT 0U
/*! Register: miv2_mcm_ctrl (0x00001600)*/
/*! Slice: mcm_init_offset_en:*/
#define MCM_RD_CFG_UPD
#define MCM_RD_CFG_UPD_MASK 0x00000040U
#define MCM_RD_CFG_UPD_SHIFT 6U
/*! Slice: mcm_init_offset_en:*/
#define MCM_RD_AUTO_UPDATE
#define MCM_RD_AUTO_UPDATE_MASK 0x00000020U
#define MCM_RD_AUTO_UPDATE_SHIFT 5U
#define MCM_INIT_OFFSET_EN
#define MCM_INIT_OFFSET_EN_MASK 0x00000010U
#define MCM_INIT_OFFSET_EN_SHIFT 4U
/*! Slice: mcm_init_base_en:*/
#define MCM_INIT_BASE_EN
#define MCM_INIT_BASE_EN_MASK 0x00000008U
#define MCM_INIT_BASE_EN_SHIFT 3U
/*! Slice: mcm_miv2_cfg_upd:*/
#define MCM_WR_CFG_UPD
#define MCM_WR_CFG_UPD_MASK 0x00000004U
#define MCM_WR_CFG_UPD_SHIFT 2U
/*! Slice: mcm_miv2_skip:*/
#define MCM_MI_SKIP
#define MCM_MI_SKIP_MASK 0x00000002U
#define MCM_MI_SKIP_SHIFT 1U
/*! Slice: mcm_auto_update:*/
#define MCM_WR_AUTO_UPDATE
#define MCM_WR_AUTO_UPDATE_MASK 0x00000001U
#define MCM_WR_AUTO_UPDATE_SHIFT 0U
/*! Register: miv2_mcm_fmt (0x00001604)*/
/*! Slice: mcm_wr1_fmt_aligned:*/
#define MCM_WR1_FMT_ALIGNED
#define MCM_WR1_FMT_ALIGNED_MASK 0x00030000U
#define MCM_WR1_FMT_ALIGNED_SHIFT 16U
/*! Slice: mcm_wr0_fmt_aligned:*/
#define MCM_WR0_FMT_ALIGNED
#define MCM_WR0_FMT_ALIGNED_MASK 0x0000C000U
#define MCM_WR0_FMT_ALIGNED_SHIFT 14U
/*! Slice: mcm_rd_fmt_aligned:*/
#define MCM_RD_FMT_ALIGNED
#define MCM_RD_FMT_ALIGNED_MASK 0x00003000U
#define MCM_RD_FMT_ALIGNED_SHIFT 12U
/*! Slice: mcm_wr1_raw_bit:*/
#define MCM_WR1_RAW_BIT
#define MCM_WR1_RAW_BIT_MASK 0x00000F00U
#define MCM_WR1_RAW_BIT_SHIFT 8U
/*! Slice: mcm_wr0_raw_bit:*/
#define MCM_WR0_RAW_BIT
#define MCM_WR0_RAW_BIT_MASK 0x000000F0U
#define MCM_WR0_RAW_BIT_SHIFT 4U
/*! Slice: mcm_rd_raw_bit:*/
#define MCM_RD_RAW_BIT
#define MCM_RD_RAW_BIT_MASK 0x0000000FU
#define MCM_RD_RAW_BIT_SHIFT 0U
/*! Register: miv2_mcm_bus_cfg (0x00001608)*/
/*! Slice: mcm_rd_swap_raw:*/
#define MCM_RD_SWAP_RAW
#define MCM_RD_SWAP_RAW_MASK 0x000F0000U
#define MCM_RD_SWAP_RAW_SHIFT 16U
/*! Slice: mcm_wr0_swap_raw:*/
#define MCM_WR0_SWAP_RAW
#define MCM_WR0_SWAP_RAW_MASK 0x0000F000U
#define MCM_WR0_SWAP_RAW_SHIFT 12U
/*! Slice: mcm_wr1_swap_raw:*/
#define MCM_WR1_SWAP_RAW
#define MCM_WR1_SWAP_RAW_MASK 0x00000F00U
#define MCM_WR1_SWAP_RAW_SHIFT 8U
/*! Slice: mcm_rd_issue_cap:*/
#define MCM_RD_ISSUE_CAP
#define MCM_RD_ISSUE_CAP_MASK 0x000000C0U
#define MCM_RD_ISSUE_CAP_SHIFT 6U
/*! Slice: mcm_wr_issue_cap:*/
#define MCM_WR_ISSUE_CAP
#define MCM_WR_ISSUE_CAP_MASK 0x00000030U
#define MCM_WR_ISSUE_CAP_SHIFT 4U
/*! Slice: mcm_rd_burst_len:*/
#define MCM_RD_BURST_LEN
#define MCM_RD_BURST_LEN_MASK 0x0000000CU
#define MCM_RD_BURST_LEN_SHIFT 2U
/*! Slice: mcm_wr_burst_len:*/
#define MCM_WR_BURST_LEN
#define MCM_WR_BURST_LEN_MASK 0x00000003U
#define MCM_WR_BURST_LEN_SHIFT 0U
/*! Register: miv2_mcm_bus_id (0x0000160c)*/
/*! Slice: mcm_bus_sw_en:*/
#define MCM_BUS_SW_EN
#define MCM_BUS_SW_EN_MASK 0x08000000U
#define MCM_BUS_SW_EN_SHIFT 27U
/*! Slice: mcm_rd_id_en:*/
#define MCM_RD_ID_EN
#define MCM_RD_ID_EN_MASK 0x04000000U
#define MCM_RD_ID_EN_SHIFT 26U
/*! Slice: mcm_rd_id_cfg:*/
#define MCM_RD_ID_CFG
#define MCM_RD_ID_CFG_MASK 0x03FC0000U
#define MCM_RD_ID_CFG_SHIFT 18U
/*! Slice: mcm_wr0_id_en:*/
#define MCM_WR0_ID_EN
#define MCM_WR0_ID_EN_MASK 0x00020000U
#define MCM_WR0_ID_EN_SHIFT 17U
/*! Slice: mcm_wr0_id_cfg:*/
#define MCM_WR0_ID_CFG
#define MCM_WR0_ID_CFG_MASK 0x0001FE00U
#define MCM_WR0_ID_CFG_SHIFT 9U
/*! Slice: mcm_wr1_id_en:*/
#define MCM_WR1_ID_EN
#define MCM_WR1_ID_EN_MASK 0x00000100U
#define MCM_WR1_ID_EN_SHIFT 8U
/*! Slice: mcm_wr1_id_cfg:*/
#define MCM_WR1_ID_CFG
#define MCM_WR1_ID_CFG_MASK 0x000000FFU
#define MCM_WR1_ID_CFG_SHIFT 0U
/*! Register: miv2_mcm_bus_timeo (0x00001610)*/
/*! Slice: mcm_bus_timeo_en:*/
#define MCM_BUS_TIMEO_EN
#define MCM_BUS_TIMEO_EN_MASK 0x80000000U
#define MCM_BUS_TIMEO_EN_SHIFT 31U
/*! Slice: mcm_bus_timeo:*/
#define MCM_BUS_TIMEO
#define MCM_BUS_TIMEO_MASK 0x7FFFFFFFU
#define MCM_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_mcm_raw0_base_ad_init (0x00001614)*/
/*! Slice: mcm_raw0_base_ad_init:*/
#define MCM_RAW0_BASE_AD_INIT
#define MCM_RAW0_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MCM_RAW0_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw0_size_init (0x00001618)*/
/*! Slice: mcm_raw0_size_init:*/
#define MCM_RAW0_SIZE_INIT
#define MCM_RAW0_SIZE_INIT_MASK 0x1FFFFFF0U
#define MCM_RAW0_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw0_offs_cnt_init (0x0000161c)*/
/*! Slice: mcm_raw0_offs_cnt_init:*/
#define MCM_RAW0_OFFS_CNT_INIT
#define MCM_RAW0_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define MCM_RAW0_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw0_llength (0x00001620)*/
/*! Slice: mcm_raw0_llengh:*/
#define MCM_RAW0_LLENGH
#define MCM_RAW0_LLENGH_MASK 0x00007FFFU
#define MCM_RAW0_LLENGH_SHIFT 0U
/*! Register: miv2_mcm_raw0_pic_width (0x00001624)*/
/*! Slice: mcm_raw0_pic_width:*/
#define MCM_RAW0_PIC_WIDTH
#define MCM_RAW0_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MCM_RAW0_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mcm_raw0_pic_height (0x00001628)*/
/*! Slice: mcm_raw0_pic_height:*/
#define MCM_RAW0_PIC_HEIGHT
#define MCM_RAW0_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MCM_RAW0_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_mcm_raw0_pic_size (0x0000162c)*/
/*! Slice: mcm_raw0_pic_size:*/
#define MCM_RAW0_PIC_SIZE
#define MCM_RAW0_PIC_SIZE_MASK 0xFFFFFFFFU
#define MCM_RAW0_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mcm_raw0_offs_cnt_start (0x00001630)*/
/*! Slice: mcm_raw0_offs_cnt_start:*/
#define MCM_RAW0_OFFS_CNT_START
#define MCM_RAW0_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define MCM_RAW0_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mcm_raw0_base_ad_shd (0x00001634)*/
/*! Slice: mcm_raw0_base_ad:*/
#define MCM_RAW0_BASE_AD
#define MCM_RAW0_BASE_AD_MASK 0xFFFFFFF0U
#define MCM_RAW0_BASE_AD_SHIFT 4U
/*! Register: miv2_mcm_raw0_size_shd (0x00001638)*/
/*! Slice: mcm_raw0_size:*/
#define MCM_RAW0_SIZE
#define MCM_RAW0_SIZE_MASK 0x1FFFFFF0U
#define MCM_RAW0_SIZE_SHIFT 4U
/*! Register: miv2_mcm_raw0_offs_cnt_shd (0x0000163c)*/
/*! Slice: mcm_raw0_offs_cnt:*/
#define MCM_RAW0_OFFS_CNT
#define MCM_RAW0_OFFS_CNT_MASK 0x1FFFFFF0U
#define MCM_RAW0_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mcm_raw1_base_ad_init (0x00001640)*/
/*! Slice: mcm_raw1_base_ad_init:*/
#define MCM_RAW1_BASE_AD_INIT
#define MCM_RAW1_BASE_AD_INIT_MASK 0xFFFFFFF0U
#define MCM_RAW1_BASE_AD_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw1_size_init (0x00001644)*/
/*! Slice: mcm_raw1_size_init:*/
#define MCM_RAW1_SIZE_INIT
#define MCM_RAW1_SIZE_INIT_MASK 0x1FFFFFF0U
#define MCM_RAW1_SIZE_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw1_offs_cnt_init (0x00001648)*/
/*! Slice: mcm_raw1_offs_cnt_init:*/
#define MCM_RAW1_OFFS_CNT_INIT
#define MCM_RAW1_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
#define MCM_RAW1_OFFS_CNT_INIT_SHIFT 4U
/*! Register: miv2_mcm_raw1_llength (0x0000164c)*/
/*! Slice: mcm_raw1_llengh:*/
#define MCM_RAW1_LLENGH
#define MCM_RAW1_LLENGH_MASK 0x00007FFFU
#define MCM_RAW1_LLENGH_SHIFT 0U
/*! Register: miv2_mcm_raw1_pic_width (0x00001650)*/
/*! Slice: mcm_raw1_pic_width:*/
#define MCM_RAW1_PIC_WIDTH
#define MCM_RAW1_PIC_WIDTH_MASK 0xFFFFFFFFU
#define MCM_RAW1_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mcm_raw1_pic_height (0x00001654)*/
/*! Slice: mcm_raw1_pic_height:*/
#define MCM_RAW1_PIC_HEIGHT
#define MCM_RAW1_PIC_HEIGHT_MASK 0xFFFFFFFFU
#define MCM_RAW1_PIC_HEIGHT_SHIFT 0U
/*! Register: miv2_mcm_raw1_pic_size (0x00001658)*/
/*! Slice: mcm_raw1_pic_size:*/
#define MCM_RAW1_PIC_SIZE
#define MCM_RAW1_PIC_SIZE_MASK 0xFFFFFFFFU
#define MCM_RAW1_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mcm_raw1_offs_cnt_start (0x0000165c)*/
/*! Slice: mcm_raw1_offs_cnt_start:*/
#define MCM_RAW1_OFFS_CNT_START
#define MCM_RAW1_OFFS_CNT_START_MASK 0x1FFFFFF0U
#define MCM_RAW1_OFFS_CNT_START_SHIFT 4U
/*! Register: miv2_mcm_raw1_base_ad_shd (0x00001660)*/
/*! Slice: mcm_raw1_base_ad:*/
#define MCM_RAW1_BASE_AD
#define MCM_RAW1_BASE_AD_MASK 0xFFFFFFF0U
#define MCM_RAW1_BASE_AD_SHIFT 4U
/*! Register: miv2_mcm_raw1_size_shd (0x00001664)*/
/*! Slice: mcm_raw1_size:*/
#define MCM_RAW1_SIZE
#define MCM_RAW1_SIZE_MASK 0x1FFFFFF0U
#define MCM_RAW1_SIZE_SHIFT 4U
/*! Register: miv2_mcm_raw1_offs_cnt_shd (0x00001668)*/
/*! Slice: mcm_raw1_offs_cnt:*/
#define MCM_RAW1_OFFS_CNT
#define MCM_RAW1_OFFS_CNT_MASK 0x1FFFFFF0U
#define MCM_RAW1_OFFS_CNT_SHIFT 4U
/*! Register: miv2_mcm_dma_raw_pic_start_ad (0x0000166c)*/
/*! Slice: mcm_dma_raw_pic_start_ad:*/
#define MCM_DMA_RAW_PIC_START_AD
#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U
/*! Register: miv2_mcm_dma_raw_pic_width (0x00001670)*/
/*! Slice: mcm_dma_raw_pic_width:*/
#define MCM_DMA_RAW_PIC_WIDTH
#define MCM_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU
#define MCM_DMA_RAW_PIC_WIDTH_SHIFT 0U
/*! Register: miv2_mcm_dma_raw_pic_llength (0x00001674)*/
/*! Slice: mcm_dma_raw_pic_llength:*/
#define MCM_DMA_RAW_PIC_LLENGTH
#define MCM_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU
#define MCM_DMA_RAW_PIC_LLENGTH_SHIFT 0U
/*! Register: miv2_mcm_dma_raw_pic_size (0x00001678)*/
/*! Slice: mcm_dma_raw_pic_size:*/
#define MCM_DMA_RAW_PIC_SIZE
#define MCM_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU
#define MCM_DMA_RAW_PIC_SIZE_SHIFT 0U
/*! Register: miv2_mcm_dma_raw_pic_start_ad_shd (0x0000167c)*/
/*! Slice: mcm_dma_raw_pic_start_ad:*/
#define MCM_DMA_RAW_PIC_START_AD
#define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
#define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U
/*! Register: miv2_mcm_status_clr (0x00001680)*/
/*! Slice: mcm_raw1_fifo_full:*/
#define MCM_RAW1_FIFO_FULL
#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U
#define MCM_RAW1_FIFO_FULL_SHIFT 1U
/*! Slice: mcm_raw0_fifo_full:*/
#define MCM_RAW0_FIFO_FULL
#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U
#define MCM_RAW0_FIFO_FULL_SHIFT 0U
/*! Register: miv2_mcm_ctrl_status (0x00001684)*/
/*! Slice: mcm_raw1_fifo_full:*/
#define MCM_RAW1_FIFO_FULL
#define MCM_RAW1_FIFO_FULL_MASK 0x00000002U
#define MCM_RAW1_FIFO_FULL_SHIFT 1U
/*! Slice: mcm_raw0_fifo_full:*/
#define MCM_RAW0_FIFO_FULL
#define MCM_RAW0_FIFO_FULL_MASK 0x00000001U
#define MCM_RAW0_FIFO_FULL_SHIFT 0U
/*! Register: miv2_mcm_axi_status (0x00001688)*/
/*! Slice: agsw_enc_pic_rdy:*/
#define AGSW_ENC_PIC_RDY
#define AGSW_ENC_PIC_RDY_MASK 0x00000002U
#define AGSW_ENC_PIC_RDY_SHIFT 1U
/*! Slice: agsw_enc_buf_full:*/
#define AGSW_ENC_BUF_FULL
#define AGSW_ENC_BUF_FULL_MASK 0x00000001U
#define AGSW_ENC_BUF_FULL_SHIFT 0U
/*! Register: miv2_mcm_dma_status (0x0000168c)*/
/*! Slice: mcm_dma_active:*/
#define MCM_DMA_ACTIVE
#define MCM_DMA_ACTIVE_MASK 0x00000001U
#define MCM_DMA_ACTIVE_SHIFT 0U
/*! Register: miv2_imsc (0x000016c0)*/
/*! Slice: fill_mp_y:*/
#define FILL_MP_Y
#define FILL_MP_Y_MASK 0x08000000U
#define FILL_MP_Y_SHIFT 27U
/*! Slice: mblk_line:*/
#define MBLK_LINE
#define MBLK_LINE_MASK 0x04000000U
#define MBLK_LINE_SHIFT 26U
/*! Slice: mp_handshk_int:*/
#define MP_HANDSHK_INT
#define MP_HANDSHK_INT_MASK 0x02000000U
#define MP_HANDSHK_INT_SHIFT 25U
/*! Slice: mcm_dma_raw_ready:*/
#define MCM_DMA_RAW_READY
#define MCM_DMA_RAW_READY_MASK 0x01000000U
#define MCM_DMA_RAW_READY_SHIFT 24U
/*! Slice: sp2_dma_raw_ready:*/
#define SP2_DMA_RAW_READY
#define SP2_DMA_RAW_READY_MASK 0x00800000U
#define SP2_DMA_RAW_READY_SHIFT 23U
/*! Slice: sp2_dma_ycbcr_ready:*/
#define SP2_DMA_YCBCR_READY
#define SP2_DMA_YCBCR_READY_MASK 0x00400000U
#define SP2_DMA_YCBCR_READY_SHIFT 22U
/*! Slice: wrap_mcm_raw1:*/
#define WRAP_MCM_RAW1
#define WRAP_MCM_RAW1_MASK 0x00200000U
#define WRAP_MCM_RAW1_SHIFT 21U
/*! Slice: wrap_mcm_raw0:*/
#define WRAP_MCM_RAW0
#define WRAP_MCM_RAW0_MASK 0x00100000U
#define WRAP_MCM_RAW0_SHIFT 20U
/*! Slice: wrap_sp2_cr:*/
#define WRAP_SP2_CR
#define WRAP_SP2_CR_MASK 0x00040000U
#define WRAP_SP2_CR_SHIFT 18U
/*! Slice: wrap_sp2_cb:*/
#define WRAP_SP2_CB
#define WRAP_SP2_CB_MASK 0x00020000U
#define WRAP_SP2_CB_SHIFT 17U
/*! Slice: wrap_sp2_y:*/
#define WRAP_SP2_Y
#define WRAP_SP2_Y_MASK 0x00010000U
#define WRAP_SP2_Y_SHIFT 16U
/*! Slice: wrap_sp1_cr:*/
#define WRAP_SP1_CR
#define WRAP_SP1_CR_MASK 0x00008000U
#define WRAP_SP1_CR_SHIFT 15U
/*! Slice: wrap_sp1_cb:*/
#define WRAP_SP1_CB
#define WRAP_SP1_CB_MASK 0x00004000U
#define WRAP_SP1_CB_SHIFT 14U
/*! Slice: wrap_sp1_y:*/
#define WRAP_SP1_Y
#define WRAP_SP1_Y_MASK 0x00002000U
#define WRAP_SP1_Y_SHIFT 13U
/*! Slice: wrap_mp_jdp:*/
#define WRAP_MP_JDP
#define WRAP_MP_JDP_MASK 0x00001000U
#define WRAP_MP_JDP_SHIFT 12U
/*! Slice: wrap_mp_raw:*/
#define WRAP_MP_RAW
#define WRAP_MP_RAW_MASK 0x00000800U
#define WRAP_MP_RAW_SHIFT 11U
/*! Slice: wrap_mp_cr:*/
#define WRAP_MP_CR
#define WRAP_MP_CR_MASK 0x00000400U
#define WRAP_MP_CR_SHIFT 10U
/*! Slice: wrap_mp_cb:*/
#define WRAP_MP_CB
#define WRAP_MP_CB_MASK 0x00000200U
#define WRAP_MP_CB_SHIFT 9U
/*! Slice: wrap_mp_y:*/
#define WRAP_MP_Y
#define WRAP_MP_Y_MASK 0x00000100U
#define WRAP_MP_Y_SHIFT 8U
/*! Slice: mcm_raw1_frame_end:*/
#define MCM_RAW1_FRAME_END
#define MCM_RAW1_FRAME_END_MASK 0x00000080U
#define MCM_RAW1_FRAME_END_SHIFT 7U
/*! Slice: mcm_raw0_frame_end:*/
#define MCM_RAW0_FRAME_END
#define MCM_RAW0_FRAME_END_MASK 0x00000040U
#define MCM_RAW0_FRAME_END_SHIFT 6U
/*! Slice: sp2_raw_frame_end:*/
#define SP2_RAW_FRAME_END
#define SP2_RAW_FRAME_END_MASK 0x00000020U
#define SP2_RAW_FRAME_END_SHIFT 5U
/*! Slice: sp2_ycbcr_frame_end:*/
#define SP2_YCBCR_FRAME_END
#define SP2_YCBCR_FRAME_END_MASK 0x00000010U
#define SP2_YCBCR_FRAME_END_SHIFT 4U
/*! Slice: sp1_ycbcr_frame_end:*/
#define SP1_YCBCR_FRAME_END
#define SP1_YCBCR_FRAME_END_MASK 0x00000008U
#define SP1_YCBCR_FRAME_END_SHIFT 3U
/*! Slice: mp_jdp_frame_end:*/
#define MP_JDP_FRAME_END
#define MP_JDP_FRAME_END_MASK 0x00000004U
#define MP_JDP_FRAME_END_SHIFT 2U
/*! Slice: mp_raw_frame_end:*/
#define MP_RAW_FRAME_END
#define MP_RAW_FRAME_END_MASK 0x00000002U
#define MP_RAW_FRAME_END_SHIFT 1U
/*! Slice: mp_ycbcr_frame_end:*/
#define MP_YCBCR_FRAME_END
#define MP_YCBCR_FRAME_END_MASK 0x00000001U
#define MP_YCBCR_FRAME_END_SHIFT 0U
/*! Register: miv2_imsc1 (0x000016c4)*/
/*! Slice: miv2_mcm_bus_buserr:*/
#define MI_MCM_BUS_BUSERR
#define MI_MCM_BUS_BUSERR_MASK 0x00000080U
#define MI_MCM_BUS_BUSERR_SHIFT 7U
/*! Slice: miv2_mcm_bus_timeo:*/
#define MI_MCM_BUS_TIMEO
#define MI_MCM_BUS_TIMEO_MASK 0x00000040U
#define MI_MCM_BUS_TIMEO_SHIFT 6U
/*! Slice: miv2_sp2_bus_buserr:*/
#define MI_SP2_BUS_BUSERR
#define MI_SP2_BUS_BUSERR_MASK 0x00000020U
#define MI_SP2_BUS_BUSERR_SHIFT 5U
/*! Slice: miv2_sp2_bus_timeo:*/
#define MI_SP2_BUS_TIMEO
#define MI_SP2_BUS_TIMEO_MASK 0x00000010U
#define MI_SP2_BUS_TIMEO_SHIFT 4U
/*! Slice: miv2_sp1_bus_buserr:*/
#define MI_SP1_BUS_BUSERR
#define MI_SP1_BUS_BUSERR_MASK 0x00000008U
#define MI_SP1_BUS_BUSERR_SHIFT 3U
/*! Slice: miv2_sp1_bus_timeo:*/
#define MI_SP1_BUS_TIMEO
#define MI_SP1_BUS_TIMEO_MASK 0x00000004U
#define MI_SP1_BUS_TIMEO_SHIFT 2U
/*! Slice: miv2_mp_bus_buserr:*/
#define MI_MP_BUS_BUSERR
#define MI_MP_BUS_BUSERR_MASK 0x00000002U
#define MI_MP_BUS_BUSERR_SHIFT 1U
/*! Slice: miv2_mp_bus_timeo:*/
#define MI_MP_BUS_TIMEO
#define MI_MP_BUS_TIMEO_MASK 0x00000001U
#define MI_MP_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_isr (0x000016c8)*/
/*! Slice: fill_mp_y:*/
#define FILL_MP_Y
#define FILL_MP_Y_MASK 0x08000000U
#define FILL_MP_Y_SHIFT 27U
/*! Slice: mblk_line:*/
#define MBLK_LINE
#define MBLK_LINE_MASK 0x04000000U
#define MBLK_LINE_SHIFT 26U
/*! Slice: mp_handshk_int:*/
#define MP_HANDSHK_INT
#define MP_HANDSHK_INT_MASK 0x02000000U
#define MP_HANDSHK_INT_SHIFT 25U
/*! Slice: mcm_dma_raw_ready:*/
#define MCM_DMA_RAW_READY
#define MCM_DMA_RAW_READY_MASK 0x01000000U
#define MCM_DMA_RAW_READY_SHIFT 24U
/*! Slice: sp2_dma_raw_ready:*/
#define SP2_DMA_RAW_READY
#define SP2_DMA_RAW_READY_MASK 0x00800000U
#define SP2_DMA_RAW_READY_SHIFT 23U
/*! Slice: sp2_dma_ycbcr_ready:*/
#define SP2_DMA_YCBCR_READY
#define SP2_DMA_YCBCR_READY_MASK 0x00400000U
#define SP2_DMA_YCBCR_READY_SHIFT 22U
/*! Slice: wrap_mcm_raw1:*/
#define WRAP_MCM_RAW1
#define WRAP_MCM_RAW1_MASK 0x00200000U
#define WRAP_MCM_RAW1_SHIFT 21U
/*! Slice: wrap_mcm_raw0:*/
#define WRAP_MCM_RAW0
#define WRAP_MCM_RAW0_MASK 0x00100000U
#define WRAP_MCM_RAW0_SHIFT 20U
/*! Slice: wrap_sp2_cr:*/
#define WRAP_SP2_CR
#define WRAP_SP2_CR_MASK 0x00040000U
#define WRAP_SP2_CR_SHIFT 18U
/*! Slice: wrap_sp2_cb:*/
#define WRAP_SP2_CB
#define WRAP_SP2_CB_MASK 0x00020000U
#define WRAP_SP2_CB_SHIFT 17U
/*! Slice: wrap_sp2_y:*/
#define WRAP_SP2_Y
#define WRAP_SP2_Y_MASK 0x00010000U
#define WRAP_SP2_Y_SHIFT 16U
/*! Slice: wrap_sp1_cr:*/
#define WRAP_SP1_CR
#define WRAP_SP1_CR_MASK 0x00008000U
#define WRAP_SP1_CR_SHIFT 15U
/*! Slice: wrap_sp1_cb:*/
#define WRAP_SP1_CB
#define WRAP_SP1_CB_MASK 0x00004000U
#define WRAP_SP1_CB_SHIFT 14U
/*! Slice: wrap_sp1_y:*/
#define WRAP_SP1_Y
#define WRAP_SP1_Y_MASK 0x00002000U
#define WRAP_SP1_Y_SHIFT 13U
/*! Slice: wrap_mp_jdp:*/
#define WRAP_MP_JDP
#define WRAP_MP_JDP_MASK 0x00001000U
#define WRAP_MP_JDP_SHIFT 12U
/*! Slice: wrap_mp_raw:*/
#define WRAP_MP_RAW
#define WRAP_MP_RAW_MASK 0x00000800U
#define WRAP_MP_RAW_SHIFT 11U
/*! Slice: wrap_mp_cr:*/
#define WRAP_MP_CR
#define WRAP_MP_CR_MASK 0x00000400U
#define WRAP_MP_CR_SHIFT 10U
/*! Slice: wrap_mp_cb:*/
#define WRAP_MP_CB
#define WRAP_MP_CB_MASK 0x00000200U
#define WRAP_MP_CB_SHIFT 9U
/*! Slice: wrap_mp_y:*/
#define WRAP_MP_Y
#define WRAP_MP_Y_MASK 0x00000100U
#define WRAP_MP_Y_SHIFT 8U
/*! Slice: mcm_raw1_frame_end:*/
#define MCM_RAW1_FRAME_END
#define MCM_RAW1_FRAME_END_MASK 0x00000080U
#define MCM_RAW1_FRAME_END_SHIFT 7U
/*! Slice: mcm_raw0_frame_end:*/
#define MCM_RAW0_FRAME_END
#define MCM_RAW0_FRAME_END_MASK 0x00000040U
#define MCM_RAW0_FRAME_END_SHIFT 6U
/*! Slice: sp2_raw_frame_end:*/
#define SP2_RAW_FRAME_END
#define SP2_RAW_FRAME_END_MASK 0x00000020U
#define SP2_RAW_FRAME_END_SHIFT 5U
/*! Slice: sp2_ycbcr_frame_end:*/
#define SP2_YCBCR_FRAME_END
#define SP2_YCBCR_FRAME_END_MASK 0x00000010U
#define SP2_YCBCR_FRAME_END_SHIFT 4U
/*! Slice: sp1_ycbcr_frame_end:*/
#define SP1_YCBCR_FRAME_END
#define SP1_YCBCR_FRAME_END_MASK 0x00000008U
#define SP1_YCBCR_FRAME_END_SHIFT 3U
/*! Slice: mp_jdp_frame_end:*/
#define MP_JDP_FRAME_END
#define MP_JDP_FRAME_END_MASK 0x00000004U
#define MP_JDP_FRAME_END_SHIFT 2U
/*! Slice: mp_raw_frame_end:*/
#define MP_RAW_FRAME_END
#define MP_RAW_FRAME_END_MASK 0x00000002U
#define MP_RAW_FRAME_END_SHIFT 1U
/*! Slice: mp_ycbcr_frame_end:*/
#define MP_YCBCR_FRAME_END
#define MP_YCBCR_FRAME_END_MASK 0x00000001U
#define MP_YCBCR_FRAME_END_SHIFT 0U
/*! Register: miv2_isr1 (0x000016cc)*/
/*! Slice: miv2_mcm_bus_buserr:*/
#define MI_MCM_BUS_BUSERR
#define MI_MCM_BUS_BUSERR_MASK 0x00000080U
#define MI_MCM_BUS_BUSERR_SHIFT 7U
/*! Slice: miv2_mcm_bus_timeo:*/
#define MI_MCM_BUS_TIMEO
#define MI_MCM_BUS_TIMEO_MASK 0x00000040U
#define MI_MCM_BUS_TIMEO_SHIFT 6U
/*! Slice: miv2_sp2_bus_buserr:*/
#define MI_SP2_BUS_BUSERR
#define MI_SP2_BUS_BUSERR_MASK 0x00000020U
#define MI_SP2_BUS_BUSERR_SHIFT 5U
/*! Slice: miv2_sp2_bus_timeo:*/
#define MI_SP2_BUS_TIMEO
#define MI_SP2_BUS_TIMEO_MASK 0x00000010U
#define MI_SP2_BUS_TIMEO_SHIFT 4U
/*! Slice: miv2_sp1_bus_buserr:*/
#define MI_SP1_BUS_BUSERR
#define MI_SP1_BUS_BUSERR_MASK 0x00000008U
#define MI_SP1_BUS_BUSERR_SHIFT 3U
/*! Slice: miv2_sp1_bus_timeo:*/
#define MI_SP1_BUS_TIMEO
#define MI_SP1_BUS_TIMEO_MASK 0x00000004U
#define MI_SP1_BUS_TIMEO_SHIFT 2U
#define MRV_MI_BP_PATH_ENABLE
#define MRV_MI_BP_PATH_ENABLE_MASK 0x00000001U
#define MRV_MI_BP_PATH_ENABLE_SHIFT 0U
/*! Register: bp_ctrl: Control register */
/*! Slice: bp_output_format */
/*  000  raw8
	001  raw10
	010  raw12
*/
#define MRV_MI_BP_WRITE_RAWBIT
#define MRV_MI_BP_WRITE_RAWBIT_MASK 0x0000001cU
#define MRV_MI_BP_WRITE_RAWBIT_SHIFT 2U
#define MRV_MI_BP_WRITE_FORMAT
#define MRV_MI_BP_WRITE_FORMAT_MASK 0x00000300U
#define MRV_MI_BP_WRITE_FORMAT_SHIFT 8U
#define MRV_MI_BP_WRITE_PLANAR_FORMAT 1
#define MRV_MI_BP_WRITE_INTERLEAVE_FORMAT 2
/*! Slice: miv2_mp_bus_buserr:*/
#define MI_MP_BUS_BUSERR
#define MI_MP_BUS_BUSERR_MASK 0x00000002U
#define MI_MP_BUS_BUSERR_SHIFT 1U
/*! Slice: miv2_mp_bus_timeo:*/
#define MI_MP_BUS_TIMEO
#define MI_MP_BUS_TIMEO_MASK 0x00000001U
#define MI_MP_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_mis (0x000016d0) */
/*! Slice: fill_mp_y: */
#define FILL_MP_Y
#define FILL_MP_Y_MASK 0x08000000U
#define FILL_MP_Y_SHIFT 27U
/*! Slice: mblk_line: */
#define MBLK_LINE
#define MBLK_LINE_MASK 0x04000000U
#define MBLK_LINE_SHIFT 26U
/*! Slice: mp_handshk_int: */
#define MP_HANDSHK_INT
#define MP_HANDSHK_INT_MASK 0x02000000U
#define MP_HANDSHK_INT_SHIFT 25U
/*! Slice: mcm_dma_raw_ready: */
#define MCM_DMA_RAW_READY
#define MCM_DMA_RAW_READY_MASK 0x01000000U
#define MCM_DMA_RAW_READY_SHIFT 24U
/*! Slice: sp2_dma_raw_ready: */
#define SP2_DMA_RAW_READY
#define SP2_DMA_RAW_READY_MASK 0x00800000U
#define SP2_DMA_RAW_READY_SHIFT 23U
/*! Slice: sp2_dma_ycbcr_ready: */
#define SP2_DMA_YCBCR_READY
#define SP2_DMA_YCBCR_READY_MASK 0x00400000U
#define SP2_DMA_YCBCR_READY_SHIFT 22U
/*! Slice: wrap_mcm_raw1: */
#define WRAP_MCM_RAW1
#define WRAP_MCM_RAW1_MASK 0x00200000U
#define WRAP_MCM_RAW1_SHIFT 21U
/*! Slice: wrap_mcm_raw0: */
#define WRAP_MCM_RAW0
#define WRAP_MCM_RAW0_MASK 0x00100000U
#define WRAP_MCM_RAW0_SHIFT 20U
/*! Slice: wrap_sp2_cr: */
#define WRAP_SP2_CR
#define WRAP_SP2_CR_MASK 0x00040000U
#define WRAP_SP2_CR_SHIFT 18U
/*! Slice: wrap_sp2_cb: */
#define WRAP_SP2_CB
#define WRAP_SP2_CB_MASK 0x00020000U
#define WRAP_SP2_CB_SHIFT 17U
/*! Slice: wrap_sp2_y: */
#define WRAP_SP2_Y
#define WRAP_SP2_Y_MASK 0x00010000U
#define WRAP_SP2_Y_SHIFT 16U
/*! Slice: wrap_sp1_cr: */
#define WRAP_SP1_CR
#define WRAP_SP1_CR_MASK 0x00008000U
#define WRAP_SP1_CR_SHIFT 15U
/*! Slice: wrap_sp1_cb: */
#define WRAP_SP1_CB
#define WRAP_SP1_CB_MASK 0x00004000U
#define WRAP_SP1_CB_SHIFT 14U
/*! Slice: wrap_sp1_y: */
#define WRAP_SP1_Y
#define WRAP_SP1_Y_MASK 0x00002000U
#define WRAP_SP1_Y_SHIFT 13U
/*! Slice: wrap_mp_jdp: */
#define WRAP_MP_JDP
#define WRAP_MP_JDP_MASK 0x00001000U
#define WRAP_MP_JDP_SHIFT 12U
/*! Slice: wrap_mp_raw: */
#define WRAP_MP_RAW
#define WRAP_MP_RAW_MASK 0x00000800U
#define WRAP_MP_RAW_SHIFT 11U
/*! Slice: wrap_mp_cr: */
#define WRAP_MP_CR
#define WRAP_MP_CR_MASK 0x00000400U
#define WRAP_MP_CR_SHIFT 10U
/*! Slice: wrap_mp_cb: */
#define WRAP_MP_CB
#define WRAP_MP_CB_MASK 0x00000200U
#define WRAP_MP_CB_SHIFT 9U
/*! Slice: wrap_mp_y: */
#define WRAP_MP_Y
#define WRAP_MP_Y_MASK 0x00000100U
#define WRAP_MP_Y_SHIFT 8U
/*! Slice: mcm_raw1_frame_end: */
#define MCM_RAW1_FRAME_END
#define MCM_RAW1_FRAME_END_MASK 0x00000080U
#define MCM_RAW1_FRAME_END_SHIFT 7U
/*! Slice: mcm_raw0_frame_end: */
#define MCM_RAW0_FRAME_END
#define MCM_RAW0_FRAME_END_MASK 0x00000040U
#define MCM_RAW0_FRAME_END_SHIFT 6U
/*! Slice: sp2_raw_frame_end: */
#define SP2_RAW_FRAME_END
#define SP2_RAW_FRAME_END_MASK 0x00000020U
#define SP2_RAW_FRAME_END_SHIFT 5U
/*! Slice: sp2_ycbcr_frame_end: */
#define SP2_YCBCR_FRAME_END
#define SP2_YCBCR_FRAME_END_MASK 0x00000010U
#define SP2_YCBCR_FRAME_END_SHIFT 4U
/*! Slice: sp1_ycbcr_frame_end: */
#define SP1_YCBCR_FRAME_END
#define SP1_YCBCR_FRAME_END_MASK 0x00000008U
#define SP1_YCBCR_FRAME_END_SHIFT 3U
/*! Slice: mp_jdp_frame_end: */
#define MP_JDP_FRAME_END
#define MP_JDP_FRAME_END_MASK 0x00000004U
#define MP_JDP_FRAME_END_SHIFT 2U
/*! Slice: mp_raw_frame_end: */
#define MP_RAW_FRAME_END
#define MP_RAW_FRAME_END_MASK 0x00000002U
#define MP_RAW_FRAME_END_SHIFT 1U
/*! Slice: mp_ycbcr_frame_end: */
#define MP_YCBCR_FRAME_END
#define MP_YCBCR_FRAME_END_MASK 0x00000001U
#define MP_YCBCR_FRAME_END_SHIFT 0U
/*! Register: miv2_mis1 (0x000016d4) */
/*! Slice: miv2_mcm_bus_buserr: */
#define MI_MCM_BUS_BUSERR
#define MI_MCM_BUS_BUSERR_MASK 0x00000080U
#define MI_MCM_BUS_BUSERR_SHIFT 7U
/*! Slice: miv2_mcm_bus_timeo: */
#define MI_MCM_BUS_TIMEO
#define MI_MCM_BUS_TIMEO_MASK 0x00000040U
#define MI_MCM_BUS_TIMEO_SHIFT 6U
/*! Slice: miv2_sp2_bus_buserr: */
#define MI_SP2_BUS_BUSERR
#define MI_SP2_BUS_BUSERR_MASK 0x00000020U
#define MI_SP2_BUS_BUSERR_SHIFT 5U
/*! Slice: miv2_sp2_bus_timeo: */
#define MI_SP2_BUS_TIMEO
#define MI_SP2_BUS_TIMEO_MASK 0x00000010U
#define MI_SP2_BUS_TIMEO_SHIFT 4U
/*! Slice: miv2_sp1_bus_buserr: */
#define MI_SP1_BUS_BUSERR
#define MI_SP1_BUS_BUSERR_MASK 0x00000008U
#define MI_SP1_BUS_BUSERR_SHIFT 3U
/*! Slice: miv2_sp1_bus_timeo: */
#define MI_SP1_BUS_TIMEO
#define MI_SP1_BUS_TIMEO_MASK 0x00000004U
#define MI_SP1_BUS_TIMEO_SHIFT 2U
/*! Slice: miv2_mp_bus_buserr: */
#define MI_MP_BUS_BUSERR
#define MI_MP_BUS_BUSERR_MASK 0x00000002U
#define MI_MP_BUS_BUSERR_SHIFT 1U
/*! Slice: miv2_mp_bus_timeo: */
#define MI_MP_BUS_TIMEO
#define MI_MP_BUS_TIMEO_MASK 0x00000001U
#define MI_MP_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_icr (0x000016d8) */
/*! Slice: fill_mp_y: */
#define FILL_MP_Y
#define FILL_MP_Y_MASK 0x08000000U
#define FILL_MP_Y_SHIFT 27U
/*! Slice: mblk_line: */
#define MBLK_LINE
#define MBLK_LINE_MASK 0x04000000U
#define MBLK_LINE_SHIFT 26U
/*! Slice: mp_handshk_int: */
#define MP_HANDSHK_INT
#define MP_HANDSHK_INT_MASK 0x02000000U
#define MP_HANDSHK_INT_SHIFT 25U
/*! Slice: mcm_dma_raw_ready: */
#define MCM_DMA_RAW_READY
#define MCM_DMA_RAW_READY_MASK 0x01000000U
#define MCM_DMA_RAW_READY_SHIFT 24U
/*! Slice: sp2_dma_raw_ready: */
#define SP2_DMA_RAW_READY
#define SP2_DMA_RAW_READY_MASK 0x00800000U
#define SP2_DMA_RAW_READY_SHIFT 23U
/*! Slice: sp2_dma_ycbcr_ready: */
#define SP2_DMA_YCBCR_READY
#define SP2_DMA_YCBCR_READY_MASK 0x00400000U
#define SP2_DMA_YCBCR_READY_SHIFT 22U
/*! Slice: wrap_mcm_raw1: */
#define WRAP_MCM_RAW1
#define WRAP_MCM_RAW1_MASK 0x00200000U
#define WRAP_MCM_RAW1_SHIFT 21U
/*! Slice: wrap_mcm_raw0: */
#define WRAP_MCM_RAW0
#define WRAP_MCM_RAW0_MASK 0x00100000U
#define WRAP_MCM_RAW0_SHIFT 20U
/*! Slice: wrap_sp2_cr: */
#define WRAP_SP2_CR
#define WRAP_SP2_CR_MASK 0x00040000U
#define WRAP_SP2_CR_SHIFT 18U
/*! Slice: wrap_sp2_cb: */
#define WRAP_SP2_CB
#define WRAP_SP2_CB_MASK 0x00020000U
#define WRAP_SP2_CB_SHIFT 17U
/*! Slice: wrap_sp2_y: */
#define WRAP_SP2_Y
#define WRAP_SP2_Y_MASK 0x00010000U
#define WRAP_SP2_Y_SHIFT 16U
/*! Slice: wrap_sp1_cr: */
#define WRAP_SP1_CR
#define WRAP_SP1_CR_MASK 0x00008000U
#define WRAP_SP1_CR_SHIFT 15U
/*! Slice: wrap_sp1_cb: */
#define WRAP_SP1_CB
#define WRAP_SP1_CB_MASK 0x00004000U
#define WRAP_SP1_CB_SHIFT 14U
/*! Slice: wrap_sp1_y: */
#define WRAP_SP1_Y
#define WRAP_SP1_Y_MASK 0x00002000U
#define WRAP_SP1_Y_SHIFT 13U
/*! Slice: wrap_mp_jdp: */
#define WRAP_MP_JDP
#define WRAP_MP_JDP_MASK 0x00001000U
#define WRAP_MP_JDP_SHIFT 12U
/*! Slice: wrap_mp_raw: */
#define WRAP_MP_RAW
#define WRAP_MP_RAW_MASK 0x00000800U
#define WRAP_MP_RAW_SHIFT 11U
/*! Slice: wrap_mp_cr: */
#define WRAP_MP_CR
#define WRAP_MP_CR_MASK 0x00000400U
#define WRAP_MP_CR_SHIFT 10U
/*! Slice: wrap_mp_cb: */
#define WRAP_MP_CB
#define WRAP_MP_CB_MASK 0x00000200U
#define WRAP_MP_CB_SHIFT 9U
/*! Slice: wrap_mp_y: */
#define WRAP_MP_Y
#define WRAP_MP_Y_MASK 0x00000100U
#define WRAP_MP_Y_SHIFT 8U
/*! Slice: mcm_raw1_frame_end: */
#define MCM_RAW1_FRAME_END
#define MCM_RAW1_FRAME_END_MASK 0x00000080U
#define MCM_RAW1_FRAME_END_SHIFT 7U
/*! Slice: mcm_raw0_frame_end: */
#define MCM_RAW0_FRAME_END
#define MCM_RAW0_FRAME_END_MASK 0x00000040U
#define MCM_RAW0_FRAME_END_SHIFT 6U
/*! Slice: sp2_raw_frame_end: */
#define SP2_RAW_FRAME_END
#define SP2_RAW_FRAME_END_MASK 0x00000020U
#define SP2_RAW_FRAME_END_SHIFT 5U
/*! Slice: sp2_ycbcr_frame_end: */
#define SP2_YCBCR_FRAME_END
#define SP2_YCBCR_FRAME_END_MASK 0x00000010U
#define SP2_YCBCR_FRAME_END_SHIFT 4U
/*! Slice: sp1_ycbcr_frame_end: */
#define SP1_YCBCR_FRAME_END
#define SP1_YCBCR_FRAME_END_MASK 0x00000008U
#define SP1_YCBCR_FRAME_END_SHIFT 3U
/*! Slice: mp_jdp_frame_end: */
#define MP_JDP_FRAME_END
#define MP_JDP_FRAME_END_MASK 0x00000004U
#define MP_JDP_FRAME_END_SHIFT 2U
/*! Slice: mp_raw_frame_end: */
#define MP_RAW_FRAME_END
#define MP_RAW_FRAME_END_MASK 0x00000002U
#define MP_RAW_FRAME_END_SHIFT 1U
/*! Slice: mp_ycbcr_frame_end: */
#define MP_YCBCR_FRAME_END
#define MP_YCBCR_FRAME_END_MASK 0x00000001U
#define MP_YCBCR_FRAME_END_SHIFT 0U
/*! Register: miv2_icr1 (0x000016dc) */
/*! Slice: miv2_mcm_bus_buserr: */
#define MI_MCM_BUS_BUSERR
#define MI_MCM_BUS_BUSERR_MASK 0x00000080U
#define MI_MCM_BUS_BUSERR_SHIFT 7U
/*! Slice: miv2_mcm_bus_timeo: */
#define MI_MCM_BUS_TIMEO
#define MI_MCM_BUS_TIMEO_MASK 0x00000040U
#define MI_MCM_BUS_TIMEO_SHIFT 6U
/*! Slice: miv2_sp2_bus_buserr: */
#define MI_SP2_BUS_BUSERR
#define MI_SP2_BUS_BUSERR_MASK 0x00000020U
#define MI_SP2_BUS_BUSERR_SHIFT 5U
/*! Slice: miv2_sp2_bus_timeo: */
#define MI_SP2_BUS_TIMEO
#define MI_SP2_BUS_TIMEO_MASK 0x00000010U
#define MI_SP2_BUS_TIMEO_SHIFT 4U
/*! Slice: miv2_sp1_bus_buserr: */
#define MI_SP1_BUS_BUSERR
#define MI_SP1_BUS_BUSERR_MASK 0x00000008U
#define MI_SP1_BUS_BUSERR_SHIFT 3U
/*! Slice: miv2_sp1_bus_timeo: */
#define MI_SP1_BUS_TIMEO
#define MI_SP1_BUS_TIMEO_MASK 0x00000004U
#define MI_SP1_BUS_TIMEO_SHIFT 2U
/*! Slice: miv2_mp_bus_buserr: */
#define MI_MP_BUS_BUSERR
#define MI_MP_BUS_BUSERR_MASK 0x00000002U
#define MI_MP_BUS_BUSERR_SHIFT 1U
/*! Slice: miv2_mp_bus_timeo: */
#define MI_MP_BUS_TIMEO
#define MI_MP_BUS_TIMEO_MASK 0x00000001U
#define MI_MP_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_ris (0x000016e0) */
/*! Slice: fill_mp_y: */
#define FILL_MP_Y
#define FILL_MP_Y_MASK 0x08000000U
#define FILL_MP_Y_SHIFT 27U
/*! Slice: mblk_line: */
#define MBLK_LINE
#define MBLK_LINE_MASK 0x04000000U
#define MBLK_LINE_SHIFT 26U
/*! Slice: mp_handshk_int: */
#define MP_HANDSHK_INT
#define MP_HANDSHK_INT_MASK 0x02000000U
#define MP_HANDSHK_INT_SHIFT 25U
/*! Slice: mcm_dma_raw_ready: */
#define MCM_DMA_RAW_READY
#define MCM_DMA_RAW_READY_MASK 0x01000000U
#define MCM_DMA_RAW_READY_SHIFT 24U
/*! Slice: sp2_dma_raw_ready: */
#define SP2_DMA_RAW_READY
#define SP2_DMA_RAW_READY_MASK 0x00800000U
#define SP2_DMA_RAW_READY_SHIFT 23U
/*! Slice: sp2_dma_ycbcr_ready: */
#define SP2_DMA_YCBCR_READY
#define SP2_DMA_YCBCR_READY_MASK 0x00400000U
#define SP2_DMA_YCBCR_READY_SHIFT 22U
/*! Slice: wrap_mcm_raw1: */
#define WRAP_MCM_RAW1
#define WRAP_MCM_RAW1_MASK 0x00200000U
#define WRAP_MCM_RAW1_SHIFT 21U
/*! Slice: wrap_mcm_raw0: */
#define WRAP_MCM_RAW0
#define WRAP_MCM_RAW0_MASK 0x00100000U
#define WRAP_MCM_RAW0_SHIFT 20U
/*! Slice: wrap_sp2_raw: */
#define WRAP_SP2_RAW
#define WRAP_SP2_RAW_MASK (0x1 << 16)
#define WRAP_SP2_RAW_SHIFT 16U
/*! Slice: wrap_sp2_cr: */
#define WRAP_SP2_CR
#define WRAP_SP2_CR_MASK 0x00040000U
#define WRAP_SP2_CR_SHIFT 18U
/*! Slice: wrap_sp2_cb: */
#define WRAP_SP2_CB
#define WRAP_SP2_CB_MASK 0x00020000U
#define WRAP_SP2_CB_SHIFT 17U
/*! Slice: wrap_sp2_y: */
#define WRAP_SP2_Y
#define WRAP_SP2_Y_MASK 0x00010000U
#define WRAP_SP2_Y_SHIFT 16U
/*! Slice: wrap_sp1_cr: */
#define WRAP_SP1_CR
#define WRAP_SP1_CR_MASK 0x00008000U
#define WRAP_SP1_CR_SHIFT 15U
/*! Slice: wrap_sp1_cb: */
#define WRAP_SP1_CB
#define WRAP_SP1_CB_MASK 0x00004000U
#define WRAP_SP1_CB_SHIFT 14U
/*! Slice: wrap_sp1_y: */
#define WRAP_SP1_Y
#define WRAP_SP1_Y_MASK 0x00002000U
#define WRAP_SP1_Y_SHIFT 13U
/*! Slice: wrap_mp_jdp: */
#define WRAP_MP_JDP
#define WRAP_MP_JDP_MASK 0x00001000U
#define WRAP_MP_JDP_SHIFT 12U
/*! Slice: wrap_mp_raw: */
#define WRAP_MP_RAW
#define WRAP_MP_RAW_MASK 0x00000800U
#define WRAP_MP_RAW_SHIFT 11U
/*! Slice: wrap_mp_cr: */
#define WRAP_MP_CR
#define WRAP_MP_CR_MASK 0x00000400U
#define WRAP_MP_CR_SHIFT 10U
/*! Slice: wrap_mp_cb: */
#define WRAP_MP_CB
#define WRAP_MP_CB_MASK 0x00000200U
#define WRAP_MP_CB_SHIFT 9U
/*! Slice: wrap_mp_y: */
#define WRAP_MP_Y
#define WRAP_MP_Y_MASK 0x00000100U
#define WRAP_MP_Y_SHIFT 8U
/*! Slice: mcm_raw1_frame_end: */
#define MCM_RAW1_FRAME_END
#define MCM_RAW1_FRAME_END_MASK 0x00000080U
#define MCM_RAW1_FRAME_END_SHIFT 7U
/*! Slice: mcm_raw0_frame_end: */
#define MCM_RAW0_FRAME_END
#define MCM_RAW0_FRAME_END_MASK 0x00000040U
#define MCM_RAW0_FRAME_END_SHIFT 6U
/*! Slice: sp2_raw_frame_end: */
#define SP2_RAW_FRAME_END
#define SP2_RAW_FRAME_END_MASK 0x00000020U
#define SP2_RAW_FRAME_END_SHIFT 5U
/*! Slice: sp2_ycbcr_frame_end: */
#define SP2_YCBCR_FRAME_END
#define SP2_YCBCR_FRAME_END_MASK 0x00000010U
#define SP2_YCBCR_FRAME_END_SHIFT 4U
/*! Slice: sp1_ycbcr_frame_end: */
#define SP1_YCBCR_FRAME_END
#define SP1_YCBCR_FRAME_END_MASK 0x00000008U
#define SP1_YCBCR_FRAME_END_SHIFT 3U
/*! Slice: mp_jdp_frame_end: */
#define MP_JDP_FRAME_END
#define MP_JDP_FRAME_END_MASK 0x00000004U
#define MP_JDP_FRAME_END_SHIFT 2U
/*! Slice: mp_raw_frame_end: */
#define MP_RAW_FRAME_END
#define MP_RAW_FRAME_END_MASK 0x00000002U
#define MP_RAW_FRAME_END_SHIFT 1U
/*! Slice: mp_ycbcr_frame_end: */
#define MP_YCBCR_FRAME_END
#define MP_YCBCR_FRAME_END_MASK 0x00000001U
#define MP_YCBCR_FRAME_END_SHIFT 0U
/*! Register: miv2_ris1 (0x000016e4)*/
/*! Slice: miv2_mcm_bus_buserr:*/
#define MI_MCM_BUS_BUSERR
#define MI_MCM_BUS_BUSERR_MASK 0x00000080U
#define MI_MCM_BUS_BUSERR_SHIFT 7U
/*! Slice: miv2_mcm_bus_timeo:*/
#define MI_MCM_BUS_TIMEO
#define MI_MCM_BUS_TIMEO_MASK 0x00000040U
#define MI_MCM_BUS_TIMEO_SHIFT 6U
/*! Slice: miv2_sp2_bus_buserr:*/
#define MI_SP2_BUS_BUSERR
#define MI_SP2_BUS_BUSERR_MASK 0x00000020U
#define MI_SP2_BUS_BUSERR_SHIFT 5U
/*! Slice: miv2_sp2_bus_timeo:*/
#define MI_SP2_BUS_TIMEO
#define MI_SP2_BUS_TIMEO_MASK 0x00000010U
#define MI_SP2_BUS_TIMEO_SHIFT 4U
/*! Slice: miv2_sp1_bus_buserr:*/
#define MI_SP1_BUS_BUSERR
#define MI_SP1_BUS_BUSERR_MASK 0x00000008U
#define MI_SP1_BUS_BUSERR_SHIFT 3U
/*! Slice: miv2_sp1_bus_timeo:*/
#define MI_SP1_BUS_TIMEO
#define MI_SP1_BUS_TIMEO_MASK 0x00000004U
#define MI_SP1_BUS_TIMEO_SHIFT 2U
/*! Slice: miv2_mp_bus_buserr:*/
#define MI_MP_BUS_BUSERR
#define MI_MP_BUS_BUSERR_MASK 0x00000002U
#define MI_MP_BUS_BUSERR_SHIFT 1U
/*! Slice: miv2_mp_bus_timeo:*/
#define MI_MP_BUS_TIMEO
#define MI_MP_BUS_TIMEO_MASK 0x00000001U
#define MI_MP_BUS_TIMEO_SHIFT 0U
/*! Register: miv2_mp_y_irq_offs_init (0x00001700)*/
/*! Slice: mp_y_irq_offs_init:*/
#define MP_Y_IRQ_OFFS_INIT
#define MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MP_Y_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_mp_jdp_irq_offs_init (0x00001704)*/
/*! Slice: mp_jdp_irq_offs_init:*/
#define MP_JDP_IRQ_OFFS_INIT
#define MP_JDP_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MP_JDP_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_mp_raw_irq_offs_init (0x00001708)*/
/*! Slice: mp_raw_irq_offs_init:*/
#define MP_RAW_IRQ_OFFS_INIT
#define MP_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MP_RAW_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_sp1_y_irq_offs_init (0x0000170c)*/
/*! Slice: sp1_y_irq_offs_init:*/
#define SP1_Y_IRQ_OFFS_INIT
#define SP1_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define SP1_Y_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_sp2_y_irq_offs_init (0x00001710)*/
/*! Slice: sp2_y_irq_offs_init:*/
#define SP2_Y_IRQ_OFFS_INIT
#define SP2_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define SP2_Y_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_sp2_raw_irq_offs_init (0x00001714)*/
/*! Slice: sp2_raw_irq_offs_init:*/
#define SP2_RAW_IRQ_OFFS_INIT
#define SP2_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define SP2_RAW_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_mcm_raw0_irq_offs_init (0x00001718)*/
/*! Slice: mcm_raw0_irq_offs_init:*/
#define MCM_RAW0_IRQ_OFFS_INIT
#define MCM_RAW0_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MCM_RAW0_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_mcm_raw1_irq_offs_init (0x0000171c)*/
/*! Slice: mcm_raw1_irq_offs_init:*/
#define MCM_RAW1_IRQ_OFFS_INIT
#define MCM_RAW1_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
#define MCM_RAW1_IRQ_OFFS_INIT_SHIFT 3U
/*! Register: miv2_mp_y_irq_offs_shd (0x00001720)*/
/*! Slice: mp_y_irq_offs:*/
#define MP_Y_IRQ_OFFS
#define MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MP_Y_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_mp_jdp_irq_offs_shd (0x00001724)*/
/*! Slice: mp_jdp_irq_offs:*/
#define MP_JDP_IRQ_OFFS
#define MP_JDP_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MP_JDP_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_mp_raw_irq_offs_shd (0x00001728)*/
/*! Slice: mp_raw_irq_offs:*/
#define MP_RAW_IRQ_OFFS
#define MP_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MP_RAW_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_sp1_y_irq_offs_shd (0x0000172c)*/
/*! Slice: sp1_y_irq_offs:*/
#define SP1_Y_IRQ_OFFS
#define SP1_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
#define SP1_Y_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_sp2_y_irq_offs_shd (0x00001730)*/
/*! Slice: sp2_y_irq_offs:*/
#define SP2_Y_IRQ_OFFS
#define SP2_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
#define SP2_Y_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_sp2_raw_irq_offs_shd (0x00001734)*/
/*! Slice: sp2_raw_irq_offs:*/
#define SP2_RAW_IRQ_OFFS
#define SP2_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U
#define SP2_RAW_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_mcm_raw0_irq_offs_shd (0x00001738)*/
/*! Slice: mcm_raw0_irq_offs:*/
#define MCM_RAW0_IRQ_OFFS
#define MCM_RAW0_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MCM_RAW0_IRQ_OFFS_SHIFT 3U
/*! Register: miv2_mcm_raw1_irq_offs_shd (0x0000173c)*/
/*! Slice: mcm_raw1_irq_offs:*/
#define MCM_RAW1_IRQ_OFFS
#define MCM_RAW1_IRQ_OFFS_MASK 0x1FFFFFF8U
#define MCM_RAW1_IRQ_OFFS_SHIFT 3U
/*! Register: isp_ee_ctrl  (0x00003900)*/
/*! Slice: isp_ee_ctrl enable:*/
#define  EE_CTRL_ENABLE
#define  EE_CTRL_ENABLE_MASK 0x00000001U
#define  EE_CTRL_ENABLE_SHIFT 0U
/*! Slice: isp_ee_ctrl_input_sel_flag:*/
#define  EE_CTRL_INPUT_SEL
#define  EE_CTRL_INPUT_SEL_MASK 0x00000002U
#define  EE_CTRL_INPUT_SEL_SHIFT 1U
/*! Slice: isp_ee_ctrl_soft_reset_flag:*/
#define  EE_CTRL_SOFT_RESET_FLAG
#define  EE_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U
#define  EE_CTRL_SOFT_RESET_FLAG_SHIFT 2U
/*! Slice: isp_ee_ctrl_strength:*/
#define  EE_CTRL_STRENGTH
#define  EE_CTRL_STRENGTH_MASK 0x000007F8U
#define  EE_CTRL_STRENGTH_SHIFT 3U
/*! Slice: isp_ee_ctrl_source_strength:*/
#define  EE_CTRL_SOURCE_STRENGTH
#define  EE_CTRL_SOURCE_STRENGTH_MASK 0x0007F800U
#define  EE_CTRL_SOURCE_STRENGTH_SHIFT 11U
/*! Register: isp_ee_y_gain  (0x00003904)*/
/*! Slice: ee_y_down_gain: */
#define  EE_Y_DOWN_GAIN
#define  EE_Y_DOWN_GAIN_MASK 0xFFFF0000U
#define  EE_Y_DOWN_GAIN_SHIFT 16U
/*! Slice: ee_y_up_gain: */
#define  EE_Y_UP_GAIN
#define  EE_Y_UP_GAIN_MASK 0x0000FFFFU
#define  EE_Y_UP_GAIN_SHIFT 0U
/*! Slice: ee_y_gain:*/
#define  EE_Y_GAIN
#define  EE_Y_GAIN_MASK 0xFFFFFFFFU
#define  EE_Y_GAIN_SHIFT 0U
/*! Register: isp_ee_edge_gain  (0x00003908)*/
/*! Slice: isp_ee_edge_gain:*/
#define  EE_EDGE_GAIN
#define  EE_EDGE_GAIN_MASK 0xFFFF0000U
#define  EE_EDGE_GAIN_SHIFT 16U
/*! Register: isp_ee_uv_gain  (0x00003908)*/
/*! Slice: isp_ee_uv_gain:*/
#define  EE_UV_GAIN
#define  EE_UV_GAIN_MASK 0x0000FFFFU
#define  EE_UV_GAIN_SHIFT 0U
/*! Register: isp_ee_dummy_hblank  (0x00003918)*/
/*! Slice: isp_ee_dummy_hblank:*/
#define  ISP_EE_DUMMY_HBLANK
#define  ISP_EE_DUMMY_HBLANK_MASK 0x0000FFFFU
#define  ISP_EE_DUMMY_HBLANK_SHIFT 0U
/*! Register: isp_ee_ctrl_shd  (0x0000390c)*/
/*! Slice: isp_ee_ctrl_shd enable:*/
#define  EE_CTRL_ENABLE_SHD
#define  EE_CTRL_ENABLE_SHD_MASK 0x00000001U
#define  EE_CTRL_ENABLE_SHD_SHIFT 0U
/*! Slice: isp_ee_ctrl_input_sel_shd:*/
#define  EE_CTRL_INPUT_SEL_SHD
#define  EE_CTRL_INPUT_SEL_SHD_MASK 0x00000002U
#define  EE_CTRL_INPUT_SEL_SHD_SHIFT 1U
/*! Slice: isp_ee_ctrl_soft_reset_flag_shd:*/
#define  EE_CTRL_SOFT_RESET_FLAG_SHD
#define  EE_CTRL_SOFT_RESET_FLAG_SHD_MASK 0x00000004U
#define  EE_CTRL_SOFT_RESET_FLAG_SHD_SHIFT 2U
/*! Slice: isp_ee_ctrl_strength_shd:*/
#define  EE_CTRL_STRENGTH_SHD
#define  EE_CTRL_STRENGTH_SHD_MASK 0x000007F8U
#define  EE_CTRL_STRENGTH_SHD_SHIFT 3U
/*! Slice: isp_ee_ctrl_source_strength_shd:*/
#define  EE_CTRL_SOURCE_STRENGTH_SHD
#define  EE_CTRL_SOURCE_STRENGTH_SHD_MASK 0xFF000000U
#define  EE_CTRL_SOURCE_STRENGTH_SHD_SHIFT 24U
/*! Register: isp_ee_y_gain_shd  (0x00003910)*/
/*! Slice: isp_ee_y_gain_shd:*/
#define  EE_Y_GAIN_SHD
#define  EE_Y_GAIN_SHD_MASK 0xFFFFFFFFU
#define  EE_Y_GAIN_SHD_SHIFT 0U
/*! Register: isp_ee_edge_gain_shd  (0x00003908)*/
/*! Slice: isp_ee_edge_gain_shd:*/
#define  EE_EDGE_GAIN_SHD
#define  EE_EDGE_GAIN_SHD_MASK 0xFFFF0000U
#define  EE_EDGE_GAIN_SHD_SHIFT 16U
/*! Register: isp_ee_uv_gain_shd  (0x00003914)*/
/*! Slice: isp_ee_uv_gain_shd:*/
#define  EE_UV_GAIN_SHD
#define  EE_UV_GAIN_SHD_MASK 0x0000FFFFU
#define  EE_UV_GAIN_SHD_SHIFT 0U
#define ISP_DEMOSAIC_THR
#define ISP_DEMOSAIC_THR_MASK 0xff000000U
#define ISP_DEMOSAIC_THR_SHIFT 24U
#define ISP_DEMOSAIC_DENOISE_STRENGTH
#define ISP_DEMOSAIC_DENOISE_STRENGTH_MASK 0x003f0000U
#define ISP_DEMOSAIC_DENOISE_STRENGTH_SHIFT 16U
#define ISP_DEMOSAIC_SHARPEN_SIZE
#define ISP_DEMOSAIC_SHARPEN_SIZE_MASK 0x00001f00U
#define ISP_DEMOSAIC_SHARPEN_SIZE_SHIFT 8U
#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE
#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_MASK 0x00000020U
#define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_SHIFT 5U
#define ISP_DEMOSAIC_SKIN_ENABLE
#define ISP_DEMOSAIC_SKIN_ENABLE_MASK 0x00000010U
#define ISP_DEMOSAIC_SKIN_ENABLE_SHIFT 4U
#define ISP_DEMOSAIC_DEPURPLE_ENABLE
#define ISP_DEMOSAIC_DEPURPLE_ENABLE_MASK 0x00000008U
#define ISP_DEMOSAIC_DEPURPLE_ENABLE_SHIFT 3U
#define ISP_DEMOSAIC_DEMOIRE_ENABLE
#define ISP_DEMOSAIC_DEMOIRE_ENABLE_MASK 0x00000004U
#define ISP_DEMOSAIC_DEMOIRE_ENABLE_SHIFT 2U
#define ISP_DEMOSAIC_SHARPEN_ENBALE
#define ISP_DEMOSAIC_SHARPEN_ENBALE_MASK 0x00000002U
#define ISP_DEMOSAIC_SHARPEN_ENBALE_SHIFT 1U
#define ISP_DEMOSAIC_BYPASS
#define ISP_DEMOSAIC_BYPASS_MASK 0x00000001U
#define ISP_DEMOSAIC_BYPASS_SHIFT 0U
#define ISP_DMSC_INTERPLATION_DIR_THR_MIN
#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_MASK 0x00fff000U
#define ISP_DMSC_INTERPLATION_DIR_THR_MIN_SHIFT 12U
#define ISP_DMSC_INTERPLATION_DIR_THR_MAX
#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_MASK 0x00000fffU
#define ISP_DMSC_INTERPLATION_DIR_THR_MAX_SHIFT 0U
#define ISP_DMSC_DEMOIRE_AREA_THR
#define ISP_DMSC_DEMOIRE_AREA_THR_MASK 0x00003f00U
#define ISP_DMSC_DEMOIRE_AREA_THR_SHIFT 8U
#define ISP_DMSC_DEMOIRE_SAT_SHRINK
#define ISP_DMSC_DEMOIRE_SAT_SHRINK_MASK 0x0000003fU
#define ISP_DMSC_DEMOIRE_SAT_SHRINK_SHIFT 0U
#define ISP_DMSC_DEMOIRE_R2
#define ISP_DMSC_DEMOIRE_R2_MASK  0x3FE00000U
#define ISP_DMSC_DEMOIRE_R2_SHIFT 21U
#define ISP_DMSC_DEMOIRE_R1
#define ISP_DMSC_DEMOIRE_R1_MASK  0x001ff000U
#define ISP_DMSC_DEMOIRE_R1_SHIFT 12U
#define ISP_DMSC_DEMOIRE_T2_SHIFT
#define ISP_DMSC_DEMOIRE_T2_SHIFT_MASK 0x00000f00U
#define ISP_DMSC_DEMOIRE_T2_SHIFT_SHIFT 8U
#define ISP_DMSC_DEMOIRE_T1
#define ISP_DMSC_DEMOIRE_T1_MASK 0x000000FFU
#define ISP_DMSC_DEMOIRE_T1_SHIFT 0U
#define ISP_DMSC_DEMOIRE_EDGE_R2
#define ISP_DMSC_DEMOIRE_EDGE_R2_MASK 0x7fc00000U
#define ISP_DMSC_DEMOIRE_EDGE_R2_SHIFT 22U
#define ISP_DMSC_DEMOIRE_EDGE_R1
#define ISP_DMSC_DEMOIRE_EDGE_R1_MASK 0x003fe000U
#define ISP_DMSC_DEMOIRE_EDGE_R1_SHIFT 13U
#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT
#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_MASK 0x00001e00U
#define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_SHIFT 9U
#define ISP_DMSC_DEMOIRE_EDGE_T1
#define ISP_DMSC_DEMOIRE_EDGE_T1_MASK 0x000001ffU
#define ISP_DMSC_DEMOIRE_EDGE_T1_SHIFT 0U
#define ISP_DMSC_SHARPEN_FACTOR_BLACK
#define ISP_DMSC_SHARPEN_FACTOR_BLACK_MASK 0x001ff000U
#define ISP_DMSC_SHARPEN_FACTOR_BLACK_SHIFT 12U
#define ISP_DMSC_SHARPEN_FACTOR_WHITE
#define ISP_DMSC_SHARPEN_FACTOR_WHITE_MASK 0x000001ffU
#define ISP_DMSC_SHARPEN_FACTOR_WHITE_SHIFT 0U
#define ISP_DMSC_SHARPEN_CLIP_BLACK
#define ISP_DMSC_SHARPEN_CLIP_BLACK_MASK 0x007ff000U
#define ISP_DMSC_SHARPEN_CLIP_BLACK_SHIFT 12U
#define ISP_DMSC_SHARPEN_CLIP_WHITE
#define ISP_DMSC_SHARPEN_CLIP_WHITE_MASK 0x000007ffU
#define ISP_DMSC_SHARPEN_CLIP_WHITE_SHIFT 0U
#define ISP_DMSC_SHARPEN_T4_SHIFT
#define ISP_DMSC_SHARPEN_T4_SHIFT_MASK 0xf0000000U
#define ISP_DMSC_SHARPEN_T4_SHIFT_SHIFT 28U
#define ISP_DMSC_SHARPEN_T3
#define ISP_DMSC_SHARPEN_T3_MASK 0x07ff0000U
#define ISP_DMSC_SHARPEN_T3_SHIFT 16U
#define ISP_DMSC_SHARPEN_T2_SHIFT
#define ISP_DMSC_SHARPEN_T2_SHIFT_MASK 0x0000f000U
#define ISP_DMSC_SHARPEN_T2_SHIFT_SHIFT 12U
#define ISP_DMSC_SHARPEN_T1
#define ISP_DMSC_SHARPEN_T1_MASK 0x000003ffU
#define ISP_DMSC_SHARPEN_T1_SHIFT 0U
#define ISP_DMSC_SHARPEN_R3
#define ISP_DMSC_SHARPEN_R3_MASK  0x07fc0000
#define ISP_DMSC_SHARPEN_R3_SHIFT 18U
#define ISP_DMSC_SHARPEN_R2
#define ISP_DMSC_SHARPEN_R2_MASK  0x0003fe00
#define ISP_DMSC_SHARPEN_R2_SHIFT 9U
#define ISP_DMSC_SHARPEN_R1
#define ISP_DMSC_SHARPEN_R1_MASK 0x000001ffU
#define ISP_DMSC_SHARPEN_R1_SHIFT 0U
#define ISP_DMSC_SHARPEN_LINE_SHIFT2
#define ISP_DMSC_SHARPEN_LINE_SHIFT2_MASK 0xf0000000U
#define ISP_DMSC_SHARPEN_LINE_SHIFT2_SHIFT 28U
#define ISP_DMSC_SHARPEN_LINE_SHIFT1
#define ISP_DMSC_SHARPEN_LINE_SHIFT1_MASK 0x0f000000U
#define ISP_DMSC_SHARPEN_LINE_SHIFT1_SHIFT 24U
#define ISP_DMSC_SHARPEN_LINE_T1
#define ISP_DMSC_SHARPEN_LINE_T1_MASK 0x007ff000U
#define ISP_DMSC_SHARPEN_LINE_T1_SHIFT 12U
#define ISP_DMSC_SHARPEN_LINE_STRENGTH
#define ISP_DMSC_SHARPEN_LINE_STRENGTH_MASK 0x00000fffU
#define ISP_DMSC_SHARPEN_LINE_STRENGTH_SHIFT 0U
#define ISP_DMSC_SHARPEN_LINE_R2
#define ISP_DMSC_SHARPEN_LINE_R2_MASK 0x0003fe00
#define ISP_DMSC_SHARPEN_LINE_R2_SHIFT 9U
#define ISP_DMSC_SHARPEN_LINE_R1
#define ISP_DMSC_SHARPEN_LINE_R1_MASK 0x000001ffU
#define ISP_DMSC_SHARPEN_LINE_R1_SHIFT 0U
#define ISP_DMSC_HF_FILT_00
#define ISP_DMSC_HF_FILT_00_MASK 0x3f000000U
#define ISP_DMSC_HF_FILT_00_SHIFT 24U
#define ISP_DMSC_HF_FILT_01
#define ISP_DMSC_HF_FILT_01_MASK 0x00fc0000U
#define ISP_DMSC_HF_FILT_01_SHIFT 18U
#define ISP_DMSC_HF_FILT_02
#define ISP_DMSC_HF_FILT_02_MASK 0x0003f000U
#define ISP_DMSC_HF_FILT_02_SHIFT 12U
#define ISP_DMSC_HF_FILT_10
#define ISP_DMSC_HF_FILT_10_MASK 0x00000fc0U
#define ISP_DMSC_HF_FILT_10_SHIFT 6U
#define ISP_DMSC_HF_FILT_11
#define ISP_DMSC_HF_FILT_11_MASK 0x0000003fU
#define ISP_DMSC_HF_FILT_11_SHIFT 0U
#define ISP_DMSC_HF_FILT_12
#define ISP_DMSC_HF_FILT_12_MASK 0x00fc0000U
#define ISP_DMSC_HF_FILT_12_SHIFT 18U
#define ISP_DMSC_HF_FILT_20
#define ISP_DMSC_HF_FILT_20_MASK 0x0003f000U
#define ISP_DMSC_HF_FILT_20_SHIFT 12U
#define ISP_DMSC_HF_FILT_21
#define ISP_DMSC_HF_FILT_21_MASK 0x00000fc0U
#define ISP_DMSC_HF_FILT_21_SHIFT 6U
#define ISP_DMSC_HF_FILT_22
#define ISP_DMSC_HF_FILT_22_MASK 0x0000003fU
#define ISP_DMSC_HF_FILT_22_SHIFT 0U
#define ISP_DMSC_DEPURPLE_RED_SAT
#define ISP_DMSC_DEPURPLE_RED_SAT_MASK 0x00001000U
#define ISP_DMSC_DEPURPLE_RED_SAT_SHIFT 12U
#define ISP_DMSC_DEPURPLE_BLUE_SAT
#define ISP_DMSC_DEPURPLE_BLUE_SAT_MASK 0x00002000U
#define ISP_DMSC_DEPURPLE_BLUE_SAT_SHIFT 13U
#define ISP_DMSC_DEPURPLE_SAT_SHRINK
#define ISP_DMSC_DEPURPLE_SAT_SHRINK_MASK 0x00000f00U
#define ISP_DMSC_DEPURPLE_SAT_SHRINK_SHIFT 8U
#define ISP_DMSC_DEPURPLE_THR
#define ISP_DMSC_DEPURPLE_THR_MASK 0x000000ffU
#define ISP_DMSC_DEPURPLE_THR_SHIFT 0U
#define ISP_DMSC_SKIN_CB_THR_MAX_2047
#define ISP_DMSC_SKIN_CB_THR_MAX_2047_MASK 0x00FFF000U
#define ISP_DMSC_SKIN_CB_THR_MAX_2047_SHIFT 12U
#define ISP_DMSC_SKIN_CB_THR_MIN_2047
#define ISP_DMSC_SKIN_CB_THR_MIN_2047_MASK 0x00000fffU
#define ISP_DMSC_SKIN_CB_THR_MIN_2047_SHIFT 0U
#define ISP_DMSC_SKIN_CR_THR_MAX_2047
#define ISP_DMSC_SKIN_CR_THR_MAX_2047_MASK 0x00FFF000U
#define ISP_DMSC_SKIN_CR_THR_MAX_2047_SHIFT 12U
#define ISP_DMSC_SKIN_CR_THR_MIN_2047
#define ISP_DMSC_SKIN_CR_THR_MIN_2047_MASK 0x00000fffU
#define ISP_DMSC_SKIN_CR_THR_MIN_2047_SHIFT 0U
#define ISP_DMSC_SKIN_Y_THR_MAX
#define ISP_DMSC_SKIN_Y_THR_MAX_MASK 0x00FFF000U
#define ISP_DMSC_SKIN_Y_THR_MAX_SHIFT 12U
#define ISP_DMSC_SKIN_Y_THR_MIN
#define ISP_DMSC_SKIN_Y_THR_MIN_MASK 0x00000fffU
#define ISP_DMSC_SKIN_Y_THR_MIN_SHIFT 0U
#define ISP_DMSC_CAC_ENABLE
#define ISP_DMSC_CAC_ENABLE_MASK   0x00000001U
#define ISP_DMSC_CAC_ENABLE_SHIFT 0U
#define ISP_DMSC_V_COUNT_START
#define ISP_DMSC_V_COUNT_START_MASK  0xffff0000U
#define ISP_DMSC_V_COUNT_START_SHIFT 16U
#define ISP_DMSC_H_COUNT_START
#define ISP_DMSC_H_COUNT_START_MASK 0x0000ffffU
#define ISP_DMSC_H_COUNT_START_SHIFT 0U
#define ISP_DMSC_A_RED
#define ISP_DMSC_A_RED_MASK 0x01ff0000U
#define ISP_DMSC_A_RED_SHIFT 16U
#define ISP_DMSC_A_BLUE
#define ISP_DMSC_A_BLUE_MASK 0x000001ffU
#define ISP_DMSC_A_BLUE_SHIFT 0U
#define ISP_DMSC_B_RED
#define ISP_DMSC_B_RED_MASK 0x01ff0000U
#define ISP_DMSC_B_RED_SHIFT 16U
#define ISP_DMSC_B_BLUE
#define ISP_DMSC_B_BLUE_MASK  0x000001ffU
#define ISP_DMSC_B_BLUE_SHIFT 0U
#define ISP_DMSC_C_RED
#define ISP_DMSC_C_RED_MASK 0x01ff0000U
#define ISP_DMSC_C_RED_SHIFT 16U
#define ISP_DMSC_C_BLUE
#define ISP_DMSC_C_BLUE_MASK 0x000001ffU
#define ISP_DMSC_C_BLUE_SHIFT 0U
#define ISP_DMSC_X_NS
#define ISP_DMSC_X_NS_MASK 0x000f0000U
#define ISP_DMSC_X_NS_SHIFT 16U
#define ISP_DMSC_X_NF
#define ISP_DMSC_X_NF_MASK 0x0000001f
#define ISP_DMSC_X_NF_SHIFT 0U
#define ISP_DMSC_Y_NS
#define ISP_DMSC_Y_NS_MASK 0x000f0000U
#define ISP_DMSC_Y_NS_SHIFT 16U
#define ISP_DMSC_Y_NF
#define ISP_DMSC_Y_NF_MASK 0x0000001fU
#define ISP_DMSC_Y_NF_SHIFT 0U
#define ISP_DMSC_Y_NF
#define ISP_DMSC_Y_NF_MASK 0x0000001fU
#define ISP_DMSC_Y_NF_SHIFT 0U
#define ISP_DMSC_IMAGE_H_SIZE
#define ISP_DMSC_IMAGE_H_SIZE_MASK 0x0000ffffU
#define ISP_DMSC_IMAGE_H_SIZE_SHIFT 0U
#define ISP_DMSC_IMAGE_H_BLANK
#define ISP_DMSC_IMAGE_H_BLANK_MASK 0xffff0000U
#define ISP_DMSC_IMAGE_H_BLANK_SHIFT 16U
#define ISP_DMSC_H_BLANK
#define ISP_DMSC_H_BLANK_MASK 0xffff0000U
#define ISP_DMSC_H_BLANK_SHIFT 16U
#define ISP_GREEN_EQUILIBTATE_TH
#define ISP_GREEN_EQUILIBTATE_TH_MASK 0x0001fffeU
#define ISP_GREEN_EQUILIBTATE_TH_SHIFT 1U
#define ISP_GREEN_EQUILIBTATE_ENABLE
#define ISP_GREEN_EQUILIBTATE_ENABLE_MASK 0x00000001U
#define ISP_GREEN_EQUILIBTATE_ENABLE_SHIFT 0U
#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY
#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_MASK 0x0000ffffU
#define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_SHIFT 0U
#define ISP_CURVE_MODE
#define ISP_CURVE_MODE_MASK 0x00000006U
#define ISP_CURVE_MODE_SHIFT 1U
#define ISP_CURVE_ENABLE
#define ISP_CURVE_ENABLE_MASK 0x00000001U
#define ISP_CURVE_ENABLE_SHIFT 0U
#define ISP_CURVE_LUT_X_ADDR
#define ISP_CURVE_LUT_X_ADDR_MASK 0x0000007fU
#define ISP_CURVE_LUT_X_ADDR_SHIFT 0U
#define ISP_CURVE_LUT_X_WRITE_DATA
#define ISP_CURVE_LUT_X_WRITE_DATA_MASK 0x000000fffU
#define ISP_CURVE_LUT_X_WRITE_DATA_SHIFT 0U
#define ISP_CURVE_LUT_LUMA_ADDR
#define ISP_CURVE_LUT_LUMA_ADDR_MASK 0x0000007fU
#define ISP_CURVE_LUT_LUMA_ADDR_SHIFT 0U
#define ISP_CURVE_LUT_LUMA_WRITE_DATA
#define ISP_CURVE_LUT_LUMA_WRITE_DATA_MASK 0x000007ffU
#define ISP_CURVE_LUT_LUMA_WRITE_DATA_SHIFT 0U
#define ISP_CURVE_LUT_CHROMA_ADDR
#define ISP_CURVE_LUT_CHROMA_ADDR_MASK 0x0000007fU
#define ISP_CURVE_LUT_CHROMA_ADDR_SHIFT 0U
#define ISP_CURVE_LUT_CHROMA_WRITE_DATA
#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_MASK 0x00000fffU
#define ISP_CURVE_LUT_CHROMA_WRITE_DATA_SHIFT 0U
#define ISP_CURVE_LUT_SHIFT_ADDR
#define ISP_CURVE_LUT_SHIFT_ADDR_MASK 0x0000007fU
#define ISP_CURVE_LUT_SHIFT_ADDR_SHIFT 0U
#define ISP_CURVE_LUT_SHIFT_WRITE_DATA
#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_MASK 0x0000001fU
#define ISP_CURVE_LUT_SHIFT_WRITE_DATA_SHIFT 0U
#define ISP_DIGITAL_GAIN_R
#define ISP_DIGITAL_GAIN_R_MASK 0xffff0000U
#define ISP_DIGITAL_GAIN_R_SHIFT 16U
#define ISP_DIGITAL_GAIN_B
#define ISP_DIGITAL_GAIN_B_MASK 0x0000ffffU
#define ISP_DIGITAL_GAIN_B_SHIFT 0U
#define ISP_DIGITAL_GAIN_GR
#define ISP_DIGITAL_GAIN_GR_MASK 0xffff0000U
#define ISP_DIGITAL_GAIN_GR_SHIFT 16U
#define ISP_DIGITAL_GAIN_GB
#define ISP_DIGITAL_GAIN_GB_MASK 0x0000ffffU
#define ISP_DIGITAL_GAIN_GB_SHIFT 0U
/*! Register: isp_vsync_delay: (0x00000730)*/
/*! Slice: vsync_delya:*/
#define ISP_VSYNC_DELAY
#define ISP_VSYNC_DELAY_MASK 0x01FFFFFFU
#define ISP_VSYNC_DELAY_SHIFT 0U
/*! Register: isp_vsync_delay: (0x00000730)*/
/*! Slice: reg_vsync_sel:*/
#define ISP_VSYNC_DELAY_SEL
#define ISP_VSYNC_DELAY_SEL_MASK 0x80000000U
#define ISP_VSYNC_DELAY_SEL_SHIFT 31U
#define WDR4_DUMMY_BLK
#define WDR4_DUMMY_BLK_MASK (0xffff << 16 )
#define WDR4_DUMMY_BLK_SHIFT 16U

#define WDR4_DUMMY_BLK_EN
#define WDR4_DUMMY_BLK_EN_MASK 0x1 << 15
#define WDR4_DUMMY_BLK_EN_SHIFT 15U

#define WDR4_SOFT_RESET_FLAG
#define WDR4_SOFT_RESET_FLAG_MASK 0x1 << 1
#define WDR4_SOFT_RESET_FLAG_SHIFT 1U

#define WDR4_ENABLE
#define WDR4_ENABLE_MASK 0x1 << 0
#define WDR4_ENABLE_SHIFT 0U

#define WDR4_OUTPUT_SHIFT_BIT
#define WDR4_OUTPUT_SHIFT_BIT_MASK (0x3f << 6 )
#define WDR4_OUTPUT_SHIFT_BIT_SHIFT 6U

#define WDR4_PIXEL_SHIFT_BIT
#define WDR4_PIXEL_SHIFT_BIT_MASK (0x3f << 0 )
#define WDR4_PIXEL_SHIFT_BIT_SHIFT 0U

#define WDR4_BLOCK_HEIGHT
#define WDR4_BLOCK_HEIGHT_MASK (0x1ff << 9 )
#define WDR4_BLOCK_HEIGHT_SHIFT 9U

#define WDR4_BLOCK_WIDTH
#define WDR4_BLOCK_WIDTH_MASK (0x1ff << 0 )
#define WDR4_BLOCK_WIDTH_SHIFT 0U

#define WDR4_BLOCK_AREA_INVERSE
#define WDR4_BLOCK_AREA_INVERSE_MASK (0xfffff << 0 )
#define WDR4_BLOCK_AREA_INVERSE_SHIFT 0U

#define WDR4_VALUE_WEIGHT_3
#define WDR4_VALUE_WEIGHT_3_MASK (0x1f << 15 )
#define WDR4_VALUE_WEIGHT_3_SHIFT 15U

#define WDR4_VALUE_WEIGHT_2
#define WDR4_VALUE_WEIGHT_2_MASK (0x1f << 10 )
#define WDR4_VALUE_WEIGHT_2_SHIFT 10U

#define WDR4_VALUE_WEIGHT_1
#define WDR4_VALUE_WEIGHT_1_MASK (0x1f << 5 )
#define WDR4_VALUE_WEIGHT_1_SHIFT 5U

#define WDR4_VALUE_WEIGHT_0
#define WDR4_VALUE_WEIGHT_0_MASK (0x1f << 0 )
#define WDR4_VALUE_WEIGHT_0_SHIFT 0U

#define WDR4_TOTAL_STRENGTH
#define WDR4_TOTAL_STRENGTH_MASK (0xff << 24 )
#define WDR4_TOTAL_STRENGTH_SHIFT 24U

#define WDR4_LOCAL_STRENGTH
#define WDR4_LOCAL_STRENGTH_MASK (0xff << 16 )
#define WDR4_LOCAL_STRENGTH_SHIFT 16U

#define WDR4_GLOBAL_STRENGTH
#define WDR4_GLOBAL_STRENGTH_MASK (0xff << 8 )
#define WDR4_GLOBAL_STRENGTH_SHIFT 8U

#define WDR4_LOW_STRENGTH
#define WDR4_LOW_STRENGTH_MASK (0xff << 0 )
#define WDR4_LOW_STRENGTH_SHIFT 0U

#define WDR4_HIGH_STRENGTH
#define WDR4_HIGH_STRENGTH_MASK (0xff << 16 )
#define WDR4_HIGH_STRENGTH_SHIFT 16U

#define WDR4_DRC_BAYER_RATIOLSVS
#define WDR4_DRC_BAYER_RATIOLSVS_MASK (0xff << 8 )
#define WDR4_DRC_BAYER_RATIOLSVS_SHIFT 8U

#define WDR4_DRC_BAYER_RATIO
#define WDR4_DRC_BAYER_RATIO_MASK (0xff << 0 )
#define WDR4_DRC_BAYER_RATIO_SHIFT 0U

#define WDR4_CONTRAST
#define WDR4_CONTRAST_MASK (0x7ff << 10 )
#define WDR4_CONTRAST_SHIFT 10U

#define WDR4_FLAT_STRENGTH
#define WDR4_FLAT_STRENGTH_MASK (0x1f << 5 )
#define WDR4_FLAT_STRENGTH_SHIFT 5U

#define WDR4_FLAT_THR
#define WDR4_FLAT_THR_MASK (0x1f << 0 )
#define WDR4_FLAT_THR_SHIFT 0U

#define WDR4_PIXEL_MERGE_SLOPE
#define WDR4_PIXEL_MERGE_SLOPE_MASK (0xff << 24 )
#define WDR4_PIXEL_MERGE_SLOPE_SHIFT 24U

#define WDR4_PIXEL_MERGE_BASE
#define WDR4_PIXEL_MERGE_BASE_MASK (0xff << 16 )
#define WDR4_PIXEL_MERGE_BASE_SHIFT 16U

#define WDR4_PIXEL_ADJUST_SLOPE
#define WDR4_PIXEL_ADJUST_SLOPE_MASK (0xff << 8 )
#define WDR4_PIXEL_ADJUST_SLOPE_SHIFT 8U

#define WDR4_PIXEL_ADJUST_BASE
#define WDR4_PIXEL_ADJUST_BASE_MASK (0xff << 0 )
#define WDR4_PIXEL_ADJUST_BASE_SHIFT 0U

#define WDR4_ENTROPY_SLOPE
#define WDR4_ENTROPY_SLOPE_MASK (0x3ff << 10 )
#define WDR4_ENTROPY_SLOPE_SHIFT 10U

#define WDR4_ENTROPY_BASE
#define WDR4_ENTROPY_BASE_MASK (0x3ff << 0 )
#define WDR4_ENTROPY_BASE_SHIFT 0U

#define WDR4_BILITERAL_WIDTH_SIGMA
#define WDR4_BILITERAL_WIDTH_SIGMA_MASK (0xfffff << 0 )
#define WDR4_BILITERAL_WIDTH_SIGMA_SHIFT 0U

#define WDR4_BILITERAL_HEIGHT_SIGMA
#define WDR4_BILITERAL_HEIGHT_SIGMA_MASK (0xfffff << 0 )
#define WDR4_BILITERAL_HEIGHT_SIGMA_SHIFT 0U

#define WDR4_BILITERAL_VALUE_SIGMA
#define WDR4_BILITERAL_VALUE_SIGMA_MASK (0xfffff << 0 )
#define WDR4_BILITERAL_VALUE_SIGMA_SHIFT 0U

#define WDR4_BLOCK_COL_FLAG
#define WDR4_BLOCK_COL_FLAG_MASK (0xffffffff << 0 )
#define WDR4_BLOCK_COL_FLAG_SHIFT 0U

#define WDR4_BLOCK_ROW_FLAG
#define WDR4_BLOCK_ROW_FLAG_MASK (0xffffffff << 0 )
#define WDR4_BLOCK_ROW_FLAG_SHIFT 0U

#define WDR4_FRAME_AVERAGE
#define WDR4_FRAME_AVERAGE_MASK (0xffffffff << 0 )
#define WDR4_FRAME_AVERAGE_SHIFT 0U

#define WDR4_FRAME_STD
#define WDR4_FRAME_STD_MASK (0xffffffff << 0 )
#define WDR4_FRAME_STD_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE0_0
#define WDR4_HISTOGRAM_CURVE0_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE0_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE1
#define WDR4_HISTOGRAM_CURVE1_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE1_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE0_1
#define WDR4_HISTOGRAM_CURVE0_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE0_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE2
#define WDR4_HISTOGRAM_CURVE2_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE2_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE3_0
#define WDR4_HISTOGRAM_CURVE3_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE3_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE4
#define WDR4_HISTOGRAM_CURVE4_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE4_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE3_1
#define WDR4_HISTOGRAM_CURVE3_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE3_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE5
#define WDR4_HISTOGRAM_CURVE5_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE5_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE6_0
#define WDR4_HISTOGRAM_CURVE6_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE6_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE7
#define WDR4_HISTOGRAM_CURVE7_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE7_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE6_1
#define WDR4_HISTOGRAM_CURVE6_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE6_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE8
#define WDR4_HISTOGRAM_CURVE8_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE8_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE9_0
#define WDR4_HISTOGRAM_CURVE9_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE9_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE10
#define WDR4_HISTOGRAM_CURVE10_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE10_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE9_1
#define WDR4_HISTOGRAM_CURVE9_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE9_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE11
#define WDR4_HISTOGRAM_CURVE11_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE11_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE12_0
#define WDR4_HISTOGRAM_CURVE12_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE12_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE13
#define WDR4_HISTOGRAM_CURVE13_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE13_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE12_1
#define WDR4_HISTOGRAM_CURVE12_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE12_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE14
#define WDR4_HISTOGRAM_CURVE14_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE14_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE15_0
#define WDR4_HISTOGRAM_CURVE15_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE15_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE16
#define WDR4_HISTOGRAM_CURVE16_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE16_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE15_1
#define WDR4_HISTOGRAM_CURVE15_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE15_1_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE17
#define WDR4_HISTOGRAM_CURVE17_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE17_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE18_0
#define WDR4_HISTOGRAM_CURVE18_0_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE18_0_SHIFT 20U

#define WDR4_HISTOGRAM_CURVE19
#define WDR4_HISTOGRAM_CURVE19_MASK (0xfffff << 0 )
#define WDR4_HISTOGRAM_CURVE19_SHIFT 0U

#define WDR4_HISTOGRAM_CURVE18_1
#define WDR4_HISTOGRAM_CURVE18_1_MASK (0x3ff << 20 )
#define WDR4_HISTOGRAM_CURVE18_1_SHIFT 20U

#define WDR4_ENTROPY_CONVERT0
#define WDR4_ENTROPY_CONVERT0_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT0_SHIFT 18U

#define WDR4_ENTROPY_CONVERT1
#define WDR4_ENTROPY_CONVERT1_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT1_SHIFT 9U

#define WDR4_ENTROPY_CONVERT2
#define WDR4_ENTROPY_CONVERT2_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT2_SHIFT 0U

#define WDR4_ENTROPY_CONVERT3
#define WDR4_ENTROPY_CONVERT3_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT3_SHIFT 18U

#define WDR4_ENTROPY_CONVERT4
#define WDR4_ENTROPY_CONVERT4_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT4_SHIFT 9U

#define WDR4_ENTROPY_CONVERT5
#define WDR4_ENTROPY_CONVERT5_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT5_SHIFT 0U

#define WDR4_ENTROPY_CONVERT6
#define WDR4_ENTROPY_CONVERT6_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT6_SHIFT 18U

#define WDR4_ENTROPY_CONVERT7
#define WDR4_ENTROPY_CONVERT7_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT7_SHIFT 9U

#define WDR4_ENTROPY_CONVERT8
#define WDR4_ENTROPY_CONVERT8_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT8_SHIFT 0U

#define WDR4_ENTROPY_CONVERT9
#define WDR4_ENTROPY_CONVERT9_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT9_SHIFT 18U

#define WDR4_ENTROPY_CONVERT10
#define WDR4_ENTROPY_CONVERT10_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT10_SHIFT 9U

#define WDR4_ENTROPY_CONVERT11
#define WDR4_ENTROPY_CONVERT11_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT11_SHIFT 0U

#define WDR4_ENTROPY_CONVERT12
#define WDR4_ENTROPY_CONVERT12_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT12_SHIFT 18U

#define WDR4_ENTROPY_CONVERT13
#define WDR4_ENTROPY_CONVERT13_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT13_SHIFT 9U

#define WDR4_ENTROPY_CONVERT14
#define WDR4_ENTROPY_CONVERT14_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT14_SHIFT 0U

#define WDR4_ENTROPY_CONVERT15
#define WDR4_ENTROPY_CONVERT15_MASK (0x1ff << 18 )
#define WDR4_ENTROPY_CONVERT15_SHIFT 18U

#define WDR4_ENTROPY_CONVERT16
#define WDR4_ENTROPY_CONVERT16_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT16_SHIFT 9U

#define WDR4_ENTROPY_CONVERT17
#define WDR4_ENTROPY_CONVERT17_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT17_SHIFT 0U

#define WDR4_ENTROPY_CONVERT18
#define WDR4_ENTROPY_CONVERT18_MASK (0x1ff << 9 )
#define WDR4_ENTROPY_CONVERT18_SHIFT 9U

#define WDR4_ENTROPY_CONVERT19
#define WDR4_ENTROPY_CONVERT19_MASK (0x1ff << 0 )
#define WDR4_ENTROPY_CONVERT19_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE0_0
#define WDR4_GAMMA_PRE_CURVE0_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE0_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE1
#define WDR4_GAMMA_PRE_CURVE1_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE1_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE0_1
#define WDR4_GAMMA_PRE_CURVE0_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE0_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE2
#define WDR4_GAMMA_PRE_CURVE2_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE2_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE3_0
#define WDR4_GAMMA_PRE_CURVE3_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE3_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE4
#define WDR4_GAMMA_PRE_CURVE4_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE4_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE3_1
#define WDR4_GAMMA_PRE_CURVE3_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE3_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE5
#define WDR4_GAMMA_PRE_CURVE5_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE5_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE6_0
#define WDR4_GAMMA_PRE_CURVE6_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE6_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE7
#define WDR4_GAMMA_PRE_CURVE7_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE7_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE6_1
#define WDR4_GAMMA_PRE_CURVE6_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE6_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE8
#define WDR4_GAMMA_PRE_CURVE8_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE8_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE9_0
#define WDR4_GAMMA_PRE_CURVE9_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE9_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE10
#define WDR4_GAMMA_PRE_CURVE10_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE10_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE9_1
#define WDR4_GAMMA_PRE_CURVE9_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE9_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE11
#define WDR4_GAMMA_PRE_CURVE11_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE11_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE12_0
#define WDR4_GAMMA_PRE_CURVE12_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE12_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE13
#define WDR4_GAMMA_PRE_CURVE13_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE13_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE12_1
#define WDR4_GAMMA_PRE_CURVE12_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE12_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE14
#define WDR4_GAMMA_PRE_CURVE14_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE14_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE15_0
#define WDR4_GAMMA_PRE_CURVE15_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE15_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE16
#define WDR4_GAMMA_PRE_CURVE16_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE16_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE15_1
#define WDR4_GAMMA_PRE_CURVE15_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE15_1_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE17
#define WDR4_GAMMA_PRE_CURVE17_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE17_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE18_0
#define WDR4_GAMMA_PRE_CURVE18_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE18_0_SHIFT 20U

#define WDR4_GAMMA_PRE_CURVE19
#define WDR4_GAMMA_PRE_CURVE19_MASK (0xfffff << 0 )
#define WDR4_GAMMA_PRE_CURVE19_SHIFT 0U

#define WDR4_GAMMA_PRE_CURVE18_1
#define WDR4_GAMMA_PRE_CURVE18_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_PRE_CURVE18_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE0_0
#define WDR4_GAMMA_UP_CURVE0_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE0_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE1
#define WDR4_GAMMA_UP_CURVE1_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE1_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE0_1
#define WDR4_GAMMA_UP_CURVE0_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE0_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE2
#define WDR4_GAMMA_UP_CURVE2_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE2_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE3_0
#define WDR4_GAMMA_UP_CURVE3_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE3_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE4
#define WDR4_GAMMA_UP_CURVE4_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE4_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE3_1
#define WDR4_GAMMA_UP_CURVE3_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE3_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE5
#define WDR4_GAMMA_UP_CURVE5_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE5_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE6_0
#define WDR4_GAMMA_UP_CURVE6_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE6_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE7
#define WDR4_GAMMA_UP_CURVE7_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE7_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE6_1
#define WDR4_GAMMA_UP_CURVE6_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE6_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE8
#define WDR4_GAMMA_UP_CURVE8_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE8_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE9_0
#define WDR4_GAMMA_UP_CURVE9_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE9_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE10
#define WDR4_GAMMA_UP_CURVE10_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE10_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE9_1
#define WDR4_GAMMA_UP_CURVE9_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE9_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE11
#define WDR4_GAMMA_UP_CURVE11_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE11_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE12_0
#define WDR4_GAMMA_UP_CURVE12_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE12_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE13
#define WDR4_GAMMA_UP_CURVE13_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE13_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE12_1
#define WDR4_GAMMA_UP_CURVE12_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE12_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE14
#define WDR4_GAMMA_UP_CURVE14_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE14_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE15_0
#define WDR4_GAMMA_UP_CURVE15_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE15_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE16
#define WDR4_GAMMA_UP_CURVE16_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE16_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE15_1
#define WDR4_GAMMA_UP_CURVE15_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE15_1_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE17
#define WDR4_GAMMA_UP_CURVE17_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE17_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE18_0
#define WDR4_GAMMA_UP_CURVE18_0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE18_0_SHIFT 20U

#define WDR4_GAMMA_UP_CURVE19
#define WDR4_GAMMA_UP_CURVE19_MASK (0xfffff << 0 )
#define WDR4_GAMMA_UP_CURVE19_SHIFT 0U

#define WDR4_GAMMA_UP_CURVE18_1
#define WDR4_GAMMA_UP_CURVE18_1_MASK (0x3ff << 20 )
#define WDR4_GAMMA_UP_CURVE18_1_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE0
#define WDR4_GAMMA_DOWN_CURVE0_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE0_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE1
#define WDR4_GAMMA_DOWN_CURVE1_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE1_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE2
#define WDR4_GAMMA_DOWN_CURVE2_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE2_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE3
#define WDR4_GAMMA_DOWN_CURVE3_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE3_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE4
#define WDR4_GAMMA_DOWN_CURVE4_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE4_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE5
#define WDR4_GAMMA_DOWN_CURVE5_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE5_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE6
#define WDR4_GAMMA_DOWN_CURVE6_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE6_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE7
#define WDR4_GAMMA_DOWN_CURVE7_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE7_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE8
#define WDR4_GAMMA_DOWN_CURVE8_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE8_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE9
#define WDR4_GAMMA_DOWN_CURVE9_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE9_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE10
#define WDR4_GAMMA_DOWN_CURVE10_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE10_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE11
#define WDR4_GAMMA_DOWN_CURVE11_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE11_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE12
#define WDR4_GAMMA_DOWN_CURVE12_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE12_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE13
#define WDR4_GAMMA_DOWN_CURVE13_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE13_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE14
#define WDR4_GAMMA_DOWN_CURVE14_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE14_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE15
#define WDR4_GAMMA_DOWN_CURVE15_MASK (0x3ff << 20 )
#define WDR4_GAMMA_DOWN_CURVE15_SHIFT 20U

#define WDR4_GAMMA_DOWN_CURVE16
#define WDR4_GAMMA_DOWN_CURVE16_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE16_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE17
#define WDR4_GAMMA_DOWN_CURVE17_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE17_SHIFT 0U

#define WDR4_GAMMA_DOWN_CURVE18
#define WDR4_GAMMA_DOWN_CURVE18_MASK (0x3ff << 10 )
#define WDR4_GAMMA_DOWN_CURVE18_SHIFT 10U

#define WDR4_GAMMA_DOWN_CURVE19
#define WDR4_GAMMA_DOWN_CURVE19_MASK (0x3ff << 0 )
#define WDR4_GAMMA_DOWN_CURVE19_SHIFT 0U

#define WDR4_DISTANCE_WEIGHT_CURVE0
#define WDR4_DISTANCE_WEIGHT_CURVE0_MASK (0x7f << 21 )
#define WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT 21U

#define WDR4_DISTANCE_WEIGHT_CURVE1
#define WDR4_DISTANCE_WEIGHT_CURVE1_MASK (0x7f << 14 )
#define WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT 14U

#define WDR4_DISTANCE_WEIGHT_CURVE2
#define WDR4_DISTANCE_WEIGHT_CURVE2_MASK (0x7f << 7 )
#define WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT 7U

#define WDR4_DISTANCE_WEIGHT_CURVE3
#define WDR4_DISTANCE_WEIGHT_CURVE3_MASK (0x7f << 0 )
#define WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT 0U

#define WDR4_DISTANCE_WEIGHT_CURVE4
#define WDR4_DISTANCE_WEIGHT_CURVE4_MASK (0x7f << 21 )
#define WDR4_DISTANCE_WEIGHT_CURVE4_SHIFT 21U

#define WDR4_DISTANCE_WEIGHT_CURVE5
#define WDR4_DISTANCE_WEIGHT_CURVE5_MASK (0x7f << 14 )
#define WDR4_DISTANCE_WEIGHT_CURVE5_SHIFT 14U

#define WDR4_DISTANCE_WEIGHT_CURVE6
#define WDR4_DISTANCE_WEIGHT_CURVE6_MASK (0x7f << 7 )
#define WDR4_DISTANCE_WEIGHT_CURVE6_SHIFT 7U

#define WDR4_DISTANCE_WEIGHT_CURVE7
#define WDR4_DISTANCE_WEIGHT_CURVE7_MASK (0x7f << 0 )
#define WDR4_DISTANCE_WEIGHT_CURVE7_SHIFT 0U

#define WDR4_DISTANCE_WEIGHT_CURVE8
#define WDR4_DISTANCE_WEIGHT_CURVE8_MASK (0x7f << 21 )
#define WDR4_DISTANCE_WEIGHT_CURVE8_SHIFT 21U

#define WDR4_DISTANCE_WEIGHT_CURVE9
#define WDR4_DISTANCE_WEIGHT_CURVE9_MASK (0x7f << 14 )
#define WDR4_DISTANCE_WEIGHT_CURVE9_SHIFT 14U

#define WDR4_DISTANCE_WEIGHT_CURVE10
#define WDR4_DISTANCE_WEIGHT_CURVE10_MASK (0x7f << 7 )
#define WDR4_DISTANCE_WEIGHT_CURVE10_SHIFT 7U

#define WDR4_DISTANCE_WEIGHT_CURVE11
#define WDR4_DISTANCE_WEIGHT_CURVE11_MASK (0x7f << 0 )
#define WDR4_DISTANCE_WEIGHT_CURVE11_SHIFT 0U

#define WDR4_DISTANCE_WEIGHT_CURVE12
#define WDR4_DISTANCE_WEIGHT_CURVE12_MASK (0x7f << 21 )
#define WDR4_DISTANCE_WEIGHT_CURVE12_SHIFT 21U

#define WDR4_DISTANCE_WEIGHT_CURVE13
#define WDR4_DISTANCE_WEIGHT_CURVE13_MASK (0x7f << 14 )
#define WDR4_DISTANCE_WEIGHT_CURVE13_SHIFT 14U

#define WDR4_DISTANCE_WEIGHT_CURVE14
#define WDR4_DISTANCE_WEIGHT_CURVE14_MASK (0x7f << 7 )
#define WDR4_DISTANCE_WEIGHT_CURVE14_SHIFT 7U

#define WDR4_DISTANCE_WEIGHT_CURVE15
#define WDR4_DISTANCE_WEIGHT_CURVE15_MASK (0x7f << 0 )
#define WDR4_DISTANCE_WEIGHT_CURVE15_SHIFT 0U

#define WDR4_DISTANCE_WEIGHT_CURVE16
#define WDR4_DISTANCE_WEIGHT_CURVE16_MASK (0x7f << 21 )
#define WDR4_DISTANCE_WEIGHT_CURVE16_SHIFT 21U

#define WDR4_DISTANCE_WEIGHT_CURVE17
#define WDR4_DISTANCE_WEIGHT_CURVE17_MASK (0x7f << 14 )
#define WDR4_DISTANCE_WEIGHT_CURVE17_SHIFT 14U

#define WDR4_DISTANCE_WEIGHT_CURVE18
#define WDR4_DISTANCE_WEIGHT_CURVE18_MASK (0x7f << 7 )
#define WDR4_DISTANCE_WEIGHT_CURVE18_SHIFT 7U

#define WDR4_DISTANCE_WEIGHT_CURVE19
#define WDR4_DISTANCE_WEIGHT_CURVE19_MASK (0x7f << 0 )
#define WDR4_DISTANCE_WEIGHT_CURVE19_SHIFT 0U

#define WDR4_DIFFERENCE_WEIGHT_CURVE0
#define WDR4_DIFFERENCE_WEIGHT_CURVE0_MASK (0x7f << 21 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT 21U

#define WDR4_DIFFERENCE_WEIGHT_CURVE1
#define WDR4_DIFFERENCE_WEIGHT_CURVE1_MASK (0x7f << 14 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT 14U

#define WDR4_DIFFERENCE_WEIGHT_CURVE2
#define WDR4_DIFFERENCE_WEIGHT_CURVE2_MASK (0x7f << 7 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT 7U

#define WDR4_DIFFERENCE_WEIGHT_CURVE3
#define WDR4_DIFFERENCE_WEIGHT_CURVE3_MASK (0x7f << 0 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT 0U

#define WDR4_DIFFERENCE_WEIGHT_CURVE4
#define WDR4_DIFFERENCE_WEIGHT_CURVE4_MASK (0x7f << 21 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE4_SHIFT 21U

#define WDR4_DIFFERENCE_WEIGHT_CURVE5
#define WDR4_DIFFERENCE_WEIGHT_CURVE5_MASK (0x7f << 14 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE5_SHIFT 14U

#define WDR4_DIFFERENCE_WEIGHT_CURVE6
#define WDR4_DIFFERENCE_WEIGHT_CURVE6_MASK (0x7f << 7 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE6_SHIFT 7U

#define WDR4_DIFFERENCE_WEIGHT_CURVE7
#define WDR4_DIFFERENCE_WEIGHT_CURVE7_MASK (0x7f << 0 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE7_SHIFT 0U

#define WDR4_DIFFERENCE_WEIGHT_CURVE8
#define WDR4_DIFFERENCE_WEIGHT_CURVE8_MASK (0x7f << 21 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE8_SHIFT 21U

#define WDR4_DIFFERENCE_WEIGHT_CURVE9
#define WDR4_DIFFERENCE_WEIGHT_CURVE9_MASK (0x7f << 14 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE9_SHIFT 14U

#define WDR4_DIFFERENCE_WEIGHT_CURVE10
#define WDR4_DIFFERENCE_WEIGHT_CURVE10_MASK (0x7f << 7 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE10_SHIFT 7U

#define WDR4_DIFFERENCE_WEIGHT_CURVE11
#define WDR4_DIFFERENCE_WEIGHT_CURVE11_MASK (0x7f << 0 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE11_SHIFT 0U

#define WDR4_DIFFERENCE_WEIGHT_CURVE12
#define WDR4_DIFFERENCE_WEIGHT_CURVE12_MASK (0x7f << 21 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE12_SHIFT 21U

#define WDR4_DIFFERENCE_WEIGHT_CURVE13
#define WDR4_DIFFERENCE_WEIGHT_CURVE13_MASK (0x7f << 14 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE13_SHIFT 14U

#define WDR4_DIFFERENCE_WEIGHT_CURVE14
#define WDR4_DIFFERENCE_WEIGHT_CURVE14_MASK (0x7f << 7 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE14_SHIFT 7U

#define WDR4_DIFFERENCE_WEIGHT_CURVE15
#define WDR4_DIFFERENCE_WEIGHT_CURVE15_MASK (0x7f << 0 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE15_SHIFT 0U

#define WDR4_DIFFERENCE_WEIGHT_CURVE16
#define WDR4_DIFFERENCE_WEIGHT_CURVE16_MASK (0x7f << 21 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE16_SHIFT 21U

#define WDR4_DIFFERENCE_WEIGHT_CURVE17
#define WDR4_DIFFERENCE_WEIGHT_CURVE17_MASK (0x7f << 14 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE17_SHIFT 14U

#define WDR4_DIFFERENCE_WEIGHT_CURVE18
#define WDR4_DIFFERENCE_WEIGHT_CURVE18_MASK (0x7f << 7 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE18_SHIFT 7U

#define WDR4_DIFFERENCE_WEIGHT_CURVE19
#define WDR4_DIFFERENCE_WEIGHT_CURVE19_MASK (0x7f << 0 )
#define WDR4_DIFFERENCE_WEIGHT_CURVE19_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT0
#define WDR4_GLOBAL_CURVE_INVERT0_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT0_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT1
#define WDR4_GLOBAL_CURVE_INVERT1_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT1_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT2
#define WDR4_GLOBAL_CURVE_INVERT2_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT2_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT3
#define WDR4_GLOBAL_CURVE_INVERT3_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT3_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT4
#define WDR4_GLOBAL_CURVE_INVERT4_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT4_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT5
#define WDR4_GLOBAL_CURVE_INVERT5_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT5_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT6
#define WDR4_GLOBAL_CURVE_INVERT6_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT6_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT7
#define WDR4_GLOBAL_CURVE_INVERT7_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT7_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT8
#define WDR4_GLOBAL_CURVE_INVERT8_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT8_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT9
#define WDR4_GLOBAL_CURVE_INVERT9_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT9_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT10
#define WDR4_GLOBAL_CURVE_INVERT10_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT10_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT11
#define WDR4_GLOBAL_CURVE_INVERT11_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT11_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT12
#define WDR4_GLOBAL_CURVE_INVERT12_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT12_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT13
#define WDR4_GLOBAL_CURVE_INVERT13_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT13_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT14
#define WDR4_GLOBAL_CURVE_INVERT14_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT14_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT15
#define WDR4_GLOBAL_CURVE_INVERT15_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT15_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT16
#define WDR4_GLOBAL_CURVE_INVERT16_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT16_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT17
#define WDR4_GLOBAL_CURVE_INVERT17_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT17_SHIFT 0U

#define WDR4_GLOBAL_CURVE_INVERT18
#define WDR4_GLOBAL_CURVE_INVERT18_MASK (0xfff << 12 )
#define WDR4_GLOBAL_CURVE_INVERT18_SHIFT 12U

#define WDR4_GLOBAL_CURVE_INVERT19
#define WDR4_GLOBAL_CURVE_INVERT19_MASK (0xfff << 0 )
#define WDR4_GLOBAL_CURVE_INVERT19_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT0_0
#define WDR4_LINEAR_CURVE_INVERT0_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT0_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT1
#define WDR4_LINEAR_CURVE_INVERT1_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT1_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT0_1
#define WDR4_LINEAR_CURVE_INVERT0_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT0_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT2
#define WDR4_LINEAR_CURVE_INVERT2_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT2_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT3_0
#define WDR4_LINEAR_CURVE_INVERT3_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT3_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT4
#define WDR4_LINEAR_CURVE_INVERT4_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT4_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT3_1
#define WDR4_LINEAR_CURVE_INVERT3_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT3_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT5
#define WDR4_LINEAR_CURVE_INVERT5_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT5_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT6_0
#define WDR4_LINEAR_CURVE_INVERT6_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT6_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT7
#define WDR4_LINEAR_CURVE_INVERT7_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT7_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT6_1
#define WDR4_LINEAR_CURVE_INVERT6_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT6_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT8
#define WDR4_LINEAR_CURVE_INVERT8_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT8_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT9_0
#define WDR4_LINEAR_CURVE_INVERT9_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT9_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT10
#define WDR4_LINEAR_CURVE_INVERT10_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT10_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT9_1
#define WDR4_LINEAR_CURVE_INVERT9_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT9_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT11
#define WDR4_LINEAR_CURVE_INVERT11_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT11_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT12_0
#define WDR4_LINEAR_CURVE_INVERT12_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT12_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT13
#define WDR4_LINEAR_CURVE_INVERT13_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT13_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT12_1
#define WDR4_LINEAR_CURVE_INVERT12_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT12_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT14
#define WDR4_LINEAR_CURVE_INVERT14_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT14_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT15_0
#define WDR4_LINEAR_CURVE_INVERT15_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT15_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT16
#define WDR4_LINEAR_CURVE_INVERT16_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT16_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT15_1
#define WDR4_LINEAR_CURVE_INVERT15_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT15_1_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT17
#define WDR4_LINEAR_CURVE_INVERT17_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT17_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT18_0
#define WDR4_LINEAR_CURVE_INVERT18_0_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT18_0_SHIFT 18U

#define WDR4_LINEAR_CURVE_INVERT19
#define WDR4_LINEAR_CURVE_INVERT19_MASK (0x3ffff << 0 )
#define WDR4_LINEAR_CURVE_INVERT19_SHIFT 0U

#define WDR4_LINEAR_CURVE_INVERT18_1
#define WDR4_LINEAR_CURVE_INVERT18_1_MASK (0x1ff << 18 )
#define WDR4_LINEAR_CURVE_INVERT18_1_SHIFT 18U

#define WDR4_SMOOTH_INVERT_CURVE0
#define WDR4_SMOOTH_INVERT_CURVE0_MASK (0xff << 24 )
#define WDR4_SMOOTH_INVERT_CURVE0_SHIFT 24U

#define WDR4_SMOOTH_INVERT_CURVE1
#define WDR4_SMOOTH_INVERT_CURVE1_MASK (0xff << 16 )
#define WDR4_SMOOTH_INVERT_CURVE1_SHIFT 16U

#define WDR4_SMOOTH_INVERT_CURVE2
#define WDR4_SMOOTH_INVERT_CURVE2_MASK (0xff << 8 )
#define WDR4_SMOOTH_INVERT_CURVE2_SHIFT 8U

#define WDR4_SMOOTH_INVERT_CURVE3
#define WDR4_SMOOTH_INVERT_CURVE3_MASK (0xff << 0 )
#define WDR4_SMOOTH_INVERT_CURVE3_SHIFT 0U

#define WDR4_SMOOTH_INVERT_CURVE4
#define WDR4_SMOOTH_INVERT_CURVE4_MASK (0xff << 24 )
#define WDR4_SMOOTH_INVERT_CURVE4_SHIFT 24U

#define WDR4_SMOOTH_INVERT_CURVE5
#define WDR4_SMOOTH_INVERT_CURVE5_MASK (0xff << 16 )
#define WDR4_SMOOTH_INVERT_CURVE5_SHIFT 16U

#define WDR4_SMOOTH_INVERT_CURVE6
#define WDR4_SMOOTH_INVERT_CURVE6_MASK (0xff << 8 )
#define WDR4_SMOOTH_INVERT_CURVE6_SHIFT 8U

#define WDR4_SMOOTH_INVERT_CURVE7
#define WDR4_SMOOTH_INVERT_CURVE7_MASK (0xff << 0 )
#define WDR4_SMOOTH_INVERT_CURVE7_SHIFT 0U

#define WDR4_SMOOTH_INVERT_CURVE8
#define WDR4_SMOOTH_INVERT_CURVE8_MASK (0xff << 24 )
#define WDR4_SMOOTH_INVERT_CURVE8_SHIFT 24U

#define WDR4_SMOOTH_INVERT_CURVE9
#define WDR4_SMOOTH_INVERT_CURVE9_MASK (0xff << 16 )
#define WDR4_SMOOTH_INVERT_CURVE9_SHIFT 16U

#define WDR4_SMOOTH_INVERT_CURVE10
#define WDR4_SMOOTH_INVERT_CURVE10_MASK (0xff << 8 )
#define WDR4_SMOOTH_INVERT_CURVE10_SHIFT 8U

#define WDR4_SMOOTH_INVERT_CURVE11
#define WDR4_SMOOTH_INVERT_CURVE11_MASK (0xff << 0 )
#define WDR4_SMOOTH_INVERT_CURVE11_SHIFT 0U

#define WDR4_SMOOTH_INVERT_CURVE12
#define WDR4_SMOOTH_INVERT_CURVE12_MASK (0xff << 24 )
#define WDR4_SMOOTH_INVERT_CURVE12_SHIFT 24U

#define WDR4_SMOOTH_INVERT_CURVE13
#define WDR4_SMOOTH_INVERT_CURVE13_MASK (0xff << 16 )
#define WDR4_SMOOTH_INVERT_CURVE13_SHIFT 16U

#define WDR4_SMOOTH_INVERT_CURVE14
#define WDR4_SMOOTH_INVERT_CURVE14_MASK (0xff << 8 )
#define WDR4_SMOOTH_INVERT_CURVE14_SHIFT 8U

#define WDR4_SMOOTH_INVERT_CURVE15
#define WDR4_SMOOTH_INVERT_CURVE15_MASK (0xff << 0 )
#define WDR4_SMOOTH_INVERT_CURVE15_SHIFT 0U

#define WDR4_SMOOTH_INVERT_CURVE16
#define WDR4_SMOOTH_INVERT_CURVE16_MASK (0xff << 24 )
#define WDR4_SMOOTH_INVERT_CURVE16_SHIFT 24U

#define WDR4_SMOOTH_INVERT_CURVE17
#define WDR4_SMOOTH_INVERT_CURVE17_MASK (0xff << 16 )
#define WDR4_SMOOTH_INVERT_CURVE17_SHIFT 16U

#define WDR4_SMOOTH_INVERT_CURVE18
#define WDR4_SMOOTH_INVERT_CURVE18_MASK (0xff << 8 )
#define WDR4_SMOOTH_INVERT_CURVE18_SHIFT 8U

#define WDR4_SMOOTH_INVERT_CURVE19
#define WDR4_SMOOTH_INVERT_CURVE19_MASK (0xff << 0 )
#define WDR4_SMOOTH_INVERT_CURVE19_SHIFT 0U

#define WDR4_HISTOGRAM_SHIFT0
#define WDR4_HISTOGRAM_SHIFT0_MASK (0x1f << 25 )
#define WDR4_HISTOGRAM_SHIFT0_SHIFT 25U

#define WDR4_HISTOGRAM_SHIFT1
#define WDR4_HISTOGRAM_SHIFT1_MASK (0x1f << 20 )
#define WDR4_HISTOGRAM_SHIFT1_SHIFT 20U

#define WDR4_HISTOGRAM_SHIFT2
#define WDR4_HISTOGRAM_SHIFT2_MASK (0x1f << 15 )
#define WDR4_HISTOGRAM_SHIFT2_SHIFT 15U

#define WDR4_HISTOGRAM_SHIFT3
#define WDR4_HISTOGRAM_SHIFT3_MASK (0x1f << 10 )
#define WDR4_HISTOGRAM_SHIFT3_SHIFT 10U

#define WDR4_HISTOGRAM_SHIFT4
#define WDR4_HISTOGRAM_SHIFT4_MASK (0x1f << 5 )
#define WDR4_HISTOGRAM_SHIFT4_SHIFT 5U

#define WDR4_HISTOGRAM_SHIFT5
#define WDR4_HISTOGRAM_SHIFT5_MASK (0x1f << 0 )
#define WDR4_HISTOGRAM_SHIFT5_SHIFT 0U

#define WDR4_HISTOGRAM_SHIFT6
#define WDR4_HISTOGRAM_SHIFT6_MASK (0x1f << 25 )
#define WDR4_HISTOGRAM_SHIFT6_SHIFT 25U

#define WDR4_HISTOGRAM_SHIFT7
#define WDR4_HISTOGRAM_SHIFT7_MASK (0x1f << 20 )
#define WDR4_HISTOGRAM_SHIFT7_SHIFT 20U

#define WDR4_HISTOGRAM_SHIFT8
#define WDR4_HISTOGRAM_SHIFT8_MASK (0x1f << 15 )
#define WDR4_HISTOGRAM_SHIFT8_SHIFT 15U

#define WDR4_HISTOGRAM_SHIFT9
#define WDR4_HISTOGRAM_SHIFT9_MASK (0x1f << 10 )
#define WDR4_HISTOGRAM_SHIFT9_SHIFT 10U

#define WDR4_HISTOGRAM_SHIFT10
#define WDR4_HISTOGRAM_SHIFT10_MASK (0x1f << 5 )
#define WDR4_HISTOGRAM_SHIFT10_SHIFT 5U

#define WDR4_HISTOGRAM_SHIFT11
#define WDR4_HISTOGRAM_SHIFT11_MASK (0x1f << 0 )
#define WDR4_HISTOGRAM_SHIFT11_SHIFT 0U

#define WDR4_HISTOGRAM_SHIFT12
#define WDR4_HISTOGRAM_SHIFT12_MASK (0x1f << 25 )
#define WDR4_HISTOGRAM_SHIFT12_SHIFT 25U

#define WDR4_HISTOGRAM_SHIFT13
#define WDR4_HISTOGRAM_SHIFT13_MASK (0x1f << 20 )
#define WDR4_HISTOGRAM_SHIFT13_SHIFT 20U

#define WDR4_HISTOGRAM_SHIFT14
#define WDR4_HISTOGRAM_SHIFT14_MASK (0x1f << 15 )
#define WDR4_HISTOGRAM_SHIFT14_SHIFT 15U

#define WDR4_HISTOGRAM_SHIFT15
#define WDR4_HISTOGRAM_SHIFT15_MASK (0x1f << 10 )
#define WDR4_HISTOGRAM_SHIFT15_SHIFT 10U

#define WDR4_HISTOGRAM_SHIFT16
#define WDR4_HISTOGRAM_SHIFT16_MASK (0x1f << 5 )
#define WDR4_HISTOGRAM_SHIFT16_SHIFT 5U

#define WDR4_HISTOGRAM_SHIFT17
#define WDR4_HISTOGRAM_SHIFT17_MASK (0x1f << 0 )
#define WDR4_HISTOGRAM_SHIFT17_SHIFT 0U

#define WDR4_HISTOGRAM_SHIFT18
#define WDR4_HISTOGRAM_SHIFT18_MASK (0x1f << 5 )
#define WDR4_HISTOGRAM_SHIFT18_SHIFT 5U

#define WDR4_HISTOGRAM_SHIFT19
#define WDR4_HISTOGRAM_SHIFT19_MASK (0x1f << 0 )
#define WDR4_HISTOGRAM_SHIFT19_SHIFT 0U

#define WDR4_HISTOGRAM0_SHIFT0
#define WDR4_HISTOGRAM0_SHIFT0_MASK (0xf << 28 )
#define WDR4_HISTOGRAM0_SHIFT0_SHIFT 28U

#define WDR4_HISTOGRAM0_SHIFT1
#define WDR4_HISTOGRAM0_SHIFT1_MASK (0xf << 24 )
#define WDR4_HISTOGRAM0_SHIFT1_SHIFT 24U

#define WDR4_HISTOGRAM0_SHIFT2
#define WDR4_HISTOGRAM0_SHIFT2_MASK (0xf << 20 )
#define WDR4_HISTOGRAM0_SHIFT2_SHIFT 20U

#define WDR4_HISTOGRAM0_SHIFT3
#define WDR4_HISTOGRAM0_SHIFT3_MASK (0xf << 16 )
#define WDR4_HISTOGRAM0_SHIFT3_SHIFT 16U

#define WDR4_HISTOGRAM0_SHIFT4
#define WDR4_HISTOGRAM0_SHIFT4_MASK (0xf << 12 )
#define WDR4_HISTOGRAM0_SHIFT4_SHIFT 12U

#define WDR4_HISTOGRAM0_SHIFT5
#define WDR4_HISTOGRAM0_SHIFT5_MASK (0xf << 8 )
#define WDR4_HISTOGRAM0_SHIFT5_SHIFT 8U

#define WDR4_HISTOGRAM0_SHIFT6
#define WDR4_HISTOGRAM0_SHIFT6_MASK (0xf << 4 )
#define WDR4_HISTOGRAM0_SHIFT6_SHIFT 4U

#define WDR4_HISTOGRAM0_SHIFT7
#define WDR4_HISTOGRAM0_SHIFT7_MASK (0xf << 0 )
#define WDR4_HISTOGRAM0_SHIFT7_SHIFT 0U

#define WDR4_HISTOGRAM0_SHIFT8
#define WDR4_HISTOGRAM0_SHIFT8_MASK (0xf << 28 )
#define WDR4_HISTOGRAM0_SHIFT8_SHIFT 28U

#define WDR4_HISTOGRAM0_SHIFT9
#define WDR4_HISTOGRAM0_SHIFT9_MASK (0xf << 24 )
#define WDR4_HISTOGRAM0_SHIFT9_SHIFT 24U

#define WDR4_HISTOGRAM0_SHIFT10
#define WDR4_HISTOGRAM0_SHIFT10_MASK (0xf << 20 )
#define WDR4_HISTOGRAM0_SHIFT10_SHIFT 20U

#define WDR4_HISTOGRAM0_SHIFT11
#define WDR4_HISTOGRAM0_SHIFT11_MASK (0xf << 16 )
#define WDR4_HISTOGRAM0_SHIFT11_SHIFT 16U

#define WDR4_HISTOGRAM0_SHIFT12
#define WDR4_HISTOGRAM0_SHIFT12_MASK (0xf << 12 )
#define WDR4_HISTOGRAM0_SHIFT12_SHIFT 12U

#define WDR4_HISTOGRAM0_SHIFT13
#define WDR4_HISTOGRAM0_SHIFT13_MASK (0xf << 8 )
#define WDR4_HISTOGRAM0_SHIFT13_SHIFT 8U

#define WDR4_HISTOGRAM0_SHIFT14
#define WDR4_HISTOGRAM0_SHIFT14_MASK (0xf << 4 )
#define WDR4_HISTOGRAM0_SHIFT14_SHIFT 4U

#define WDR4_HISTOGRAM0_SHIFT15
#define WDR4_HISTOGRAM0_SHIFT15_MASK (0xf << 0 )
#define WDR4_HISTOGRAM0_SHIFT15_SHIFT 0U

#define WDR4_HISTOGRAM0_SHIFT16
#define WDR4_HISTOGRAM0_SHIFT16_MASK (0xf << 12 )
#define WDR4_HISTOGRAM0_SHIFT16_SHIFT 12U

#define WDR4_HISTOGRAM0_SHIFT17
#define WDR4_HISTOGRAM0_SHIFT17_MASK (0xf << 8 )
#define WDR4_HISTOGRAM0_SHIFT17_SHIFT 8U

#define WDR4_HISTOGRAM0_SHIFT18
#define WDR4_HISTOGRAM0_SHIFT18_MASK (0xf << 4 )
#define WDR4_HISTOGRAM0_SHIFT18_SHIFT 4U

#define WDR4_HISTOGRAM0_SHIFT19
#define WDR4_HISTOGRAM0_SHIFT19_MASK (0xf << 0 )
#define WDR4_HISTOGRAM0_SHIFT19_SHIFT 0U

#define WDR4_TOTAL_STRENGTH_SHD
#define WDR4_TOTAL_STRENGTH_SHD_MASK (0xff << 24 )
#define WDR4_TOTAL_STRENGTH_SHD_SHIFT 24U

#define WDR4_LOCAL_STRENGTH_SHD
#define WDR4_LOCAL_STRENGTH_SHD_MASK (0xff << 16 )
#define WDR4_LOCAL_STRENGTH_SHD_SHIFT 16U

#define WDR4_GLOBAL_STRENGTH_SHD
#define WDR4_GLOBAL_STRENGTH_SHD_MASK (0xff << 8 )
#define WDR4_GLOBAL_STRENGTH_SHD_SHIFT 8U

#define WDR4_LOW_STRENGTH_SHD
#define WDR4_LOW_STRENGTH_SHD_MASK (0xff << 0 )
#define WDR4_LOW_STRENGTH_SHD_SHIFT 0U

#define WDR4_HIGH_STRENGTH_SHD
#define WDR4_HIGH_STRENGTH_SHD_MASK (0xff << 16 )
#define WDR4_HIGH_STRENGTH_SHD_SHIFT 16U

#define WDR4_DRC_BAYER_RATIOLSVS_SHD
#define WDR4_DRC_BAYER_RATIOLSVS_SHD_MASK (0xff << 8 )
#define WDR4_DRC_BAYER_RATIOLSVS_SHD_SHIFT 8U

#define WDR4_DRC_BAYER_RATIO_SHD
#define WDR4_DRC_BAYER_RATIO_SHD_MASK (0xff << 0 )
#define WDR4_DRC_BAYER_RATIO_SHD_SHIFT 0U

#define WDR4_CONTRAST_SHD
#define WDR4_CONTRAST_SHD_MASK (0x7ff << 10 )
#define WDR4_CONTRAST_SHD_SHIFT 10U

#define WDR4_FLAT_STRENGTH_SHD
#define WDR4_FLAT_STRENGTH_SHD_MASK (0x1f << 5 )
#define WDR4_FLAT_STRENGTH_SHD_SHIFT 5U

#define WDR4_FLAT_THR_SHD
#define WDR4_FLAT_THR_SHD_MASK (0x1f << 0 )
#define WDR4_FLAT_THR_SHD_SHIFT 0U

#define WDR4_PIXEL_MERGE_SLOPE_SHD
#define WDR4_PIXEL_MERGE_SLOPE_SHD_MASK (0xff << 24 )
#define WDR4_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U

#define WDR4_PIXEL_MERGE_BASE_SHD
#define WDR4_PIXEL_MERGE_BASE_SHD_MASK (0xff << 16 )
#define WDR4_PIXEL_MERGE_BASE_SHD_SHIFT 16U

#define WDR4_PIXEL_ADJUST_SLOPE_SHD
#define WDR4_PIXEL_ADJUST_SLOPE_SHD_MASK (0xff << 8 )
#define WDR4_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U

#define WDR4_PIXEL_ADJUST_BASE_SHD
#define WDR4_PIXEL_ADJUST_BASE_SHD_MASK (0xff << 0 )
#define WDR4_PIXEL_ADJUST_BASE_SHD_SHIFT 0U

#define WDR4_ENABLE_SHD
#define WDR4_ENABLE_SHD_MASK 0x1 << 20
#define WDR4_ENABLE_SHD_SHIFT 20U

#define WDR4_ENTROPY_SLOPE_SHD
#define WDR4_ENTROPY_SLOPE_SHD_MASK (0x3ff << 10 )
#define WDR4_ENTROPY_SLOPE_SHD_SHIFT 10U

#define WDR4_ENTROPY_BASE_SHD
#define WDR4_ENTROPY_BASE_SHD_MASK (0x3ff << 0 )
#define WDR4_ENTROPY_BASE_SHD_SHIFT 0U

#define DENOISE3D_V20_INVGAMMA_EN
#define DENOISE3D_V20_INVGAMMA_EN_MASK (0x1 << 11)
#define DENOISE3D_V20_INVGAMMA_EN_SHIFT 11U

#define DENOISE3D_V20_PREGAMMA_EN
#define DENOISE3D_V20_PREGAMMA_EN_MASK (0x1 << 10)
#define DENOISE3D_V20_PREGAMMA_EN_SHIFT 10U

#define DENOISE3D_V20_ERODE_EN
#define DENOISE3D_V20_ERODE_EN_MASK (0x1 << 9)
#define DENOISE3D_V20_ERODE_EN_SHIFT 9U

#define DENOISE3D_V20_MOTION_CONV_EN
#define DENOISE3D_V20_MOTION_CONV_EN_MASK (0x1 << 8)
#define DENOISE3D_V20_MOTION_CONV_EN_SHIFT 8U

#define DENOISE3D_V20_INV_DGAIN_EN
#define DENOISE3D_V20_INV_DGAIN_EN_MASK (0x1 << 7)
#define DENOISE3D_V20_INV_DGAIN_EN_SHIFT 7U

#define DENOISE3D_V20_INV_AWB_GAIN_EN
#define DENOISE3D_V20_INV_AWB_GAIN_EN_MASK (0x1 << 6)
#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHIFT 6U

#define DENOISE3D_V20_COMP_LUMA_EN
#define DENOISE3D_V20_COMP_LUMA_EN_MASK (0x1 << 5)
#define DENOISE3D_V20_COMP_LUMA_EN_SHIFT 5U

#define DENOISE3D_V20_REF_RESET
#define DENOISE3D_V20_REF_RESET_MASK (0x1 << 4)
#define DENOISE3D_V20_REF_RESET_SHIFT 4U

#define DENOISE3D_V20_MOTION_DILATE_ENABLE
#define DENOISE3D_V20_MOTION_DILATE_ENABLE_MASK (0x1 << 3)
#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHIFT 3U

#define DENOISE3D_V20_NLM_ENABLE
#define DENOISE3D_V20_NLM_ENABLE_MASK (0x1 << 2)
#define DENOISE3D_V20_NLM_ENABLE_SHIFT 2U

#define DENOISE3D_V20_TNR_ENABLE
#define DENOISE3D_V20_TNR_ENABLE_MASK (0x1 << 1)
#define DENOISE3D_V20_TNR_ENABLE_SHIFT 1U

#define DENOISE3D_V20_ENABLE
#define DENOISE3D_V20_ENABLE_MASK (0x1 << 0)
#define DENOISE3D_V20_ENABLE_SHIFT 0U

#define DENOISE3D_V20_TNR_STRENGTH
#define DENOISE3D_V20_TNR_STRENGTH_MASK (0xff << 0 )
#define DENOISE3D_V20_TNR_STRENGTH_SHIFT 0U

#define DENOISE3D_V20_NOISE_LEVEL
#define DENOISE3D_V20_NOISE_LEVEL_MASK (0xffff << 16 )
#define DENOISE3D_V20_NOISE_LEVEL_SHIFT 16U

#define DENOISE3D_V20_NOISE_MEAN
#define DENOISE3D_V20_NOISE_MEAN_MASK (0xffff << 0 )
#define DENOISE3D_V20_NOISE_MEAN_SHIFT 0U

#define DENOISE3D_V20_NOSIE_THRESH
#define DENOISE3D_V20_NOSIE_THRESH_MASK (0xffff << 16 )
#define DENOISE3D_V20_NOSIE_THRESH_SHIFT 16U

#define DENOISE3D_V20_MOTION_MEAN
#define DENOISE3D_V20_MOTION_MEAN_MASK (0xffff << 0 )
#define DENOISE3D_V20_MOTION_MEAN_SHIFT 0U

#define DENOISE3D_V20_TNR_RANGE_H
#define DENOISE3D_V20_TNR_RANGE_H_MASK (0xf << 12 )
#define DENOISE3D_V20_TNR_RANGE_H_SHIFT 12U

#define DENOISE3D_V20_TNR_RANGE_V
#define DENOISE3D_V20_TNR_RANGE_V_MASK (0xf << 8 )
#define DENOISE3D_V20_TNR_RANGE_V_SHIFT 8U

#define DENOISE3D_V20_TNR_DILATE_RANGE_H
#define DENOISE3D_V20_TNR_DILATE_RANGE_H_MASK (0xf << 4 )
#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHIFT 4U

#define DENOISE3D_V20_TNR_DILATE_RANGE_V
#define DENOISE3D_V20_TNR_DILATE_RANGE_V_MASK (0xf << 0 )
#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHIFT 0U

#define DENOISE3D_V20_MOTION_INV
#define DENOISE3D_V20_MOTION_INV_MASK (0xfffff << 0 )
#define DENOISE3D_V20_MOTION_INV_SHIFT 0U

#define DENOISE3D_V20_THR_UPDATE
#define DENOISE3D_V20_THR_UPDATE_MASK (0x7ff << 16 )
#define DENOISE3D_V20_THR_UPDATE_SHIFT 16U

#define DENOISE3D_V20_MOTION_THR_UPDATE
#define DENOISE3D_V20_MOTION_THR_UPDATE_MASK (0x7ff << 0 )
#define DENOISE3D_V20_MOTION_THR_UPDATE_SHIFT 0U

#define DENOISE3D_V20_MOTION_PRE_WEIGHT
#define DENOISE3D_V20_MOTION_PRE_WEIGHT_MASK (0x3f << 16 )
#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHIFT 16U

#define DENOISE3D_V20_MOTION_SLOPE
#define DENOISE3D_V20_MOTION_SLOPE_MASK (0x7ff << 0 )
#define DENOISE3D_V20_MOTION_SLOPE_SHIFT 0U

#define DENOISE3D_V20_MOTION_CONV_SHIFT
#define DENOISE3D_V20_MOTION_CONV_SHIFT_MASK (0xf << 28 )
#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHIFT 28U

#define DENOISE3D_V20_MOTION_CONV_MAX
#define DENOISE3D_V20_MOTION_CONV_MAX_MASK (0x7ff << 17 )
#define DENOISE3D_V20_MOTION_CONV_MAX_SHIFT 17U

#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT
#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_MASK (0x3f << 11 )
#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHIFT 11U

#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT
#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_MASK (0x3f << 5 )
#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHIFT 5U

#define DENOISE3D_V20_SAD_WEIGHT
#define DENOISE3D_V20_SAD_WEIGHT_MASK (0x1f << 0 )
#define DENOISE3D_V20_SAD_WEIGHT_SHIFT 0U

#define DENOISE3D_V20_PIXEL_VAL_SHIFT
#define DENOISE3D_V20_PIXEL_VAL_SHIFT_MASK (0x7ff << 20 )
#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHIFT 20U

#define DENOISE3D_V20_PIXEL_SLOP
#define DENOISE3D_V20_PIXEL_SLOP_MASK (0xff << 12 )
#define DENOISE3D_V20_PIXEL_SLOP_SHIFT 12U

#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT
#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_MASK (0xf << 8 )
#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_SHIFT 8U

#define DENOISE3D_V20_PIXEL_SLOP_MIN
#define DENOISE3D_V20_PIXEL_SLOP_MIN_MASK (0xff << 0 )
#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHIFT 0U

#define DENOISE3D_V20_INVGAMMA_EN_SHD
#define DENOISE3D_V20_INVGAMMA_EN_SHD_MASK 0x1 << 11
#define DENOISE3D_V20_INVGAMMA_EN_SHD_SHIFT 11U

#define DENOISE3D_V20_PREGAMMA_EN_SHD
#define DENOISE3D_V20_PREGAMMA_EN_SHD_MASK 0x1 << 10
#define DENOISE3D_V20_PREGAMMA_EN_SHD_SHIFT 10U

#define DENOISE3D_V20_ERODE_EN_SHD
#define DENOISE3D_V20_ERODE_EN_SHD_MASK 0x1 << 9
#define DENOISE3D_V20_ERODE_EN_SHD_SHIFT 9U

#define DENOISE3D_V20_MOTION_CONV_EN_SHD
#define DENOISE3D_V20_MOTION_CONV_EN_SHD_MASK 0x1 << 8
#define DENOISE3D_V20_MOTION_CONV_EN_SHD_SHIFT 8U

#define DENOISE3D_V20_INV_DGAIN_EN_SHD
#define DENOISE3D_V20_INV_DGAIN_EN_SHD_MASK 0x1 << 7
#define DENOISE3D_V20_INV_DGAIN_EN_SHD_SHIFT 7U

#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD
#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_MASK 0x1 << 6
#define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_SHIFT 6U

#define DENOISE3D_V20_COMP_LUMA_EN_SHD
#define DENOISE3D_V20_COMP_LUMA_EN_SHD_MASK 0x1 << 5
#define DENOISE3D_V20_COMP_LUMA_EN_SHD_SHIFT 5U

#define DENOISE3D_V20_REF_RESET_SHD
#define DENOISE3D_V20_REF_RESET_SHD_MASK 0x1 << 4
#define DENOISE3D_V20_REF_RESET_SHD_SHIFT 4U

#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD
#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_MASK 0x1 << 3
#define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_SHIFT 3U

#define DENOISE3D_V20_NLM_ENABLE_SHD
#define DENOISE3D_V20_NLM_ENABLE_SHD_MASK 0x1 << 2
#define DENOISE3D_V20_NLM_ENABLE_SHD_SHIFT 2U

#define DENOISE3D_V20_TNR_ENABLE_SHD
#define DENOISE3D_V20_TNR_ENABLE_SHD_MASK 0x1 << 1
#define DENOISE3D_V20_TNR_ENABLE_SHD_SHIFT 1U

#define DENOISE3D_V20_ENABLE_SHD
#define DENOISE3D_V20_ENABLE_SHD_MASK 0x1 << 0
#define DENOISE3D_V20_ENABLE_SHD_SHIFT 0U

#define DENOISE3D_V20_TNR_STRENGTH_SHD
#define DENOISE3D_V20_TNR_STRENGTH_SHD_MASK (0xff << 0 )
#define DENOISE3D_V20_TNR_STRENGTH_SHD_SHIFT 0U

#define DENOISE3D_V20_NOISE_LEVEL_SHD
#define DENOISE3D_V20_NOISE_LEVEL_SHD_MASK (0x3fff << 16 )
#define DENOISE3D_V20_NOISE_LEVEL_SHD_SHIFT 16U

#define DENOISE3D_V20_NOISE_MEAN_SHD
#define DENOISE3D_V20_NOISE_MEAN_SHD_MASK (0x3fff << 0 )
#define DENOISE3D_V20_NOISE_MEAN_SHD_SHIFT 0U

#define DENOISE3D_V20_NOSIE_THRESH_SHD
#define DENOISE3D_V20_NOSIE_THRESH_SHD_MASK (0x3fff << 16 )
#define DENOISE3D_V20_NOSIE_THRESH_SHD_SHIFT 16U

#define DENOISE3D_V20_MOTION_MEAN_SHD
#define DENOISE3D_V20_MOTION_MEAN_SHD_MASK (0x3fff << 0 )
#define DENOISE3D_V20_MOTION_MEAN_SHD_SHIFT 0U

#define DENOISE3D_V20_TNR_RANGE_H_SHD
#define DENOISE3D_V20_TNR_RANGE_H_SHD_MASK (0x3 << 8 )
#define DENOISE3D_V20_TNR_RANGE_H_SHD_SHIFT 8U

#define DENOISE3D_V20_TNR_RANGE_V_SHD
#define DENOISE3D_V20_TNR_RANGE_V_SHD_MASK (0x3 << 6 )
#define DENOISE3D_V20_TNR_RANGE_V_SHD_SHIFT 6U

#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD
#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_MASK (0x7 << 3 )
#define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_SHIFT 3U

#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD
#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_MASK (0x7 << 0 )
#define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_SHIFT 0U

#define DENOISE3D_V20_MOTION_INV_SHD
#define DENOISE3D_V20_MOTION_INV_SHD_MASK (0xfffff << 0 )
#define DENOISE3D_V20_MOTION_INV_SHD_SHIFT 0U

#define DENOISE3D_V20_THR_UPDATE_SHD
#define DENOISE3D_V20_THR_UPDATE_SHD_MASK (0x7ff << 16 )
#define DENOISE3D_V20_THR_UPDATE_SHD_SHIFT 16U

#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD
#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_MASK (0x7ff << 0 )
#define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_SHIFT 0U

#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD
#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_MASK (0x7ff << 16 )
#define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_SHIFT 16U

#define DENOISE3D_V20_MOTION_SLOPE_SHD
#define DENOISE3D_V20_MOTION_SLOPE_SHD_MASK (0x7ff << 0 )
#define DENOISE3D_V20_MOTION_SLOPE_SHD_SHIFT 0U

#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD
#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_MASK (0xf << 28 )
#define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_SHIFT 28U

#define DENOISE3D_V20_MOTION_CONV_MAX_SHD
#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_MASK (0x7ff << 17 )
#define DENOISE3D_V20_MOTION_CONV_MAX_SHD_SHIFT 17U

#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD
#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_MASK (0x3f << 11 )
#define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_SHIFT 11U

#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD
#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_MASK (0x3f << 5 )
#define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_SHIFT 5U

#define DENOISE3D_V20_SAD_WEIGHT_SHD
#define DENOISE3D_V20_SAD_WEIGHT_SHD_MASK (0x1f << 0 )
#define DENOISE3D_V20_SAD_WEIGHT_SHD_SHIFT 0U

#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD
#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_MASK (0x7ff << 20 )
#define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_SHIFT 20U

#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD
#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_MASK (0xff << 12 )
#define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_SHIFT 12U

#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD
#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_MASK (0xf << 8 )
#define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_SHIFT 8U

#define DENOISE3D_V20_BG_VAL_SUM
#define DENOISE3D_V20_BG_VAL_SUM_MASK (0xffffffff << 0 )
#define DENOISE3D_V20_BG_VAL_SUM_SHIFT 0U

#define DENOISE3D_V20_MO_VAL_SUM
#define DENOISE3D_V20_MO_VAL_SUM_MASK (0xffffffff << 0 )
#define DENOISE3D_V20_MO_VAL_SUM_SHIFT 0U

#define DENOISE3D_V20_BG_PIX_CNT
#define DENOISE3D_V20_BG_PIX_CNT_MASK (0xffffffff << 0 )
#define DENOISE3D_V20_BG_PIX_CNT_SHIFT 0U

#define DENOISE3D_V20_MO_PIX_CNT
#define DENOISE3D_V20_MO_PIX_CNT_MASK (0xffffffff << 0 )
#define DENOISE3D_V20_MO_PIX_CNT_SHIFT 0U

#define DENOISE3D_V20_FRAME_AVG
#define DENOISE3D_V20_FRAME_AVG_MASK (0xffffffff << 0 )
#define DENOISE3D_V20_FRAME_AVG_SHIFT 0U

#define DENOISE3D_V20_DUMMY_HBLANK
#define DENOISE3D_V20_DUMMY_HBLANK_MASK (0xffff << 0 )
#define DENOISE3D_V20_DUMMY_HBLANK_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_2_A
#define DENOISE3D2_PREGAMMA_Y_2_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_2_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_1
#define DENOISE3D2_PREGAMMA_Y_1_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_1_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_0
#define DENOISE3D2_PREGAMMA_Y_0_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_0_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_2_B
#define DENOISE3D2_PREGAMMA_Y_2_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_2_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_4
#define DENOISE3D2_PREGAMMA_Y_4_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_4_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_3
#define DENOISE3D2_PREGAMMA_Y_3_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_3_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_7_A
#define DENOISE3D2_PREGAMMA_Y_7_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_7_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_6
#define DENOISE3D2_PREGAMMA_Y_6_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_6_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_5
#define DENOISE3D2_PREGAMMA_Y_5_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_5_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_7_B
#define DENOISE3D2_PREGAMMA_Y_7_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_7_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_9
#define DENOISE3D2_PREGAMMA_Y_9_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_9_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_8
#define DENOISE3D2_PREGAMMA_Y_8_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_8_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_12_A
#define DENOISE3D2_PREGAMMA_Y_12_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_12_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_11
#define DENOISE3D2_PREGAMMA_Y_11_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_11_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_10
#define DENOISE3D2_PREGAMMA_Y_10_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_10_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_12_B
#define DENOISE3D2_PREGAMMA_Y_12_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_12_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_14
#define DENOISE3D2_PREGAMMA_Y_14_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_14_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_13
#define DENOISE3D2_PREGAMMA_Y_13_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_13_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_17_A
#define DENOISE3D2_PREGAMMA_Y_17_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_17_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_16
#define DENOISE3D2_PREGAMMA_Y_16_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_16_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_15
#define DENOISE3D2_PREGAMMA_Y_15_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_15_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_17_B
#define DENOISE3D2_PREGAMMA_Y_17_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_17_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_19
#define DENOISE3D2_PREGAMMA_Y_19_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_19_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_18
#define DENOISE3D2_PREGAMMA_Y_18_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_18_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_22_A
#define DENOISE3D2_PREGAMMA_Y_22_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_22_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_21
#define DENOISE3D2_PREGAMMA_Y_21_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_21_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_20
#define DENOISE3D2_PREGAMMA_Y_20_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_20_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_22_B
#define DENOISE3D2_PREGAMMA_Y_22_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_22_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_24
#define DENOISE3D2_PREGAMMA_Y_24_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_24_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_23
#define DENOISE3D2_PREGAMMA_Y_23_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_23_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_27_A
#define DENOISE3D2_PREGAMMA_Y_27_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_27_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_26
#define DENOISE3D2_PREGAMMA_Y_26_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_26_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_25
#define DENOISE3D2_PREGAMMA_Y_25_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_25_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_27_B
#define DENOISE3D2_PREGAMMA_Y_27_B_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_27_B_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_29
#define DENOISE3D2_PREGAMMA_Y_29_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_29_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_28
#define DENOISE3D2_PREGAMMA_Y_28_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_28_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_32_A
#define DENOISE3D2_PREGAMMA_Y_32_A_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_32_A_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_31
#define DENOISE3D2_PREGAMMA_Y_31_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_31_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_30
#define DENOISE3D2_PREGAMMA_Y_30_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_30_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_32_B
#define DENOISE3D2_PREGAMMA_Y_32_B_MASK (0x3f << 0 )
#define DENOISE3D2_PREGAMMA_Y_32_B_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_2_A_SHD
#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_2_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_1_SHD
#define DENOISE3D2_PREGAMMA_Y_1_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_1_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_0_SHD
#define DENOISE3D2_PREGAMMA_Y_0_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_0_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_2_B_SHD
#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_2_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_4_SHD
#define DENOISE3D2_PREGAMMA_Y_4_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_4_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_3_SHD
#define DENOISE3D2_PREGAMMA_Y_3_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_3_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_7_A_SHD
#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_7_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_6_SHD
#define DENOISE3D2_PREGAMMA_Y_6_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_6_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_5_SHD
#define DENOISE3D2_PREGAMMA_Y_5_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_5_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_7_B_SHD
#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_7_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_9_SHD
#define DENOISE3D2_PREGAMMA_Y_9_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_9_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_8_SHD
#define DENOISE3D2_PREGAMMA_Y_8_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_8_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_12_A_SHD
#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_12_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_11_SHD
#define DENOISE3D2_PREGAMMA_Y_11_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_11_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_10_SHD
#define DENOISE3D2_PREGAMMA_Y_10_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_10_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_12_B_SHD
#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_12_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_14_SHD
#define DENOISE3D2_PREGAMMA_Y_14_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_14_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_13_SHD
#define DENOISE3D2_PREGAMMA_Y_13_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_13_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_17_A_SHD
#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_17_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_16_SHD
#define DENOISE3D2_PREGAMMA_Y_16_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_16_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_15_SHD
#define DENOISE3D2_PREGAMMA_Y_15_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_15_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_17_B_SHD
#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_17_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_19_SHD
#define DENOISE3D2_PREGAMMA_Y_19_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_19_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_18_SHD
#define DENOISE3D2_PREGAMMA_Y_18_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_18_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_22_A_SHD
#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_22_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_21_SHD
#define DENOISE3D2_PREGAMMA_Y_21_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_21_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_20_SHD
#define DENOISE3D2_PREGAMMA_Y_20_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_20_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_22_B_SHD
#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_22_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_24_SHD
#define DENOISE3D2_PREGAMMA_Y_24_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_24_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_23_SHD
#define DENOISE3D2_PREGAMMA_Y_23_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_23_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_27_A_SHD
#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_27_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_26_SHD
#define DENOISE3D2_PREGAMMA_Y_26_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_26_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_25_SHD
#define DENOISE3D2_PREGAMMA_Y_25_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_25_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_27_B_SHD
#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_27_B_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_29_SHD
#define DENOISE3D2_PREGAMMA_Y_29_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_29_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_28_SHD
#define DENOISE3D2_PREGAMMA_Y_28_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_28_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_32_A_SHD
#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_PREGAMMA_Y_32_A_SHD_SHIFT 24U

#define DENOISE3D2_PREGAMMA_Y_31_SHD
#define DENOISE3D2_PREGAMMA_Y_31_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_PREGAMMA_Y_31_SHD_SHIFT 12U

#define DENOISE3D2_PREGAMMA_Y_30_SHD
#define DENOISE3D2_PREGAMMA_Y_30_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_PREGAMMA_Y_30_SHD_SHIFT 0U

#define DENOISE3D2_PREGAMMA_Y_32_B_SHD
#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_MASK (0x3f << 0 )
#define DENOISE3D2_PREGAMMA_Y_32_B_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_2_A
#define DENOISE3D2_INVGAMMA_Y_2_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_2_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_1
#define DENOISE3D2_INVGAMMA_Y_1_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_1_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_0
#define DENOISE3D2_INVGAMMA_Y_0_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_0_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_2_B
#define DENOISE3D2_INVGAMMA_Y_2_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_2_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_4
#define DENOISE3D2_INVGAMMA_Y_4_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_4_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_3
#define DENOISE3D2_INVGAMMA_Y_3_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_3_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_7_A
#define DENOISE3D2_INVGAMMA_Y_7_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_7_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_6
#define DENOISE3D2_INVGAMMA_Y_6_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_6_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_5
#define DENOISE3D2_INVGAMMA_Y_5_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_5_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_7_B
#define DENOISE3D2_INVGAMMA_Y_7_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_7_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_9
#define DENOISE3D2_INVGAMMA_Y_9_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_9_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_8
#define DENOISE3D2_INVGAMMA_Y_8_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_8_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_12_A
#define DENOISE3D2_INVGAMMA_Y_12_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_12_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_11
#define DENOISE3D2_INVGAMMA_Y_11_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_11_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_10
#define DENOISE3D2_INVGAMMA_Y_10_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_10_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_12_B
#define DENOISE3D2_INVGAMMA_Y_12_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_12_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_14
#define DENOISE3D2_INVGAMMA_Y_14_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_14_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_13
#define DENOISE3D2_INVGAMMA_Y_13_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_13_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_17_A
#define DENOISE3D2_INVGAMMA_Y_17_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_17_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_16
#define DENOISE3D2_INVGAMMA_Y_16_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_16_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_15
#define DENOISE3D2_INVGAMMA_Y_15_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_15_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_17_B
#define DENOISE3D2_INVGAMMA_Y_17_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_17_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_19
#define DENOISE3D2_INVGAMMA_Y_19_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_19_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_18
#define DENOISE3D2_INVGAMMA_Y_18_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_18_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_22_A
#define DENOISE3D2_INVGAMMA_Y_22_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_22_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_21
#define DENOISE3D2_INVGAMMA_Y_21_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_21_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_20
#define DENOISE3D2_INVGAMMA_Y_20_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_20_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_22_B
#define DENOISE3D2_INVGAMMA_Y_22_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_22_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_24
#define DENOISE3D2_INVGAMMA_Y_24_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_24_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_23
#define DENOISE3D2_INVGAMMA_Y_23_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_23_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_27_A
#define DENOISE3D2_INVGAMMA_Y_27_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_27_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_26
#define DENOISE3D2_INVGAMMA_Y_26_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_26_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_25
#define DENOISE3D2_INVGAMMA_Y_25_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_25_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_27_B
#define DENOISE3D2_INVGAMMA_Y_27_B_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_27_B_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_29
#define DENOISE3D2_INVGAMMA_Y_29_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_29_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_28
#define DENOISE3D2_INVGAMMA_Y_28_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_28_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_32_A
#define DENOISE3D2_INVGAMMA_Y_32_A_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_32_A_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_31
#define DENOISE3D2_INVGAMMA_Y_31_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_31_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_30
#define DENOISE3D2_INVGAMMA_Y_30_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_30_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_32_B
#define DENOISE3D2_INVGAMMA_Y_32_B_MASK (0x3f << 0 )
#define DENOISE3D2_INVGAMMA_Y_32_B_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_2_A_SHD
#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_2_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_1_SHD
#define DENOISE3D2_INVGAMMA_Y_1_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_1_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_0_SHD
#define DENOISE3D2_INVGAMMA_Y_0_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_0_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_2_B_SHD
#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_2_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_4_SHD
#define DENOISE3D2_INVGAMMA_Y_4_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_4_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_3_SHD
#define DENOISE3D2_INVGAMMA_Y_3_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_3_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_7_A_SHD
#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_7_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_6_SHD
#define DENOISE3D2_INVGAMMA_Y_6_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_6_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_5_SHD
#define DENOISE3D2_INVGAMMA_Y_5_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_5_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_7_B_SHD
#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_7_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_9_SHD
#define DENOISE3D2_INVGAMMA_Y_9_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_9_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_8_SHD
#define DENOISE3D2_INVGAMMA_Y_8_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_8_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_12_A_SHD
#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_12_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_11_SHD
#define DENOISE3D2_INVGAMMA_Y_11_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_11_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_10_SHD
#define DENOISE3D2_INVGAMMA_Y_10_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_10_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_12_B_SHD
#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_12_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_14_SHD
#define DENOISE3D2_INVGAMMA_Y_14_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_14_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_13_SHD
#define DENOISE3D2_INVGAMMA_Y_13_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_13_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_17_A_SHD
#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_17_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_16_SHD
#define DENOISE3D2_INVGAMMA_Y_16_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_16_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_15_SHD
#define DENOISE3D2_INVGAMMA_Y_15_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_15_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_17_B_SHD
#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_17_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_19_SHD
#define DENOISE3D2_INVGAMMA_Y_19_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_19_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_18_SHD
#define DENOISE3D2_INVGAMMA_Y_18_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_18_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_22_A_SHD
#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_22_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_21_SHD
#define DENOISE3D2_INVGAMMA_Y_21_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_21_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_20_SHD
#define DENOISE3D2_INVGAMMA_Y_20_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_20_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_22_B_SHD
#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_22_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_24_SHD
#define DENOISE3D2_INVGAMMA_Y_24_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_24_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_23_SHD
#define DENOISE3D2_INVGAMMA_Y_23_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_23_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_27_A_SHD
#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_27_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_26_SHD
#define DENOISE3D2_INVGAMMA_Y_26_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_26_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_25_SHD
#define DENOISE3D2_INVGAMMA_Y_25_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_25_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_27_B_SHD
#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_27_B_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_29_SHD
#define DENOISE3D2_INVGAMMA_Y_29_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_29_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_28_SHD
#define DENOISE3D2_INVGAMMA_Y_28_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_28_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_32_A_SHD
#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_MASK (0x3f << 24 )
#define DENOISE3D2_INVGAMMA_Y_32_A_SHD_SHIFT 24U

#define DENOISE3D2_INVGAMMA_Y_31_SHD
#define DENOISE3D2_INVGAMMA_Y_31_SHD_MASK (0xfff << 12 )
#define DENOISE3D2_INVGAMMA_Y_31_SHD_SHIFT 12U

#define DENOISE3D2_INVGAMMA_Y_30_SHD
#define DENOISE3D2_INVGAMMA_Y_30_SHD_MASK (0xfff << 0 )
#define DENOISE3D2_INVGAMMA_Y_30_SHD_SHIFT 0U

#define DENOISE3D2_INVGAMMA_Y_32_B_SHD
#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_MASK (0x3f << 0 )
#define DENOISE3D2_INVGAMMA_Y_32_B_SHD_SHIFT 0U

#define DENOISE3D2_NLM_STRENGTH_SLOPE
#define DENOISE3D2_NLM_STRENGTH_SLOPE_MASK (0xff << 0 )
#define DENOISE3D2_NLM_STRENGTH_SLOPE_SHIFT 0U

#define DENOISE3D2_TNR
#define DENOISE3D2_TNR_MASK (0x7ff << 0 )
#define DENOISE3D2_TNR_SHIFT 0U

#define PP_RD_YUV_CFG_UPDATE
#define PP_RD_YUV_CFG_UPDATE_MASK 0x1 << 7
#define PP_RD_YUV_CFG_UPDATE_SHIFT 7U

#define PP_RD_YUV_AUTO_UPDATE
#define PP_RD_YUV_AUTO_UPDATE_MASK 0x1 << 6
#define PP_RD_YUV_AUTO_UPDATE_SHIFT 6U

#define PP_INIT_OFFSET_EN
#define PP_INIT_OFFSET_EN_MASK 0x1 << 5
#define PP_INIT_OFFSET_EN_SHIFT 5U

#define PP_INIT_BASE_EN
#define PP_INIT_BASE_EN_MASK 0x1 << 4
#define PP_INIT_BASE_EN_SHIFT 4U

#define PP_MI_CFG_UPD
#define PP_MI_CFG_UPD_MASK 0x1 << 3
#define PP_MI_CFG_UPD_SHIFT 3U

#define PP_MI_SKIP
#define PP_MI_SKIP_MASK 0x1 << 2
#define PP_MI_SKIP_SHIFT 2U

#define PP_AUTO_UPDATE
#define PP_AUTO_UPDATE_MASK 0x1 << 1
#define PP_AUTO_UPDATE_SHIFT 1U

#define PP_PINGPONG_ENABLE
#define PP_PINGPONG_ENABLE_MASK 0x1 << 0
#define PP_PINGPONG_ENABLE_SHIFT 0U

#define PP_RD_RAW_ENABLE
#define PP_RD_RAW_ENABLE_MASK 0x1 << 31
#define PP_RD_RAW_ENABLE_SHIFT 31U

#define PP_RD_RAW_ALIGNED
#define PP_RD_RAW_ALIGNED_MASK (0x3 << 29 )
#define PP_RD_RAW_ALIGNED_SHIFT 29U

#define PP_RD_RAW_BIT
#define PP_RD_RAW_BIT_MASK (0x7 << 26 )
#define PP_RD_RAW_BIT_SHIFT 26U

#define PP_RD_YUV_NVY
#define PP_RD_YUV_NVY_MASK (0x3 << 24 )
#define PP_RD_YUV_NVY_SHIFT 24U

#define PP_RD_YUV_NV21
#define PP_RD_YUV_NV21_MASK 0x1 << 23
#define PP_RD_YUV_NV21_SHIFT 23U

#define PP_RD_YUV_ALIGNED
#define PP_RD_YUV_ALIGNED_MASK 0x1 << 22
#define PP_RD_YUV_ALIGNED_SHIFT 22U

#define PP_RD_YUV_STR
#define PP_RD_YUV_STR_MASK (0x3 << 20 )
#define PP_RD_YUV_STR_SHIFT 20U

#define PP_RD_YUV_FMT
#define PP_RD_YUV_FMT_MASK (0x3 << 18 )
#define PP_RD_YUV_FMT_SHIFT 18U

#define PP_RD_YUV_BIT
#define PP_RD_YUV_BIT_MASK 0x1 << 17
#define PP_RD_YUV_BIT_SHIFT 17U

#define PP_WR_RAW_SEL
#define PP_WR_RAW_SEL_MASK 0x1 << 16
#define PP_WR_RAW_SEL_SHIFT 16U

#define PP_WR_RAW_ALIGNED
#define PP_WR_RAW_ALIGNED_MASK (0x3 << 14 )
#define PP_WR_RAW_ALIGNED_SHIFT 14U

#define PP_WR_RAW_BIT
#define PP_WR_RAW_BIT_MASK (0x7 << 11 )
#define PP_WR_RAW_BIT_SHIFT 11U

#define PP_WR_YUV_WORD_ALIGNED_MSB_EN
#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_MASK 0x1 << 10
#define PP_WR_YUV_WORD_ALIGNED_MSB_EN_SHIFT 10U

#define PP_WR_YUV_WORD_ALIGNED
#define PP_WR_YUV_WORD_ALIGNED_MASK 0x1 << 9
#define PP_WR_YUV_WORD_ALIGNED_SHIFT 9U

#define PP_WR_YUV_NVY
#define PP_WR_YUV_NVY_MASK (0x3 << 7 )
#define PP_WR_YUV_NVY_SHIFT 7U

#define PP_WR_YUV_NV21
#define PP_WR_YUV_NV21_MASK 0x1 << 6
#define PP_WR_YUV_NV21_SHIFT 6U

#define PP_WR_YUV_ALIGNED
#define PP_WR_YUV_ALIGNED_MASK 0x1 << 5
#define PP_WR_YUV_ALIGNED_SHIFT 5U

#define PP_WR_YUV_STR
#define PP_WR_YUV_STR_MASK (0x3 << 3 )
#define PP_WR_YUV_STR_SHIFT 3U

#define PP_WR_YUV_FMT
#define PP_WR_YUV_FMT_MASK (0x3 << 1 )
#define PP_WR_YUV_FMT_SHIFT 1U

#define PP_WR_YUV_BIT
#define PP_WR_YUV_BIT_MASK 0x1 << 0
#define PP_WR_YUV_BIT_SHIFT 0U

#define PP_RD_SWAP_V
#define PP_RD_SWAP_V_MASK 0xf << 24
#define PP_RD_SWAP_V_SHIFT 24U

#define PP_RD_SWAP_U
#define PP_RD_SWAP_U_MASK 0xf << 20
#define PP_RD_SWAP_U_SHIFT 20U

#define PP_RD_SWAP_Y
#define PP_RD_SWAP_Y_MASK 0xf << 16
#define PP_RD_SWAP_Y_SHIFT 16U

#define PP_WR_SWAP_V
#define PP_WR_SWAP_V_MASK 0xf << 8
#define PP_WR_SWAP_V_SHIFT 8U

#define PP_WR_SWAP_U
#define PP_WR_SWAP_U_MASK 0xf << 4
#define PP_WR_SWAP_U_SHIFT 4U

#define PP_WR_SWAP_Y
#define PP_WR_SWAP_Y_MASK 0xf << 0
#define PP_WR_SWAP_Y_SHIFT 0U

#define PP_Y_BASE_AD_INIT
#define PP_Y_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define PP_Y_BASE_AD_INIT_SHIFT 4U

#define PP_Y_SIZE_INIT
#define PP_Y_SIZE_INIT_MASK (0x1ffffff << 4 )
#define PP_Y_SIZE_INIT_SHIFT 4U

#define PP_Y_OFFS_CNT_INIT
#define PP_Y_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
#define PP_Y_OFFS_CNT_INIT_SHIFT 4U

#define PP_Y_LLENGH
#define PP_Y_LLENGH_MASK (0xffffffff << 0 )
#define PP_Y_LLENGH_SHIFT 0U

#define PP_Y_PIC_WIDTH
#define PP_Y_PIC_WIDTH_MASK (0xffffffff << 0 )
#define PP_Y_PIC_WIDTH_SHIFT 0U

#define PP_Y_PIC_HEIGHT
#define PP_Y_PIC_HEIGHT_MASK (0xffffffff << 0 )
#define PP_Y_PIC_HEIGHT_SHIFT 0U

#define PP_Y_PIC_SIZE
#define PP_Y_PIC_SIZE_MASK (0xffffffff << 0 )
#define PP_Y_PIC_SIZE_SHIFT 0U

#define PP_CB_BASE_AD_INIT
#define PP_CB_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define PP_CB_BASE_AD_INIT_SHIFT 4U

#define PP_CB_SIZE_INIT
#define PP_CB_SIZE_INIT_MASK (0xffffff << 4 )
#define PP_CB_SIZE_INIT_SHIFT 4U

#define PP_CB_OFFS_CNT_INIT
#define PP_CB_OFFS_CNT_INIT_MASK (0xffffff << 4 )
#define PP_CB_OFFS_CNT_INIT_SHIFT 4U

#define PP_CR_BASE_AD_INIT
#define PP_CR_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define PP_CR_BASE_AD_INIT_SHIFT 4U

#define PP_CR_SIZE_INIT
#define PP_CR_SIZE_INIT_MASK (0xffffff << 4 )
#define PP_CR_SIZE_INIT_SHIFT 4U

#define PP_CR_OFFS_CNT_INIT
#define PP_CR_OFFS_CNT_INIT_MASK (0xffffff << 4 )
#define PP_CR_OFFS_CNT_INIT_SHIFT 4U

#define PP_Y_BASE_AD_INIT2
#define PP_Y_BASE_AD_INIT2_MASK (0xfffffff << 4 )
#define PP_Y_BASE_AD_INIT2_SHIFT 4U

#define PP_CB_BASE_AD_INIT2
#define PP_CB_BASE_AD_INIT2_MASK (0xfffffff << 4 )
#define PP_CB_BASE_AD_INIT2_SHIFT 4U

#define PP_CR_BASE_AD_INIT2
#define PP_CR_BASE_AD_INIT2_MASK (0xfffffff << 4 )
#define PP_CR_BASE_AD_INIT2_SHIFT 4U

#define PP_Y_OFFS_CNT_START
#define PP_Y_OFFS_CNT_START_MASK (0x1ffffff << 4 )
#define PP_Y_OFFS_CNT_START_SHIFT 4U

#define PP_CB_OFFS_CNT_START
#define PP_CB_OFFS_CNT_START_MASK (0xffffff << 4 )
#define PP_CB_OFFS_CNT_START_SHIFT 4U

#define PP_CR_OFFS_CNT_START
#define PP_CR_OFFS_CNT_START_MASK (0xffffff << 4 )
#define PP_CR_OFFS_CNT_START_SHIFT 4U

#define PP_Y_BASE_AD
#define PP_Y_BASE_AD_MASK (0xfffffff << 4 )
#define PP_Y_BASE_AD_SHIFT 4U

#define PP_Y_SIZE
#define PP_Y_SIZE_MASK (0x1ffffff << 4 )
#define PP_Y_SIZE_SHIFT 4U

#define PP_Y_OFFS_CNT
#define PP_Y_OFFS_CNT_MASK (0x1ffffff << 4 )
#define PP_Y_OFFS_CNT_SHIFT 4U

#define PP_CB_BASE_AD
#define PP_CB_BASE_AD_MASK (0xfffffff << 4 )
#define PP_CB_BASE_AD_SHIFT 4U

#define PP_CB_SIZE
#define PP_CB_SIZE_MASK (0xffffff << 4 )
#define PP_CB_SIZE_SHIFT 4U

#define PP_CB_OFFS_CNT
#define PP_CB_OFFS_CNT_MASK (0xffffff << 4 )
#define PP_CB_OFFS_CNT_SHIFT 4U

#define PP_CR_BASE_AD
#define PP_CR_BASE_AD_MASK (0xfffffff << 4 )
#define PP_CR_BASE_AD_SHIFT 4U

#define PP_CR_SIZE
#define PP_CR_SIZE_MASK (0xffffff << 4 )
#define PP_CR_SIZE_SHIFT 4U

#define PP_CR_OFFS_CNT
#define PP_CR_OFFS_CNT_MASK (0xffffff << 4 )
#define PP_CR_OFFS_CNT_SHIFT 4U

#define PP_DMA_Y_PIC_WIDTH
#define PP_DMA_Y_PIC_WIDTH_MASK (0x7fff << 0 )
#define PP_DMA_Y_PIC_WIDTH_SHIFT 0U

#define PP_DMA_Y_PIC_LLENGTH
#define PP_DMA_Y_PIC_LLENGTH_MASK (0xffffffff << 0 )
#define PP_DMA_Y_PIC_LLENGTH_SHIFT 0U

#define PP_DMA_Y_PIC_SIZE
#define PP_DMA_Y_PIC_SIZE_MASK (0xfffffff << 0 )
#define PP_DMA_Y_PIC_SIZE_SHIFT 0U

#define PP_DMA_CB_PIC_START_AD
#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 )
#define PP_DMA_CB_PIC_START_AD_SHIFT 4U

#define PP_DMA_CR_PIC_START_AD
#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 )
#define PP_DMA_CR_PIC_START_AD_SHIFT 4U

#define PP_DMA_Y_PIC_START_AD
#define PP_DMA_Y_PIC_START_AD_MASK (0xfffffff << 4 )
#define PP_DMA_Y_PIC_START_AD_SHIFT 4U

#define PP_DMA_CB_PIC_START_AD
#define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 )
#define PP_DMA_CB_PIC_START_AD_SHIFT 4U

#define PP_DMA_CR_PIC_START_AD
#define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 )
#define PP_DMA_CR_PIC_START_AD_SHIFT 4U

#define PP_DMA_Y_PIC_LVAL
#define PP_DMA_Y_PIC_LVAL_MASK (0xffff << 0 )
#define PP_DMA_Y_PIC_LVAL_SHIFT 0U



#define HDR_DMA_START_CONTINUOUS
#define HDR_DMA_START_CONTINUOUS_MASK 0x1 << 8
#define HDR_DMA_START_CONTINUOUS_SHIFT 8U

#define HDR_DMA_START
#define HDR_DMA_START_MASK 0x1 << 7
#define HDR_DMA_START_SHIFT 7U

#define HDR_WR_ENABLE
#define HDR_WR_ENABLE_MASK 0x1 << 6
#define HDR_WR_ENABLE_SHIFT 6U

#define HDR_RD_RAW_CFG_UPDATE
#define HDR_RD_RAW_CFG_UPDATE_MASK 0x1 << 5
#define HDR_RD_RAW_CFG_UPDATE_SHIFT 5U

#define HDR_RD_RAW_AUTO_UPDATE
#define HDR_RD_RAW_AUTO_UPDATE_MASK 0x1 << 4
#define HDR_RD_RAW_AUTO_UPDATE_SHIFT 4U

#define HDR_INIT_OFFSET_EN
#define HDR_INIT_OFFSET_EN_MASK 0x1 << 3
#define HDR_INIT_OFFSET_EN_SHIFT 3U

#define HDR_INIT_BASE_EN
#define HDR_INIT_BASE_EN_MASK 0x1 << 2
#define HDR_INIT_BASE_EN_SHIFT 2U

#define HDR_MI_CFG_UPD
#define HDR_MI_CFG_UPD_MASK 0x1 << 1
#define HDR_MI_CFG_UPD_SHIFT 1U

#define HDR_AUTO_UPDATE
#define HDR_AUTO_UPDATE_MASK 0x1 << 0
#define HDR_AUTO_UPDATE_SHIFT 0U

#define HDR_RD_RAW_ALIGNED
#define HDR_RD_RAW_ALIGNED_MASK (0x3 << 24 )
#define HDR_RD_RAW_ALIGNED_SHIFT 24U

#define HDR_RD_VS_BIT
#define HDR_RD_VS_BIT_MASK (0x3 << 22 )
#define HDR_RD_VS_BIT_SHIFT 22U

#define HDR_RD_S_BIT
#define HDR_RD_S_BIT_MASK (0x3 << 20 )
#define HDR_RD_S_BIT_SHIFT 20U

#define HDR_RD_L_BIT
#define HDR_RD_L_BIT_MASK (0x3 << 18 )
#define HDR_RD_L_BIT_SHIFT 18U

#define HDR_RD_STR
#define HDR_RD_STR_MASK (0x3 << 16 )
#define HDR_RD_STR_SHIFT 16U

#define HDR_WR_RAW_ALIGNED
#define HDR_WR_RAW_ALIGNED_MASK (0x3 << 8 )
#define HDR_WR_RAW_ALIGNED_SHIFT 8U

#define HDR_WR_VS_BIT
#define HDR_WR_VS_BIT_MASK (0x3 << 6 )
#define HDR_WR_VS_BIT_SHIFT 6U

#define HDR_WR_S_BIT
#define HDR_WR_S_BIT_MASK (0x3 << 4 )
#define HDR_WR_S_BIT_SHIFT 4U

#define HDR_WR_L_BIT
#define HDR_WR_L_BIT_MASK (0x3 << 2 )
#define HDR_WR_L_BIT_SHIFT 2U

#define HDR_WR_STR
#define HDR_WR_STR_MASK (0x3 << 0 )
#define HDR_WR_STR_SHIFT 0U

#define HDR_DMA_START_BY_LINES
#define HDR_DMA_START_BY_LINES_MASK (0xffff << 0 )
#define HDR_DMA_START_BY_LINES_SHIFT 0U

#define HDR_RD_SWAP_RAW
#define HDR_RD_SWAP_RAW_MASK (0xf << 16 )
#define HDR_RD_SWAP_RAW_SHIFT 16U

#define HDR_WR_SWAP_RAW
#define HDR_WR_SWAP_RAW_MASK (0xf << 0 )
#define HDR_WR_SWAP_RAW_SHIFT 0U

#define HDR_BUS_SW_EN
#define HDR_BUS_SW_EN_MASK 0x1 << 23
#define HDR_BUS_SW_EN_SHIFT 23U

#define HDR_RD_BURST_LEN
#define HDR_RD_BURST_LEN_MASK (0x3 << 21 )
#define HDR_RD_BURST_LEN_SHIFT 21U

#define HDR_WR_BURST_LEN
#define HDR_WR_BURST_LEN_MASK (0x3 << 19 )
#define HDR_WR_BURST_LEN_SHIFT 19U

#define HDR_RD_ID_EN
#define HDR_RD_ID_EN_MASK 0x1 << 18
#define HDR_RD_ID_EN_SHIFT 18U

#define HDR_RD_ID_CFG
#define HDR_RD_ID_CFG_MASK (0xff << 10 )
#define HDR_RD_ID_CFG_SHIFT 10U

#define HDR_WR_ID_EN
#define HDR_WR_ID_EN_MASK 0x1 << 8
#define HDR_WR_ID_EN_SHIFT 8U

#define HDR_WR_ID_CFG
#define HDR_WR_ID_CFG_MASK (0xff << 0 )
#define HDR_WR_ID_CFG_SHIFT 0U

#define HDR_BUS_TIMEO_EN
#define HDR_BUS_TIMEO_EN_MASK 0x1 << 31
#define HDR_BUS_TIMEO_EN_SHIFT 31U

#define HDR_BUS_TIMEO
#define HDR_BUS_TIMEO_MASK (0x7fffffff << 0 )
#define HDR_BUS_TIMEO_SHIFT 0U

#define HDR_L_PIC_WIDTH
#define HDR_L_PIC_WIDTH_MASK (0xffffffff << 0 )
#define HDR_L_PIC_WIDTH_SHIFT 0U

#define HDR_L_PIC_HEIGHT
#define HDR_L_PIC_HEIGHT_MASK (0xffffffff << 0 )
#define HDR_L_PIC_HEIGHT_SHIFT 0U

#define HDR_L_BASE_AD_INIT
#define HDR_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_L_BASE_AD_INIT_SHIFT 4U

#define HDR_L_SIZE_INIT
#define HDR_L_SIZE_INIT_MASK (0x1ffffff << 4 )
#define HDR_L_SIZE_INIT_SHIFT 4U

#define HDR_L_OFFS_CNT_INIT
#define HDR_L_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
#define HDR_L_OFFS_CNT_INIT_SHIFT 4U

#define HDR_L_LLENGTH
#define HDR_L_LLENGTH_MASK (0xffffffff << 0 )
#define HDR_L_LLENGTH_SHIFT 0U

#define HDR_L_PIC_LVAL
#define HDR_L_PIC_LVAL_MASK (0xffff << 0 )
#define HDR_L_PIC_LVAL_SHIFT 0U

#define HDR_L_IRQ_OFFS_INIT
#define HDR_L_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
#define HDR_L_IRQ_OFFS_INIT_SHIFT 0U

#define HDR_L_OFFS_CNT_START
#define HDR_L_OFFS_CNT_START_MASK (0x1ffffff << 4 )
#define HDR_L_OFFS_CNT_START_SHIFT 4U

#define HDR_L_BASE_AD_SHD
#define HDR_L_BASE_AD_SHD_MASK (0xfffffff << 4 )
#define HDR_L_BASE_AD_SHD_SHIFT 4U

#define HDR_L_SIZE_SHD
#define HDR_L_SIZE_SHD_MASK (0x1ffffff << 4 )
#define HDR_L_SIZE_SHD_SHIFT 4U

#define HDR_L_OFFS_CNT
#define HDR_L_OFFS_CNT_MASK (0x1ffffff << 4 )
#define HDR_L_OFFS_CNT_SHIFT 4U

#define HDR_L_IRQ_OFFS_SHD
#define HDR_L_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
#define HDR_L_IRQ_OFFS_SHD_SHIFT 0U

#define HDR_S_BASE_AD_INIT
#define HDR_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_S_BASE_AD_INIT_SHIFT 4U

#define HDR_S_SIZE_INIT
#define HDR_S_SIZE_INIT_MASK (0x1ffffff << 4 )
#define HDR_S_SIZE_INIT_SHIFT 4U

#define HDR_S_OFFS_CNT_INIT
#define HDR_S_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
#define HDR_S_OFFS_CNT_INIT_SHIFT 4U

#define HDR_S_LLENGTH
#define HDR_S_LLENGTH_MASK (0xffffffff << 0 )
#define HDR_S_LLENGTH_SHIFT 0U

#define HDR_S_PIC_LVAL
#define HDR_S_PIC_LVAL_MASK (0xffff << 0 )
#define HDR_S_PIC_LVAL_SHIFT 0U

#define HDR_S_IRQ_OFFS_INIT
#define HDR_S_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
#define HDR_S_IRQ_OFFS_INIT_SHIFT 0U

#define HDR_S_OFFS_CNT_START
#define HDR_S_OFFS_CNT_START_MASK (0x1ffffff << 4 )
#define HDR_S_OFFS_CNT_START_SHIFT 4U

#define HDR_S_BASE_AD_SHD
#define HDR_S_BASE_AD_SHD_MASK (0xfffffff << 4 )
#define HDR_S_BASE_AD_SHD_SHIFT 4U

#define HDR_S_SIZE_SHD
#define HDR_S_SIZE_SHD_MASK (0x1ffffff << 4 )
#define HDR_S_SIZE_SHD_SHIFT 4U

#define HDR_S_OFFS_CNT
#define HDR_S_OFFS_CNT_MASK (0x1ffffff << 4 )
#define HDR_S_OFFS_CNT_SHIFT 4U

#define HDR_S_IRQ_OFFS_SHD
#define HDR_S_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
#define HDR_S_IRQ_OFFS_SHD_SHIFT 0U

#define HDR_VS_BASE_AD_INIT
#define HDR_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_VS_BASE_AD_INIT_SHIFT 4U

#define HDR_VS_SIZE_INIT
#define HDR_VS_SIZE_INIT_MASK (0x1ffffff << 4 )
#define HDR_VS_SIZE_INIT_SHIFT 4U

#define HDR_VS_OFFS_CNT_INIT
#define HDR_VS_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
#define HDR_VS_OFFS_CNT_INIT_SHIFT 4U

#define HDR_VS_LLENGTH
#define HDR_VS_LLENGTH_MASK (0xffffffff << 0 )
#define HDR_VS_LLENGTH_SHIFT 0U

#define HDR_VS_PIC_LVAL
#define HDR_VS_PIC_LVAL_MASK (0xffff << 0 )
#define HDR_VS_PIC_LVAL_SHIFT 0U

#define HDR_VS_IRQ_OFFS_INIT
#define HDR_VS_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
#define HDR_VS_IRQ_OFFS_INIT_SHIFT 0U

#define HDR_VS_OFFS_CNT_START
#define HDR_VS_OFFS_CNT_START_MASK (0x1ffffff << 4 )
#define HDR_VS_OFFS_CNT_START_SHIFT 4U

#define HDR_VS_BASE_AD_SHD
#define HDR_VS_BASE_AD_SHD_MASK (0xfffffff << 4 )
#define HDR_VS_BASE_AD_SHD_SHIFT 4U

#define HDR_VS_SIZE_SHD
#define HDR_VS_SIZE_SHD_MASK (0x1ffffff << 4 )
#define HDR_VS_SIZE_SHD_SHIFT 4U

#define HDR_VS_OFFS_CNT
#define HDR_VS_OFFS_CNT_MASK (0x1ffffff << 4 )
#define HDR_VS_OFFS_CNT_SHIFT 4U

#define HDR_VS_IRQ_OFFS_SHD
#define HDR_VS_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
#define HDR_VS_IRQ_OFFS_SHD_SHIFT 0U

#define HDR_DMA_PIC_WIDTH
#define HDR_DMA_PIC_WIDTH_MASK (0x7fff << 0 )
#define HDR_DMA_PIC_WIDTH_SHIFT 0U

#define HDR_DMA_PIC_HEIGHT
#define HDR_DMA_PIC_HEIGHT_MASK (0x7fff << 0 )
#define HDR_DMA_PIC_HEIGHT_SHIFT 0U

#define HDR_DMA_L_BASE_AD_INIT
#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_L_SIZE_INIT
#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_L_SIZE_INIT_SHIFT 4U

#define HDR_DMA_L_PIC_LLENGTH
#define HDR_DMA_L_PIC_LLENGTH_MASK (0xfffffff << 4 )
#define HDR_DMA_L_PIC_LLENGTH_SHIFT 4U

#define HDR_DMA_L_WIDTH_BYTES
#define HDR_DMA_L_WIDTH_BYTES_MASK (0xffff << 0 )
#define HDR_DMA_L_WIDTH_BYTES_SHIFT 0U

#define HDR_DMA_L_BASE_AD_INIT
#define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_L_SIZE_INIT
#define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_L_SIZE_INIT_SHIFT 4U

#define HDR_DMA_S_BASE_AD_INIT
#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_S_SIZE_INIT
#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_S_SIZE_INIT_SHIFT 4U

#define HDR_DMA_S_PIC_LLENGTH
#define HDR_DMA_S_PIC_LLENGTH_MASK (0xfffffff << 4 )
#define HDR_DMA_S_PIC_LLENGTH_SHIFT 4U

#define HDR_DMA_S_WIDTH_BYTES
#define HDR_DMA_S_WIDTH_BYTES_MASK (0xffff << 0 )
#define HDR_DMA_S_WIDTH_BYTES_SHIFT 0U

#define HDR_DMA_S_BASE_AD_INIT
#define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_S_SIZE_INIT
#define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_S_SIZE_INIT_SHIFT 4U

#define HDR_DMA_VS_BASE_AD_INIT
#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_VS_SIZE_INIT
#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U

#define HDR_DMA_VS_PIC_LLENGTH
#define HDR_DMA_VS_PIC_LLENGTH_MASK (0xfffffff << 4 )
#define HDR_DMA_VS_PIC_LLENGTH_SHIFT 4U

#define HDR_DMA_VS_WIDTH_BYTES
#define HDR_DMA_VS_WIDTH_BYTES_MASK (0xffff << 0 )
#define HDR_DMA_VS_WIDTH_BYTES_SHIFT 0U

#define HDR_DMA_VS_BASE_AD_INIT
#define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U

#define HDR_DMA_VS_SIZE_INIT
#define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 )
#define HDR_DMA_VS_SIZE_INIT_SHIFT 4U

#define HDR_RT_VSYNC_POL
#define HDR_RT_VSYNC_POL_MASK (0x1 << 8)
#define HDR_RT_VSYNC_POL_SHIFT 8U

#define HDR_RT_HSYNC_POL
#define HDR_RT_HSYNC_POL_MASK (0x1 << 7)
#define HDR_RT_HSYNC_POL_SHIFT 7U

#define HDR_RETIMING_ENABLE
#define HDR_RETIMING_ENABLE_MASK 0x1 << 6
#define HDR_RETIMING_ENABLE_SHIFT 6U

#define LONG_USE_DDR_ONLY_EN
#define LONG_USE_DDR_ONLY_EN_MASK 0x1 << 5
#define LONG_USE_DDR_ONLY_EN_SHIFT 5U

#define SHORT_USE_DDR_ONLY_EN
#define SHORT_USE_DDR_ONLY_EN_MASK 0x1 << 4
#define SHORT_USE_DDR_ONLY_EN_SHIFT 4U

#define DUMP_MODE_EN
#define DUMP_MODE_EN_MASK 0x1 << 3
#define DUMP_MODE_EN_SHIFT 3U

#define L_VS_COMBINING_ENABLE
#define L_VS_COMBINING_ENABLE_MASK 0x1 << 2
#define L_VS_COMBINING_ENABLE_SHIFT 2U

#define EXPOSURE_COUNT
#define EXPOSURE_COUNT_MASK (0x3 << 0 )
#define EXPOSURE_COUNT_SHIFT 0U

#define HDR_INTERVAL1
#define HDR_INTERVAL1_MASK (0xffff << 16 )
#define HDR_INTERVAL1_SHIFT 16U

#define HDR_INTERVAL0
#define HDR_INTERVAL0_MASK (0xffff << 0 )
#define HDR_INTERVAL0_SHIFT 0U

#define PART_TWO_ENABLE
#define PART_TWO_ENABLE_MASK 0x1 << 23
#define PART_TWO_ENABLE_SHIFT 23U

#define PART_ONE_ENABLE
#define PART_ONE_ENABLE_MASK 0x1 << 22
#define PART_ONE_ENABLE_SHIFT 22U

#define SOFT_RST_PRE_FILT
#define SOFT_RST_PRE_FILT_MASK 0x1 << 21
#define SOFT_RST_PRE_FILT_SHIFT 21U

#define DEMOSAIC_THRESHOLD
#define DEMOSAIC_THRESHOLD_MASK (0xff << 13 )
#define DEMOSAIC_THRESHOLD_SHIFT 13U

#define STAGE1_SELECT
#define STAGE1_SELECT_MASK (0xf << 9 )
#define STAGE1_SELECT_SHIFT 9U

#define OUT_RGB_BAYER_PATTERN
#define OUT_RGB_BAYER_PATTERN_MASK (0x3 << 7 )
#define OUT_RGB_BAYER_PATTERN_SHIFT 7U

#define RGBIR_BAYER_PATTERN
#define RGBIR_BAYER_PATTERN_MASK (0xf << 3 )
#define RGBIR_BAYER_PATTERN_SHIFT 3U

#define GREEN_FILT_ENABLE
#define GREEN_FILT_ENABLE_MASK 0x1 << 2
#define GREEN_FILT_ENABLE_SHIFT 2U

#define GREEN_FILT_MODE
#define GREEN_FILT_MODE_MASK 0x1 << 1
#define GREEN_FILT_MODE_SHIFT 1U

#define ISP_PRE_FILT_ENABLE
#define ISP_PRE_FILT_ENABLE_MASK 0x1 << 0
#define ISP_PRE_FILT_ENABLE_SHIFT 0U

#define ISP_PRE_FILT_BLS_A
#define ISP_PRE_FILT_BLS_A_MASK (0xffff << 0 )
#define ISP_PRE_FILT_BLS_A_SHIFT 0U

#define ISP_PRE_FILT_BLS_B
#define ISP_PRE_FILT_BLS_B_MASK (0xffff << 0 )
#define ISP_PRE_FILT_BLS_B_SHIFT 0U

#define ISP_PRE_FILT_BLS_C
#define ISP_PRE_FILT_BLS_C_MASK (0xffff << 0 )
#define ISP_PRE_FILT_BLS_C_SHIFT 0U

#define ISP_PRE_FILT_BLS_D
#define ISP_PRE_FILT_BLS_D_MASK (0xffff << 0 )
#define ISP_PRE_FILT_BLS_D_SHIFT 0U

#define ISP_PRE_FILT_GAIN_R
#define ISP_PRE_FILT_GAIN_R_MASK (0x3ff << 0 )
#define ISP_PRE_FILT_GAIN_R_SHIFT 0U

#define ISP_PRE_FILT_GAIN_G
#define ISP_PRE_FILT_GAIN_G_MASK (0x3ff << 0 )
#define ISP_PRE_FILT_GAIN_G_SHIFT 0U

#define ISP_PRE_FILT_GAIN_B
#define ISP_PRE_FILT_GAIN_B_MASK (0x3ff << 0 )
#define ISP_PRE_FILT_GAIN_B_SHIFT 0U

#define ISP_PRE_FILT_DPC_TH_MED_R
#define ISP_PRE_FILT_DPC_TH_MED_R_MASK (0xffff << 16 )
#define ISP_PRE_FILT_DPC_TH_MED_R_SHIFT 16U

#define ISP_PRE_FILT_DPC_TH_AVG_R
#define ISP_PRE_FILT_DPC_TH_AVG_R_MASK (0xffff << 0 )
#define ISP_PRE_FILT_DPC_TH_AVG_R_SHIFT 0U

#define ISP_PRE_FILT_DPC_TH_MED_G
#define ISP_PRE_FILT_DPC_TH_MED_G_MASK (0xffff << 16 )
#define ISP_PRE_FILT_DPC_TH_MED_G_SHIFT 16U

#define ISP_PRE_FILT_DPC_TH_AVG_G
#define ISP_PRE_FILT_DPC_TH_AVG_G_MASK (0xffff << 0 )
#define ISP_PRE_FILT_DPC_TH_AVG_G_SHIFT 0U

#define ISP_PRE_FILT_DPC_TH_MED_B
#define ISP_PRE_FILT_DPC_TH_MED_B_MASK (0xffff << 16 )
#define ISP_PRE_FILT_DPC_TH_MED_B_SHIFT 16U

#define ISP_PRE_FILT_DPC_TH_AVG_B
#define ISP_PRE_FILT_DPC_TH_AVG_B_MASK (0xffff << 0 )
#define ISP_PRE_FILT_DPC_TH_AVG_B_SHIFT 0U

#define ISP_PRE_FILT_DPC_TH_MED_IR
#define ISP_PRE_FILT_DPC_TH_MED_IR_MASK (0xffff << 16 )
#define ISP_PRE_FILT_DPC_TH_MED_IR_SHIFT 16U

#define ISP_PRE_FILT_DPC_TH_AVG_IR
#define ISP_PRE_FILT_DPC_TH_AVG_IR_MASK (0xffff << 0 )
#define ISP_PRE_FILT_DPC_TH_AVG_IR_SHIFT 0U

#define ISP_PRE_FILT_CC_00
#define ISP_PRE_FILT_CC_00_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_00_SHIFT 16U

#define ISP_PRE_FILT_CC_01
#define ISP_PRE_FILT_CC_01_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_01_SHIFT 0U

#define ISP_PRE_FILT_CC_02
#define ISP_PRE_FILT_CC_02_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_02_SHIFT 16U

#define ISP_PRE_FILT_CC_03
#define ISP_PRE_FILT_CC_03_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_03_SHIFT 0U

#define ISP_PRE_FILT_CC_10
#define ISP_PRE_FILT_CC_10_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_10_SHIFT 16U

#define ISP_PRE_FILT_CC_11
#define ISP_PRE_FILT_CC_11_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_11_SHIFT 0U

#define ISP_PRE_FILT_CC_12
#define ISP_PRE_FILT_CC_12_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_12_SHIFT 16U

#define ISP_PRE_FILT_CC_13
#define ISP_PRE_FILT_CC_13_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_13_SHIFT 0U

#define ISP_PRE_FILT_CC_20
#define ISP_PRE_FILT_CC_20_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_20_SHIFT 16U

#define ISP_PRE_FILT_CC_21
#define ISP_PRE_FILT_CC_21_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_21_SHIFT 0U

#define ISP_PRE_FILT_CC_22
#define ISP_PRE_FILT_CC_22_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_22_SHIFT 16U

#define ISP_PRE_FILT_CC_23
#define ISP_PRE_FILT_CC_23_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_23_SHIFT 0U

#define ISP_PRE_FILT_CC_00_SHD
#define ISP_PRE_FILT_CC_00_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_00_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_01_SHD
#define ISP_PRE_FILT_CC_01_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_01_SHD_SHIFT 0U

#define ISP_PRE_FILT_CC_02_SHD
#define ISP_PRE_FILT_CC_02_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_02_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_03_SHD
#define ISP_PRE_FILT_CC_03_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_03_SHD_SHIFT 0U

#define ISP_PRE_FILT_CC_10_SHD
#define ISP_PRE_FILT_CC_10_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_10_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_11_SHD
#define ISP_PRE_FILT_CC_11_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_11_SHD_SHIFT 0U

#define ISP_PRE_FILT_CC_12_SHD
#define ISP_PRE_FILT_CC_12_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_12_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_13_SHD
#define ISP_PRE_FILT_CC_13_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_13_SHD_SHIFT 0U

#define ISP_PRE_FILT_CC_20_SHD
#define ISP_PRE_FILT_CC_20_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_20_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_21_SHD
#define ISP_PRE_FILT_CC_21_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_21_SHD_SHIFT 0U

#define ISP_PRE_FILT_CC_22_SHD
#define ISP_PRE_FILT_CC_22_SHD_MASK (0x7ff << 16 )
#define ISP_PRE_FILT_CC_22_SHD_SHIFT 16U

#define ISP_PRE_FILT_CC_23_SHD
#define ISP_PRE_FILT_CC_23_SHD_MASK (0x7ff << 0 )
#define ISP_PRE_FILT_CC_23_SHD_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PX1
#define ISP_PRE_FILT_IR_DES_PX1_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PX1_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY2
#define ISP_PRE_FILT_IR_DES_PY2_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY2_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY1
#define ISP_PRE_FILT_IR_DES_PY1_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY1_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY4
#define ISP_PRE_FILT_IR_DES_PY4_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY4_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY3
#define ISP_PRE_FILT_IR_DES_PY3_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY3_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY6
#define ISP_PRE_FILT_IR_DES_PY6_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY6_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY5
#define ISP_PRE_FILT_IR_DES_PY5_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY5_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY8
#define ISP_PRE_FILT_IR_DES_PY8_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY8_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY7
#define ISP_PRE_FILT_IR_DES_PY7_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY7_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY10
#define ISP_PRE_FILT_IR_DES_PY10_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY10_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY9
#define ISP_PRE_FILT_IR_DES_PY9_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY9_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY12
#define ISP_PRE_FILT_IR_DES_PY12_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY12_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY11
#define ISP_PRE_FILT_IR_DES_PY11_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY11_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY14
#define ISP_PRE_FILT_IR_DES_PY14_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY14_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY13
#define ISP_PRE_FILT_IR_DES_PY13_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY13_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PY16
#define ISP_PRE_FILT_IR_DES_PY16_MASK (0xffff << 16 )
#define ISP_PRE_FILT_IR_DES_PY16_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PY15
#define ISP_PRE_FILT_IR_DES_PY15_MASK (0xffff << 0 )
#define ISP_PRE_FILT_IR_DES_PY15_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PD4
#define ISP_PRE_FILT_IR_DES_PD4_MASK (0xff << 24 )
#define ISP_PRE_FILT_IR_DES_PD4_SHIFT 24U

#define ISP_PRE_FILT_IR_DES_PD3
#define ISP_PRE_FILT_IR_DES_PD3_MASK (0xff << 16 )
#define ISP_PRE_FILT_IR_DES_PD3_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PD2
#define ISP_PRE_FILT_IR_DES_PD2_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DES_PD2_SHIFT 8U

#define ISP_PRE_FILT_IR_DES_PD1
#define ISP_PRE_FILT_IR_DES_PD1_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DES_PD1_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PD8
#define ISP_PRE_FILT_IR_DES_PD8_MASK (0xff << 24 )
#define ISP_PRE_FILT_IR_DES_PD8_SHIFT 24U

#define ISP_PRE_FILT_IR_DES_PD7
#define ISP_PRE_FILT_IR_DES_PD7_MASK (0xff << 16 )
#define ISP_PRE_FILT_IR_DES_PD7_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PD6
#define ISP_PRE_FILT_IR_DES_PD6_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DES_PD6_SHIFT 8U

#define ISP_PRE_FILT_IR_DES_PD5
#define ISP_PRE_FILT_IR_DES_PD5_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DES_PD5_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PD12
#define ISP_PRE_FILT_IR_DES_PD12_MASK (0xff << 24 )
#define ISP_PRE_FILT_IR_DES_PD12_SHIFT 24U

#define ISP_PRE_FILT_IR_DES_PD11
#define ISP_PRE_FILT_IR_DES_PD11_MASK (0xff << 16 )
#define ISP_PRE_FILT_IR_DES_PD11_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PD10
#define ISP_PRE_FILT_IR_DES_PD10_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DES_PD10_SHIFT 8U

#define ISP_PRE_FILT_IR_DES_PD9
#define ISP_PRE_FILT_IR_DES_PD9_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DES_PD9_SHIFT 0U

#define ISP_PRE_FILT_IR_DES_PD15
#define ISP_PRE_FILT_IR_DES_PD15_MASK (0xff << 16 )
#define ISP_PRE_FILT_IR_DES_PD15_SHIFT 16U

#define ISP_PRE_FILT_IR_DES_PD14
#define ISP_PRE_FILT_IR_DES_PD14_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DES_PD14_SHIFT 8U

#define ISP_PRE_FILT_IR_DES_PD13
#define ISP_PRE_FILT_IR_DES_PD13_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DES_PD13_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PX1
#define ISP_PRE_FILT_L_DES_PX1_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PX1_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY2
#define ISP_PRE_FILT_L_DES_PY2_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY2_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY1
#define ISP_PRE_FILT_L_DES_PY1_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY1_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY4
#define ISP_PRE_FILT_L_DES_PY4_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY4_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY3
#define ISP_PRE_FILT_L_DES_PY3_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY3_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY6
#define ISP_PRE_FILT_L_DES_PY6_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY6_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY5
#define ISP_PRE_FILT_L_DES_PY5_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY5_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY8
#define ISP_PRE_FILT_L_DES_PY8_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY8_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY7
#define ISP_PRE_FILT_L_DES_PY7_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY7_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY10
#define ISP_PRE_FILT_L_DES_PY10_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY10_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY9
#define ISP_PRE_FILT_L_DES_PY9_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY9_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY12
#define ISP_PRE_FILT_L_DES_PY12_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY12_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY11
#define ISP_PRE_FILT_L_DES_PY11_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY11_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY14
#define ISP_PRE_FILT_L_DES_PY14_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY14_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY13
#define ISP_PRE_FILT_L_DES_PY13_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY13_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PY16
#define ISP_PRE_FILT_L_DES_PY16_MASK (0xffff << 16 )
#define ISP_PRE_FILT_L_DES_PY16_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PY15
#define ISP_PRE_FILT_L_DES_PY15_MASK (0xffff << 0 )
#define ISP_PRE_FILT_L_DES_PY15_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PD4
#define ISP_PRE_FILT_L_DES_PD4_MASK (0xff << 24 )
#define ISP_PRE_FILT_L_DES_PD4_SHIFT 24U

#define ISP_PRE_FILT_L_DES_PD3
#define ISP_PRE_FILT_L_DES_PD3_MASK (0xff << 16 )
#define ISP_PRE_FILT_L_DES_PD3_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PD2
#define ISP_PRE_FILT_L_DES_PD2_MASK (0xff << 8 )
#define ISP_PRE_FILT_L_DES_PD2_SHIFT 8U

#define ISP_PRE_FILT_L_DES_PD1
#define ISP_PRE_FILT_L_DES_PD1_MASK (0xff << 0 )
#define ISP_PRE_FILT_L_DES_PD1_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PD8
#define ISP_PRE_FILT_L_DES_PD8_MASK (0xff << 24 )
#define ISP_PRE_FILT_L_DES_PD8_SHIFT 24U

#define ISP_PRE_FILT_L_DES_PD7
#define ISP_PRE_FILT_L_DES_PD7_MASK (0xff << 16 )
#define ISP_PRE_FILT_L_DES_PD7_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PD6
#define ISP_PRE_FILT_L_DES_PD6_MASK (0xff << 8 )
#define ISP_PRE_FILT_L_DES_PD6_SHIFT 8U

#define ISP_PRE_FILT_L_DES_PD5
#define ISP_PRE_FILT_L_DES_PD5_MASK (0xff << 0 )
#define ISP_PRE_FILT_L_DES_PD5_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PD12
#define ISP_PRE_FILT_L_DES_PD12_MASK (0xff << 24 )
#define ISP_PRE_FILT_L_DES_PD12_SHIFT 24U

#define ISP_PRE_FILT_L_DES_PD11
#define ISP_PRE_FILT_L_DES_PD11_MASK (0xff << 16 )
#define ISP_PRE_FILT_L_DES_PD11_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PD10
#define ISP_PRE_FILT_L_DES_PD10_MASK (0xff << 8 )
#define ISP_PRE_FILT_L_DES_PD10_SHIFT 8U

#define ISP_PRE_FILT_L_DES_PD9
#define ISP_PRE_FILT_L_DES_PD9_MASK (0xff << 0 )
#define ISP_PRE_FILT_L_DES_PD9_SHIFT 0U

#define ISP_PRE_FILT_L_DES_PD15
#define ISP_PRE_FILT_L_DES_PD15_MASK (0xff << 16 )
#define ISP_PRE_FILT_L_DES_PD15_SHIFT 16U

#define ISP_PRE_FILT_L_DES_PD14
#define ISP_PRE_FILT_L_DES_PD14_MASK (0xff << 8 )
#define ISP_PRE_FILT_L_DES_PD14_SHIFT 8U

#define ISP_PRE_FILT_L_DES_PD13
#define ISP_PRE_FILT_L_DES_PD13_MASK (0xff << 0 )
#define ISP_PRE_FILT_L_DES_PD13_SHIFT 0U

#define PREFILT_THRESH_BL0
#define PREFILT_THRESH_BL0_MASK (0x3ff << 0 )
#define PREFILT_THRESH_BL0_SHIFT 0U

#define PREFILT_THRESH_BL1
#define PREFILT_THRESH_BL1_MASK (0x3ff << 0 )
#define PREFILT_THRESH_BL1_SHIFT 0U

#define PREFILT_THRESH_SH0
#define PREFILT_THRESH_SH0_MASK (0x3ff << 0 )
#define PREFILT_THRESH_SH0_SHIFT 0U

#define PREFILT_THRESH_SH1
#define PREFILT_THRESH_SH1_MASK (0x3ff << 0 )
#define PREFILT_THRESH_SH1_SHIFT 0U

#define LUM_WEIGHT_GAIN
#define LUM_WEIGHT_GAIN_MASK (0x7 << 16 )
#define LUM_WEIGHT_GAIN_SHIFT 16U

#define LUM_WEIGHT_KINK
#define LUM_WEIGHT_KINK_MASK (0xff << 8 )
#define LUM_WEIGHT_KINK_SHIFT 8U

#define LUM_WEIGHT_MIN
#define LUM_WEIGHT_MIN_MASK (0xff << 0 )
#define LUM_WEIGHT_MIN_SHIFT 0U

#define PREFILT_FAC_SH1
#define PREFILT_FAC_SH1_MASK (0x3f << 0 )
#define PREFILT_FAC_SH1_SHIFT 0U

#define PREFILT_FAC_SH0
#define PREFILT_FAC_SH0_MASK (0x3f << 0 )
#define PREFILT_FAC_SH0_SHIFT 0U

#define PREFILT_FAC_MID
#define PREFILT_FAC_MID_MASK (0x3f << 0 )
#define PREFILT_FAC_MID_SHIFT 0U

#define PREFILT_FAC_BL0
#define PREFILT_FAC_BL0_MASK (0x3f << 0 )
#define PREFILT_FAC_BL0_SHIFT 0U

#define PREFILT_FAC_BL1
#define PREFILT_FAC_BL1_MASK (0x3f << 0 )
#define PREFILT_FAC_BL1_SHIFT 0U

#define ISP_PRE_FILT_IR_DENOISE_SW3
#define ISP_PRE_FILT_IR_DENOISE_SW3_MASK (0xff << 24 )
#define ISP_PRE_FILT_IR_DENOISE_SW3_SHIFT 24U

#define ISP_PRE_FILT_IR_DENOISE_SW2
#define ISP_PRE_FILT_IR_DENOISE_SW2_MASK (0xff << 16 )
#define ISP_PRE_FILT_IR_DENOISE_SW2_SHIFT 16U

#define ISP_PRE_FILT_IR_DENOISE_SW1
#define ISP_PRE_FILT_IR_DENOISE_SW1_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DENOISE_SW1_SHIFT 8U

#define ISP_PRE_FILT_IR_DENOISE_SW0
#define ISP_PRE_FILT_IR_DENOISE_SW0_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DENOISE_SW0_SHIFT 0U

#define ISP_PRE_FILT_IR_DENOISE_SW5
#define ISP_PRE_FILT_IR_DENOISE_SW5_MASK (0xff << 8 )
#define ISP_PRE_FILT_IR_DENOISE_SW5_SHIFT 8U

#define ISP_PRE_FILT_IR_DENOISE_SW4
#define ISP_PRE_FILT_IR_DENOISE_SW4_MASK (0xff << 0 )
#define ISP_PRE_FILT_IR_DENOISE_SW4_SHIFT 0U

#define PRE_FILT_H_SIZE
#define PRE_FILT_H_SIZE_MASK (0x7fff << 0 )
#define PRE_FILT_H_SIZE_SHIFT 0U

#define PRE_FILT_V_SIZE
#define PRE_FILT_V_SIZE_MASK (0x3fff << 0 )
#define PRE_FILT_V_SIZE_SHIFT 0U

#define PRE_FILT_DMY_HB
#define PRE_FILT_DMY_HB_MASK (0x1fff << 0 )
#define PRE_FILT_DMY_HB_SHIFT 0U


#define SP2_DMA_RAW_WIDTH_BYTES
#define SP2_DMA_RAW_WIDTH_BYTES_MASK (0xffff << 0 )
#define SP2_DMA_RAW_WIDTH_BYTES_SHIFT 0U

#define PPW_Y_BUF_FULL
#define PPW_Y_BUF_FULL_MASK (0x1 << 26)
#define PPW_Y_BUF_FULL_SHIFT 26U

#define PPW_U_BUF_FULL
#define PPW_U_BUF_FULL_MASK (0x1 << 25)
#define PPW_U_BUF_FULL_SHIFT 25U

#define PPW_V_BUF_FULL
#define PPW_V_BUF_FULL_MASK (0x1 << 24)
#define PPW_V_BUF_FULL_SHIFT 24U

#define PPR_Y_BUF_FULL
#define PPR_Y_BUF_FULL_MASK (0x1 << 23)
#define PPR_Y_BUF_FULL_SHIFT 23U

#define SP2_RAW2_W_BUF_FULL
#define SP2_RAW2_W_BUF_FULL_MASK (0x1 << 22)
#define SP2_RAW2_W_BUF_FULL_SHIFT 22U

#define SP2_RAW2_R_BUF_FULL
#define SP2_RAW2_R_BUF_FULL_MASK (0x1 << 21)
#define SP2_RAW2_R_BUF_FULL_SHIFT 21U

#define HDR_W_BUF_FULL
#define HDR_W_BUF_FULL_MASK (0x1 << 20)
#define HDR_W_BUF_FULL_SHIFT 20U

#define HDR_R_BUF_FULL
#define HDR_R_BUF_FULL_MASK (0x1 << 19)
#define HDR_R_BUF_FULL_SHIFT 19U

#define SP2_RAW2_DMA_READY
#define SP2_RAW2_DMA_READY_MASK (0x1 << 18)
#define SP2_RAW2_DMA_READY_SHIFT 18U

#define PPR_DMA_READY
#define PPR_DMA_READY_MASK (0x1 << 17)
#define PPR_DMA_READY_SHIFT 17U

#define WRAP_PPW_CR
#define WRAP_PPW_CR_MASK (0x1 << 15)
#define WRAP_PPW_CR_SHIFT 15U

#define WRAP_PPW_CB
#define WRAP_PPW_CB_MASK (0x1 << 14)
#define WRAP_PPW_CB_SHIFT 14U

#define WRAP_PPW_Y
#define WRAP_PPW_Y_MASK (0x1 << 13)
#define WRAP_PPW_Y_SHIFT 13U

#define SP2_RAW2_FRAME_END
#define SP2_RAW2_FRAME_END_MASK (0x1 << 12)
#define SP2_RAW2_FRAME_END_SHIFT 12U

#define PPW_FRAME_END
#define PPW_FRAME_END_MASK (0x1 << 11)
#define PPW_FRAME_END_SHIFT 11U

#define HDR_VS_DMA_READY
#define HDR_VS_DMA_READY_MASK (0x1 << 10)
#define HDR_VS_DMA_READY_SHIFT 10U

#define HDR_S_DMA_READY
#define HDR_S_DMA_READY_MASK (0x1 << 9)
#define HDR_S_DMA_READY_SHIFT 9U

#define HDR_L_DMA_READY
#define HDR_L_DMA_READY_MASK (0x1 << 8)
#define HDR_L_DMA_READY_SHIFT 8U

#define WRAP_HDR_VS
#define WRAP_HDR_VS_MASK (0x1 << 7)
#define WRAP_HDR_VS_SHIFT 7U

#define WRAP_HDR_S
#define WRAP_HDR_S_MASK (0x1 << 6)
#define WRAP_HDR_S_SHIFT 6U

#define WRAP_HDR_L
#define WRAP_HDR_L_MASK (0x1 << 5)
#define WRAP_HDR_L_SHIFT 5U

#define HDR_VS_FRAME_END
#define HDR_VS_FRAME_END_MASK (0x1 << 4)
#define HDR_VS_FRAME_END_SHIFT 4U

#define HDR_S_FRAME_END
#define HDR_S_FRAME_END_MASK (0x1 << 3)
#define HDR_S_FRAME_END_SHIFT 3U

#define HDR_L_FRAME_END
#define HDR_L_FRAME_END_MASK (0x1 << 2)
#define HDR_L_FRAME_END_SHIFT 2U

#define MI_RT_BUS_BUSERR
#define MI_RT_BUS_BUSERR_MASK (0x1 << 1)
#define MI_RT_BUS_BUSERR_SHIFT 1U

#define MI_RT_BUS_TIMEO
#define MI_RT_BUS_TIMEO_MASK (0x1 << 0)
#define MI_RT_BUS_TIMEO_SHIFT 0U

#endif /* _MRV_ALL_REGS_H */
