pmic.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Tests for the driver model pmic API
  4. *
  5. * Copyright (c) 2015 Samsung Electronics
  6. * Przemyslaw Marczak <p.marczak@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <malloc.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/root.h>
  15. #include <dm/util.h>
  16. #include <dm/test.h>
  17. #include <dm/uclass-internal.h>
  18. #include <power/pmic.h>
  19. #include <power/sandbox_pmic.h>
  20. #include <test/ut.h>
  21. #include <fsl_pmic.h>
  22. /* Test PMIC get method */
  23. static inline int power_pmic_get(struct unit_test_state *uts, char *name)
  24. {
  25. struct udevice *dev;
  26. ut_assertok(pmic_get(name, &dev));
  27. ut_assertnonnull(dev);
  28. /* Check PMIC's name */
  29. ut_asserteq_str(name, dev->name);
  30. return 0;
  31. }
  32. /* Test PMIC get method */
  33. static int dm_test_power_pmic_get(struct unit_test_state *uts)
  34. {
  35. power_pmic_get(uts, "sandbox_pmic");
  36. return 0;
  37. }
  38. DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
  39. /* PMIC get method - MC34708 - for 3 bytes transmission */
  40. static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
  41. {
  42. power_pmic_get(uts, "pmic@41");
  43. return 0;
  44. }
  45. DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
  46. /* Test PMIC I/O */
  47. static int dm_test_power_pmic_io(struct unit_test_state *uts)
  48. {
  49. const char *name = "sandbox_pmic";
  50. uint8_t out_buffer, in_buffer;
  51. struct udevice *dev;
  52. int reg_count, i;
  53. ut_assertok(pmic_get(name, &dev));
  54. reg_count = pmic_reg_count(dev);
  55. ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
  56. /*
  57. * Test PMIC I/O - write and read a loop counter.
  58. * usually we can't write to all PMIC's registers in the real hardware,
  59. * but we can to the sandbox pmic.
  60. */
  61. for (i = 0; i < reg_count; i++) {
  62. out_buffer = i;
  63. ut_assertok(pmic_write(dev, i, &out_buffer, 1));
  64. ut_assertok(pmic_read(dev, i, &in_buffer, 1));
  65. ut_asserteq(out_buffer, in_buffer);
  66. }
  67. return 0;
  68. }
  69. DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
  70. #define MC34708_PMIC_REG_COUNT 64
  71. #define MC34708_PMIC_TEST_VAL 0x125534
  72. static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
  73. {
  74. struct udevice *dev;
  75. int reg_count;
  76. ut_assertok(pmic_get("pmic@41", &dev));
  77. /* Check number of PMIC registers */
  78. reg_count = pmic_reg_count(dev);
  79. ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
  80. return 0;
  81. }
  82. DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
  83. static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
  84. {
  85. struct udevice *dev;
  86. int val;
  87. ut_assertok(pmic_get("pmic@41", &dev));
  88. /* Check if single 3 byte read is successful */
  89. val = pmic_reg_read(dev, REG_POWER_CTL2);
  90. ut_asserteq(val, 0x422100);
  91. /* Check if RW works */
  92. val = 0;
  93. ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
  94. ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
  95. val = pmic_reg_read(dev, REG_RTC_TIME);
  96. ut_asserteq(val, MC34708_PMIC_TEST_VAL);
  97. pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
  98. val = pmic_reg_read(dev, REG_POWER_CTL2);
  99. ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
  100. return 0;
  101. }
  102. DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);