Makefile.build 14 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. # ==========================================================================
  3. # Building
  4. # ==========================================================================
  5. # Modified for U-Boot
  6. prefix := tpl
  7. src := $(patsubst $(prefix)/%,%,$(obj))
  8. ifeq ($(obj),$(src))
  9. prefix := spl
  10. src := $(patsubst $(prefix)/%,%,$(obj))
  11. ifeq ($(obj),$(src))
  12. prefix := ppl
  13. src := $(patsubst $(prefix)/%,%,$(obj))
  14. ifeq ($(obj),$(src))
  15. prefix := .
  16. endif
  17. endif
  18. endif
  19. PHONY := __build
  20. __build:
  21. # Init all relevant variables used in kbuild files so
  22. # 1) they have correct type
  23. # 2) they do not inherit any value from the environment
  24. obj-y :=
  25. obj-m :=
  26. lib-y :=
  27. lib-m :=
  28. always :=
  29. targets :=
  30. subdir-y :=
  31. subdir-m :=
  32. EXTRA_AFLAGS :=
  33. EXTRA_CFLAGS :=
  34. EXTRA_CPPFLAGS :=
  35. EXTRA_LDFLAGS :=
  36. asflags-y :=
  37. ccflags-y :=
  38. cppflags-y :=
  39. ldflags-y :=
  40. subdir-asflags-y :=
  41. subdir-ccflags-y :=
  42. # Read auto.conf if it exists, otherwise ignore
  43. # Modified for U-Boot
  44. -include include/config/auto.conf
  45. -include $(prefix)/include/autoconf.mk
  46. include scripts/Makefile.uncmd_spl
  47. include scripts/Kbuild.include
  48. # For backward compatibility check that these variables do not change
  49. save-cflags := $(CFLAGS)
  50. # The filename Kbuild has precedence over Makefile
  51. kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
  52. kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
  53. include $(kbuild-file)
  54. # Added for U-Boot
  55. asflags-y += $(PLATFORM_CPPFLAGS)
  56. ccflags-y += $(PLATFORM_CPPFLAGS)
  57. cppflags-y += $(PLATFORM_CPPFLAGS)
  58. # If the save-* variables changed error out
  59. ifeq ($(KBUILD_NOPEDANTIC),)
  60. ifneq ("$(save-cflags)","$(CFLAGS)")
  61. $(error CFLAGS was changed in "$(kbuild-file)". Fix it to use ccflags-y)
  62. endif
  63. endif
  64. include scripts/Makefile.lib
  65. ifdef host-progs
  66. ifneq ($(hostprogs-y),$(host-progs))
  67. $(warning kbuild: $(obj)/Makefile - Usage of host-progs is deprecated. Please replace with hostprogs-y!)
  68. hostprogs-y += $(host-progs)
  69. endif
  70. endif
  71. # Do not include host rules unless needed
  72. ifneq ($(hostprogs-y)$(hostprogs-m),)
  73. include scripts/Makefile.host
  74. endif
  75. # Uncommented for U-Boot
  76. # We need to create output dicrectory for SPL and TPL even for in-tree build
  77. #ifneq ($(KBUILD_SRC),)
  78. # Create output directory if not already present
  79. _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
  80. # Create directories for object files if directory does not exist
  81. # Needed when obj-y := dir/file.o syntax is used
  82. _dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
  83. #endif
  84. ifndef obj
  85. $(warning kbuild: Makefile.build is included improperly)
  86. endif
  87. # ===========================================================================
  88. ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),)
  89. lib-target := $(obj)/lib.a
  90. endif
  91. ifneq ($(strip $(obj-y) $(obj-m) $(obj-) $(subdir-m) $(lib-target)),)
  92. builtin-target := $(obj)/built-in.o
  93. endif
  94. modorder-target := $(obj)/modules.order
  95. # We keep a list of all modules in $(MODVERDIR)
  96. __build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
  97. $(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \
  98. $(subdir-ym) $(always)
  99. @:
  100. # Linus' kernel sanity checking tool
  101. ifneq ($(KBUILD_CHECKSRC),0)
  102. ifeq ($(KBUILD_CHECKSRC),2)
  103. quiet_cmd_force_checksrc = CHECK $<
  104. cmd_force_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
  105. else
  106. quiet_cmd_checksrc = CHECK $<
  107. cmd_checksrc = $(CHECK) $(CHECKFLAGS) $(c_flags) $< ;
  108. endif
  109. endif
  110. # Do section mismatch analysis for each module/built-in.o
  111. ifdef CONFIG_DEBUG_SECTION_MISMATCH
  112. cmd_secanalysis = ; scripts/mod/modpost $@
  113. endif
  114. # Compile C sources (.c)
  115. # ---------------------------------------------------------------------------
  116. # Default is built-in, unless we know otherwise
  117. modkern_cflags = \
  118. $(if $(part-of-module), \
  119. $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE), \
  120. $(KBUILD_CFLAGS_KERNEL) $(CFLAGS_KERNEL))
  121. quiet_modtag := $(empty) $(empty)
  122. $(real-objs-m) : part-of-module := y
  123. $(real-objs-m:.o=.i) : part-of-module := y
  124. $(real-objs-m:.o=.s) : part-of-module := y
  125. $(real-objs-m:.o=.lst): part-of-module := y
  126. $(real-objs-m) : quiet_modtag := [M]
  127. $(real-objs-m:.o=.i) : quiet_modtag := [M]
  128. $(real-objs-m:.o=.s) : quiet_modtag := [M]
  129. $(real-objs-m:.o=.lst): quiet_modtag := [M]
  130. $(obj-m) : quiet_modtag := [M]
  131. # Default for not multi-part modules
  132. modname = $(basetarget)
  133. $(multi-objs-m) : modname = $(modname-multi)
  134. $(multi-objs-m:.o=.i) : modname = $(modname-multi)
  135. $(multi-objs-m:.o=.s) : modname = $(modname-multi)
  136. $(multi-objs-m:.o=.lst) : modname = $(modname-multi)
  137. $(multi-objs-y) : modname = $(modname-multi)
  138. $(multi-objs-y:.o=.i) : modname = $(modname-multi)
  139. $(multi-objs-y:.o=.s) : modname = $(modname-multi)
  140. $(multi-objs-y:.o=.lst) : modname = $(modname-multi)
  141. quiet_cmd_cc_s_c = CC $(quiet_modtag) $@
  142. cmd_cc_s_c = $(CC) $(c_flags) $(DISABLE_LTO) -fverbose-asm -S -o $@ $<
  143. $(obj)/%.s: $(src)/%.c FORCE
  144. $(call if_changed_dep,cc_s_c)
  145. quiet_cmd_cc_i_c = CPP $(quiet_modtag) $@
  146. cmd_cc_i_c = $(CPP) $(c_flags) -o $@ $<
  147. $(obj)/%.i: $(src)/%.c FORCE
  148. $(call if_changed_dep,cc_i_c)
  149. cmd_gensymtypes = \
  150. $(CPP) -D__GENKSYMS__ $(c_flags) $< | \
  151. $(GENKSYMS) $(if $(1), -T $(2)) \
  152. $(patsubst y,-s _,$(CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX)) \
  153. $(if $(KBUILD_PRESERVE),-p) \
  154. -r $(firstword $(wildcard $(2:.symtypes=.symref) /dev/null))
  155. quiet_cmd_cc_symtypes_c = SYM $(quiet_modtag) $@
  156. cmd_cc_symtypes_c = \
  157. set -e; \
  158. $(call cmd_gensymtypes,true,$@) >/dev/null; \
  159. test -s $@ || rm -f $@
  160. $(obj)/%.symtypes : $(src)/%.c FORCE
  161. $(call cmd,cc_symtypes_c)
  162. # C (.c) files
  163. # The C file is compiled and updated dependency information is generated.
  164. # (See cmd_cc_o_c + relevant part of rule_cc_o_c)
  165. quiet_cmd_cc_o_c = CC $(quiet_modtag) $@
  166. ifndef CONFIG_MODVERSIONS
  167. cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
  168. else
  169. # When module versioning is enabled the following steps are executed:
  170. # o compile a .tmp_<file>.o from <file>.c
  171. # o if .tmp_<file>.o doesn't contain a __ksymtab version, i.e. does
  172. # not export symbols, we just rename .tmp_<file>.o to <file>.o and
  173. # are done.
  174. # o otherwise, we calculate symbol versions using the good old
  175. # genksyms on the preprocessed source and postprocess them in a way
  176. # that they are usable as a linker script
  177. # o generate <file>.o from .tmp_<file>.o using the linker to
  178. # replace the unresolved symbols __crc_exported_symbol with
  179. # the actual value of the checksum generated by genksyms
  180. cmd_cc_o_c = $(CC) $(c_flags) -c -o $(@D)/.tmp_$(@F) $<
  181. cmd_modversions = \
  182. if $(OBJDUMP) -h $(@D)/.tmp_$(@F) | grep -q __ksymtab; then \
  183. $(call cmd_gensymtypes,$(KBUILD_SYMTYPES),$(@:.o=.symtypes)) \
  184. > $(@D)/.tmp_$(@F:.o=.ver); \
  185. \
  186. $(LD) $(LDFLAGS) -r -o $@ $(@D)/.tmp_$(@F) \
  187. -T $(@D)/.tmp_$(@F:.o=.ver); \
  188. rm -f $(@D)/.tmp_$(@F) $(@D)/.tmp_$(@F:.o=.ver); \
  189. else \
  190. mv -f $(@D)/.tmp_$(@F) $@; \
  191. fi;
  192. endif
  193. ifdef CONFIG_FTRACE_MCOUNT_RECORD
  194. ifdef BUILD_C_RECORDMCOUNT
  195. ifeq ("$(origin RECORDMCOUNT_WARN)", "command line")
  196. RECORDMCOUNT_FLAGS = -w
  197. endif
  198. # Due to recursion, we must skip empty.o.
  199. # The empty.o file is created in the make process in order to determine
  200. # the target endianness and word size. It is made before all other C
  201. # files, including recordmcount.
  202. sub_cmd_record_mcount = \
  203. if [ $(@) != "scripts/mod/empty.o" ]; then \
  204. $(objtree)/scripts/recordmcount $(RECORDMCOUNT_FLAGS) "$(@)"; \
  205. fi;
  206. recordmcount_source := $(srctree)/scripts/recordmcount.c \
  207. $(srctree)/scripts/recordmcount.h
  208. else
  209. sub_cmd_record_mcount = set -e ; perl $(srctree)/scripts/recordmcount.pl "$(ARCH)" \
  210. "$(if $(CONFIG_CPU_BIG_ENDIAN),big,little)" \
  211. "$(if $(CONFIG_64BIT),64,32)" \
  212. "$(OBJDUMP)" "$(OBJCOPY)" "$(CC) $(KBUILD_CFLAGS)" \
  213. "$(LD)" "$(NM)" "$(RM)" "$(MV)" \
  214. "$(if $(part-of-module),1,0)" "$(@)";
  215. recordmcount_source := $(srctree)/scripts/recordmcount.pl
  216. endif
  217. cmd_record_mcount = \
  218. if [ "$(findstring $(CC_FLAGS_FTRACE),$(_c_flags))" = \
  219. "$(CC_FLAGS_FTRACE)" ]; then \
  220. $(sub_cmd_record_mcount) \
  221. fi;
  222. endif
  223. define rule_cc_o_c
  224. $(call echo-cmd,checksrc) $(cmd_checksrc) \
  225. $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \
  226. $(cmd_modversions) \
  227. $(call echo-cmd,record_mcount) \
  228. $(cmd_record_mcount) \
  229. scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,cc_o_c)' > \
  230. $(dot-target).tmp; \
  231. rm -f $(depfile); \
  232. mv -f $(dot-target).tmp $(dot-target).cmd
  233. endef
  234. # Built-in and composite module parts
  235. $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
  236. $(call cmd,force_checksrc)
  237. $(call if_changed_rule,cc_o_c)
  238. # Single-part modules are special since we need to mark them in $(MODVERDIR)
  239. $(single-used-m): $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
  240. $(call cmd,force_checksrc)
  241. $(call if_changed_rule,cc_o_c)
  242. @{ echo $(@:.o=.ko); echo $@; } > $(MODVERDIR)/$(@F:.o=.mod)
  243. quiet_cmd_cc_lst_c = MKLST $@
  244. cmd_cc_lst_c = $(CC) $(c_flags) -g -c -o $*.o $< && \
  245. $(CONFIG_SHELL) $(srctree)/scripts/makelst $*.o \
  246. System.map $(OBJDUMP) > $@
  247. $(obj)/%.lst: $(src)/%.c FORCE
  248. $(call if_changed_dep,cc_lst_c)
  249. # Compile assembler sources (.S)
  250. # ---------------------------------------------------------------------------
  251. modkern_aflags := $(KBUILD_AFLAGS_KERNEL) $(AFLAGS_KERNEL)
  252. $(real-objs-m) : modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
  253. $(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
  254. quiet_cmd_as_s_S = CPP $(quiet_modtag) $@
  255. cmd_as_s_S = $(CPP) $(a_flags) -o $@ $<
  256. $(obj)/%.s: $(src)/%.S FORCE
  257. $(call if_changed_dep,as_s_S)
  258. quiet_cmd_as_o_S = AS $(quiet_modtag) $@
  259. cmd_as_o_S = $(CC) $(a_flags) -c -o $@ $<
  260. $(obj)/%.o: $(src)/%.S FORCE
  261. $(call if_changed_dep,as_o_S)
  262. targets += $(real-objs-y) $(real-objs-m) $(lib-y)
  263. targets += $(extra-y) $(MAKECMDGOALS) $(always)
  264. # Linker scripts preprocessor (.lds.S -> .lds)
  265. # ---------------------------------------------------------------------------
  266. quiet_cmd_cpp_lds_S = LDS $@
  267. cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \
  268. -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
  269. $(obj)/%.lds: $(src)/%.lds.S FORCE
  270. $(call if_changed_dep,cpp_lds_S)
  271. # ASN.1 grammar
  272. # ---------------------------------------------------------------------------
  273. quiet_cmd_asn1_compiler = ASN.1 $@
  274. cmd_asn1_compiler = $(objtree)/tools/asn1_compiler $< \
  275. $(subst .h,.c,$@) $(subst .c,.h,$@)
  276. $(obj)/%.asn1.c $(obj)/%.asn1.h: $(src)/%.asn1 $(objtree)/tools/asn1_compiler
  277. $(call cmd,asn1_compiler)
  278. # Build the compiled-in targets
  279. # ---------------------------------------------------------------------------
  280. # To build objects in subdirs, we need to descend into the directories
  281. $(sort $(subdir-obj-y)): $(subdir-ym) ;
  282. #
  283. # Rule to compile a set of .o files into one .o file
  284. #
  285. ifdef builtin-target
  286. quiet_cmd_link_o_target = LD $@
  287. # If the list of objects to link is empty, just create an empty built-in.o
  288. cmd_link_o_target = $(if $(strip $(obj-y)),\
  289. $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
  290. $(cmd_secanalysis),\
  291. rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
  292. $(builtin-target): $(obj-y) FORCE
  293. $(call if_changed,link_o_target)
  294. targets += $(builtin-target)
  295. endif # builtin-target
  296. #
  297. # Rule to create modules.order file
  298. #
  299. # Create commands to either record .ko file or cat modules.order from
  300. # a subdirectory
  301. modorder-cmds = \
  302. $(foreach m, $(modorder), \
  303. $(if $(filter %/modules.order, $m), \
  304. cat $m;, echo kernel/$m;))
  305. $(modorder-target): $(subdir-ym) FORCE
  306. $(Q)(cat /dev/null; $(modorder-cmds)) > $@
  307. #
  308. # Rule to compile a set of .o files into one .a file
  309. #
  310. ifdef lib-target
  311. quiet_cmd_link_l_target = AR $@
  312. cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
  313. $(lib-target): $(lib-y) FORCE
  314. $(call if_changed,link_l_target)
  315. targets += $(lib-target)
  316. endif
  317. #
  318. # Rule to link composite objects
  319. #
  320. # Composite objects are specified in kbuild makefile as follows:
  321. # <composite-object>-objs := <list of .o files>
  322. # or
  323. # <composite-object>-y := <list of .o files>
  324. link_multi_deps = \
  325. $(filter $(addprefix $(obj)/, \
  326. $($(subst $(obj)/,,$(@:.o=-objs))) \
  327. $($(subst $(obj)/,,$(@:.o=-y)))), $^)
  328. quiet_cmd_link_multi-y = LD $@
  329. cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
  330. quiet_cmd_link_multi-m = LD [M] $@
  331. cmd_link_multi-m = $(cmd_link_multi-y)
  332. $(multi-used-y): FORCE
  333. $(call if_changed,link_multi-y)
  334. $(call multi_depend, $(multi-used-y), .o, -objs -y)
  335. $(multi-used-m): FORCE
  336. $(call if_changed,link_multi-m)
  337. @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
  338. $(call multi_depend, $(multi-used-m), .o, -objs -y)
  339. targets += $(multi-used-y) $(multi-used-m)
  340. # Add intermediate targets:
  341. # When building objects with specific suffix patterns, add intermediate
  342. # targets that the final targets are derived from.
  343. intermediate_targets = $(foreach sfx, $(2), \
  344. $(patsubst %$(strip $(1)),%$(sfx), \
  345. $(filter %$(strip $(1)), $(targets))))
  346. # %.lex.o <- %.lex.c <- %.l
  347. # %.tab.o <- %.tab.[ch] <- %.y
  348. targets += $(call intermediate_targets, .lex.o, .lex.c) \
  349. $(call intermediate_targets, .tab.o, .tab.c .tab.h)
  350. # Descending
  351. # ---------------------------------------------------------------------------
  352. PHONY += $(subdir-ym)
  353. $(subdir-ym):
  354. $(Q)$(MAKE) $(build)=$@
  355. # Add FORCE to the prequisites of a target to force it to be always rebuilt.
  356. # ---------------------------------------------------------------------------
  357. PHONY += FORCE
  358. FORCE:
  359. # Read all saved command lines and dependencies for the $(targets) we
  360. # may be building above, using $(if_changed{,_dep}). As an
  361. # optimization, we don't need to read them if the target does not
  362. # exist, we will rebuild anyway in that case.
  363. targets := $(wildcard $(sort $(targets)))
  364. cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
  365. ifneq ($(cmd_files),)
  366. include $(cmd_files)
  367. endif
  368. # Declare the contents of the .PHONY variable as phony. We keep that
  369. # information in a variable se we can use it in if_changed and friends.
  370. .PHONY: $(PHONY)