rlwinm.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. /*
  9. * CPU test
  10. * Shift instructions: rlwinm
  11. *
  12. * The test contains a pre-built table of instructions, operands and
  13. * expected results. For each table entry, the test will cyclically use
  14. * different sets of operand registers and result registers.
  15. */
  16. #include <post.h>
  17. #include "cpu_asm.h"
  18. #if CONFIG_POST & CONFIG_SYS_POST_CPU
  19. extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
  20. extern ulong cpu_post_makecr (long v);
  21. static struct cpu_post_rlwinm_s
  22. {
  23. ulong cmd;
  24. ulong op1;
  25. uchar op2;
  26. uchar mb;
  27. uchar me;
  28. ulong res;
  29. } cpu_post_rlwinm_table[] =
  30. {
  31. {
  32. OP_RLWINM,
  33. 0xffff0000,
  34. 24,
  35. 16,
  36. 23,
  37. 0x0000ff00
  38. },
  39. };
  40. static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
  41. int cpu_post_test_rlwinm (void)
  42. {
  43. int ret = 0;
  44. unsigned int i, reg;
  45. int flag = disable_interrupts();
  46. for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
  47. {
  48. struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
  49. for (reg = 0; reg < 32 && ret == 0; reg++)
  50. {
  51. unsigned int reg0 = (reg + 0) % 32;
  52. unsigned int reg1 = (reg + 1) % 32;
  53. unsigned int stk = reg < 16 ? 31 : 15;
  54. unsigned long code[] =
  55. {
  56. ASM_STW(stk, 1, -4),
  57. ASM_ADDI(stk, 1, -16),
  58. ASM_STW(3, stk, 8),
  59. ASM_STW(reg0, stk, 4),
  60. ASM_STW(reg1, stk, 0),
  61. ASM_LWZ(reg0, stk, 8),
  62. ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  63. ASM_STW(reg1, stk, 8),
  64. ASM_LWZ(reg1, stk, 0),
  65. ASM_LWZ(reg0, stk, 4),
  66. ASM_LWZ(3, stk, 8),
  67. ASM_ADDI(1, stk, 16),
  68. ASM_LWZ(stk, 1, -4),
  69. ASM_BLR,
  70. };
  71. unsigned long codecr[] =
  72. {
  73. ASM_STW(stk, 1, -4),
  74. ASM_ADDI(stk, 1, -16),
  75. ASM_STW(3, stk, 8),
  76. ASM_STW(reg0, stk, 4),
  77. ASM_STW(reg1, stk, 0),
  78. ASM_LWZ(reg0, stk, 8),
  79. ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
  80. test->me) | BIT_C,
  81. ASM_STW(reg1, stk, 8),
  82. ASM_LWZ(reg1, stk, 0),
  83. ASM_LWZ(reg0, stk, 4),
  84. ASM_LWZ(3, stk, 8),
  85. ASM_ADDI(1, stk, 16),
  86. ASM_LWZ(stk, 1, -4),
  87. ASM_BLR,
  88. };
  89. ulong res;
  90. ulong cr;
  91. if (ret == 0)
  92. {
  93. cr = 0;
  94. cpu_post_exec_21 (code, & cr, & res, test->op1);
  95. ret = res == test->res && cr == 0 ? 0 : -1;
  96. if (ret != 0)
  97. {
  98. post_log ("Error at rlwinm test %d !\n", i);
  99. }
  100. }
  101. if (ret == 0)
  102. {
  103. cpu_post_exec_21 (codecr, & cr, & res, test->op1);
  104. ret = res == test->res &&
  105. (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
  106. if (ret != 0)
  107. {
  108. post_log ("Error at rlwinm test %d !\n", i);
  109. }
  110. }
  111. }
  112. }
  113. if (flag)
  114. enable_interrupts();
  115. return ret;
  116. }
  117. #endif