ecc.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Eastman Kodak Company, <www.kodak.com>
  5. * Michael Zaidman, <michael.zaidman@kodak.com>
  6. *
  7. * The code is based on the cpu/mpc83xx/ecc.c written by
  8. * Dave Liu <daveliu@freescale.com>
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <irq_func.h>
  13. #include <mpc83xx.h>
  14. #include <watchdog.h>
  15. #include <asm/io.h>
  16. #include <post.h>
  17. #if CONFIG_POST & CONFIG_SYS_POST_ECC
  18. /*
  19. * We use the RAW I/O accessors where possible in order to
  20. * achieve performance goal, since the test's execution time
  21. * affects the board start up time.
  22. */
  23. static inline void ecc_clear(ddr83xx_t *ddr)
  24. {
  25. /* Clear capture registers */
  26. __raw_writel(0, &ddr->capture_address);
  27. __raw_writel(0, &ddr->capture_data_hi);
  28. __raw_writel(0, &ddr->capture_data_lo);
  29. __raw_writel(0, &ddr->capture_ecc);
  30. __raw_writel(0, &ddr->capture_attributes);
  31. /* Clear SBEC and set SBET to 1 */
  32. out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
  33. /* Clear Error Detect register */
  34. out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
  35. ECC_ERROR_DETECT_MBE |\
  36. ECC_ERROR_DETECT_SBE |\
  37. ECC_ERROR_DETECT_MSE);
  38. isync();
  39. }
  40. int ecc_post_test(int flags)
  41. {
  42. int ret = 0;
  43. int int_state;
  44. int errbit;
  45. u32 pattern[2], writeback[2], retval[2];
  46. ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr;
  47. volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR;
  48. /* The pattern is written into memory to generate error */
  49. pattern[0] = 0xfedcba98UL;
  50. pattern[1] = 0x76543210UL;
  51. /* After injecting error, re-initialize the memory with the value */
  52. writeback[0] = ~pattern[0];
  53. writeback[1] = ~pattern[1];
  54. /* Check if ECC is enabled */
  55. if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) {
  56. debug("DDR's ECC is not enabled, skipping the ECC POST.\n");
  57. return 0;
  58. }
  59. int_state = disable_interrupts();
  60. icache_enable();
  61. #ifdef CONFIG_DDR_32BIT
  62. /* It seems like no one really uses the CONFIG_DDR_32BIT mode */
  63. #error "Add ECC POST support for CONFIG_DDR_32BIT here!"
  64. #else
  65. for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
  66. addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
  67. WATCHDOG_RESET();
  68. ecc_clear(ddr);
  69. /* Enable error injection */
  70. setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
  71. sync();
  72. isync();
  73. /* Set bit to be injected */
  74. if (errbit < 32) {
  75. __raw_writel(1 << errbit, &ddr->data_err_inject_lo);
  76. __raw_writel(0, &ddr->data_err_inject_hi);
  77. } else {
  78. __raw_writel(0, &ddr->data_err_inject_lo);
  79. __raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi);
  80. }
  81. sync();
  82. isync();
  83. /* Write memory location injecting SBE */
  84. ppcDWstore((u32*)addr, pattern);
  85. sync();
  86. /* Disable error injection */
  87. clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
  88. sync();
  89. isync();
  90. /* Data read should generate SBE */
  91. ppcDWload((u32*)addr, retval);
  92. sync();
  93. if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) ||
  94. (__raw_readl(&ddr->data_err_inject_hi) !=
  95. (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) ||
  96. (__raw_readl(&ddr->data_err_inject_lo) !=
  97. (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) {
  98. post_log("ECC failed to detect SBE error at %08x, "
  99. "SBE injection mask %08x-%08x, wrote "
  100. "%08x-%08x, read %08x-%08x\n", addr,
  101. ddr->data_err_inject_hi,
  102. ddr->data_err_inject_lo,
  103. pattern[0], pattern[1],
  104. retval[0], retval[1]);
  105. printf("ERR_DETECT Reg: %08x\n", ddr->err_detect);
  106. printf("ECC CAPTURE_DATA Reg: %08x-%08x\n",
  107. ddr->capture_data_hi, ddr->capture_data_lo);
  108. ret = 1;
  109. break;
  110. }
  111. /* Re-initialize the ECC memory */
  112. ppcDWstore((u32*)addr, writeback);
  113. sync();
  114. isync();
  115. errbit %= 63;
  116. }
  117. #endif /* !CONFIG_DDR_32BIT */
  118. ecc_clear(ddr);
  119. icache_disable();
  120. if (int_state)
  121. enable_interrupts();
  122. return ret;
  123. }
  124. #endif