vsc9953.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013, 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Driver for the Vitesse VSC9953 L2 Switch
  6. */
  7. #ifndef _VSC9953_H_
  8. #define _VSC9953_H_
  9. #include <config.h>
  10. #include <miiphy.h>
  11. #include <asm/types.h>
  12. #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
  13. #define VSC9953_SYS_OFFSET 0x010000
  14. #define VSC9953_REW_OFFSET 0x030000
  15. #define VSC9953_DEV_GMII_OFFSET 0x100000
  16. #define VSC9953_QSYS_OFFSET 0x200000
  17. #define VSC9953_ANA_OFFSET 0x280000
  18. #define VSC9953_DEVCPU_GCB 0x070000
  19. #define VSC9953_ES0 0x040000
  20. #define VSC9953_IS1 0x050000
  21. #define VSC9953_IS2 0x060000
  22. #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
  23. #define VSC9953_PHY_REGS_OFFST 0x0000AC
  24. /* Macros for vsc9953_chip_regs.soft_rst register */
  25. #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
  26. /* Macros for vsc9953_sys_sys.reset_cfg register */
  27. #define VSC9953_CORE_ENABLE 0x80
  28. #define VSC9953_MEM_ENABLE 0x40
  29. #define VSC9953_MEM_INIT 0x20
  30. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
  31. #define VSC9953_MAC_ENA_CFG 0x00000011
  32. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
  33. #define VSC9953_MAC_MODE_CFG 0x00000011
  34. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
  35. #define VSC9953_MAC_IFG_CFG 0x00000515
  36. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
  37. #define VSC9953_MAC_HDX_CFG 0x00001043
  38. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
  39. #define VSC9953_MAC_MAX_LEN 0x000005ee
  40. /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
  41. #define VSC9953_CLOCK_CFG 0x00000001
  42. #define VSC9953_CLOCK_CFG_1000M 0x00000001
  43. /* Macros for vsc9953_sys_sys.front_port_mode register */
  44. #define VSC9953_FRONT_PORT_MODE 0x00000000
  45. /* Macros for vsc9953_ana_pfc.pfc_cfg register */
  46. #define VSC9953_PFC_FC 0x00000001
  47. #define VSC9953_PFC_FC_QSGMII 0x00000000
  48. /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
  49. #define VSC9953_MAC_FC_CFG 0x04700000
  50. #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
  51. /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
  52. #define VSC9953_PAUSE_CFG 0x001ffffe
  53. /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
  54. #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
  55. /* Macros for vsc9953_sys_sys.stat_cfg register */
  56. #define VSC9953_STAT_CLEAR_RX 0x00000400
  57. #define VSC9953_STAT_CLEAR_TX 0x00000800
  58. #define VSC9953_STAT_CLEAR_DR 0x00001000
  59. /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
  60. #define VSC9953_VCAP_MV_CFG 0x0000ffff
  61. #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
  62. /* Macros for register vsc9953_ana_ana_tables.mac_access register */
  63. #define VSC9953_MAC_CMD_IDLE 0x00000000
  64. #define VSC9953_MAC_CMD_LEARN 0x00000001
  65. #define VSC9953_MAC_CMD_FORGET 0x00000002
  66. #define VSC9953_MAC_CMD_AGE 0x00000003
  67. #define VSC9953_MAC_CMD_NEXT 0x00000004
  68. #define VSC9953_MAC_CMD_READ 0x00000006
  69. #define VSC9953_MAC_CMD_WRITE 0x00000007
  70. #define VSC9953_MAC_CMD_MASK 0x00000007
  71. #define VSC9953_MAC_CMD_VALID 0x00000800
  72. #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
  73. #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
  74. #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
  75. #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
  76. #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
  77. #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
  78. #define VSC9953_MAC_VID_MASK 0x1fff0000
  79. #define VSC9953_MAC_MACH_MASK 0x0000ffff
  80. /* Macros for vsc9953_ana_port.vlan_cfg register */
  81. #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
  82. #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
  83. #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
  84. #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
  85. #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
  86. /* Macros for vsc9953_rew_port.port_vlan_cfg register */
  87. #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
  88. /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
  89. #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
  90. /* Macros for vsc9953_ana_ana_tables.vlan_access register */
  91. #define VSC9953_VLAN_PORT_MASK 0x00001ffc
  92. #define VSC9953_VLAN_CMD_MASK 0x00000003
  93. #define VSC9953_VLAN_CMD_IDLE 0x00000000
  94. #define VSC9953_VLAN_CMD_READ 0x00000001
  95. #define VSC9953_VLAN_CMD_WRITE 0x00000002
  96. #define VSC9953_VLAN_CMD_INIT 0x00000003
  97. /* Macros for vsc9953_ana_port.port_cfg register */
  98. #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
  99. #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
  100. #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
  101. #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
  102. #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
  103. /* Macros for vsc9953_qsys_sys.switch_port_mode register */
  104. #define VSC9953_PORT_ENA 0x00002000
  105. /* Macros for vsc9953_ana_ana.agen_ctrl register */
  106. #define VSC9953_FID_MASK_ALL 0x00fff000
  107. /* Macros for vsc9953_ana_ana.adv_learn register */
  108. #define VSC9953_VLAN_CHK 0x00000400
  109. /* Macros for vsc9953_ana_ana.auto_age register */
  110. #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
  111. /* Macros for vsc9953_rew_port.port_tag_cfg register */
  112. #define VSC9953_TAG_CFG_MASK 0x00000180
  113. #define VSC9953_TAG_CFG_NONE 0x00000000
  114. #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
  115. #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
  116. #define VSC9953_TAG_CFG_ALL 0x00000180
  117. #define VSC9953_TAG_VID_PVID 0x00000010
  118. /* Macros for vsc9953_ana_ana.anag_efil register */
  119. #define VSC9953_AGE_PORT_EN 0x00080000
  120. #define VSC9953_AGE_PORT_MASK 0x0007c000
  121. #define VSC9953_AGE_VID_EN 0x00002000
  122. #define VSC9953_AGE_VID_MASK 0x00001fff
  123. /* Macros for vsc9953_ana_ana_tables.mach_data register */
  124. #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
  125. /* Macros for vsc9953_ana_common.aggr_cfg register */
  126. #define VSC9953_AC_RND_ENA 0x00000080
  127. #define VSC9953_AC_DMAC_ENA 0x00000040
  128. #define VSC9953_AC_SMAC_ENA 0x00000020
  129. #define VSC9953_AC_IP6_LBL_ENA 0x00000010
  130. #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
  131. #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
  132. #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
  133. #define VSC9953_AC_MASK 0x000000fe
  134. /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
  135. #define VSC9953_PGID_PORT_MASK 0x000003ff
  136. #define VSC9953_MAX_PORTS 10
  137. #define VSC9953_PORT_CHECK(port) \
  138. (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
  139. #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
  140. ( \
  141. (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
  142. ) ? 0 : 1 \
  143. )
  144. #define VSC9953_MAX_VLAN 4096
  145. #define VSC9953_VLAN_CHECK(vid) \
  146. (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
  147. #define VSC9953_DEFAULT_AGE_TIME 300
  148. #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
  149. #define MIIMIND_OPR_PEND 0x00000004
  150. #define VSC9953_BITMASK(offset) ((BIT(offset)) - 1)
  151. #define VSC9953_ENC_BITFIELD(target, offset, width) \
  152. (((target) & VSC9953_BITMASK(width)) << (offset))
  153. #define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2))
  154. #define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset))
  155. #define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \
  156. VSC9953_IO_REG(target, (0x2 + (ri)))
  157. #define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
  158. VSC9953_IO_REG(target, (0x42 + (ri)))
  159. #define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2)
  160. #define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1)
  161. #define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
  162. VSC9953_ENC_BITFIELD(target, 0, 16)
  163. #define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0)
  164. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
  165. VSC9953_ENC_BITFIELD(target, 22, 3)
  166. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
  167. VSC9953_ENC_BITFIELD(target, 3, 16)
  168. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
  169. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
  170. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
  171. #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
  172. #define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
  173. VSC9953_IO_REG(target, (0x82 + (ri)))
  174. #define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \
  175. VSC9953_IO_REG(target, (0xc2 + (ri)))
  176. #define VSC9953_PORT_OFFSET 1
  177. #define VSC9953_IS1_CNT 256
  178. #define VSC9953_IS2_CNT 1024
  179. #define VSC9953_ES0_CNT 1024
  180. #define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32))
  181. #define ENTRY_WORDS_ES0 BITS_TO_DWORD(29)
  182. #define ENTRY_WORDS_IS1 BITS_TO_DWORD(376)
  183. #define ENTRY_WORDS_IS2 BITS_TO_DWORD(376)
  184. #define ES0_ACT_WIDTH BITS_TO_DWORD(91)
  185. #define ES0_CNT_WIDTH BITS_TO_DWORD(1)
  186. #define IS1_ACT_WIDTH BITS_TO_DWORD(320)
  187. #define IS1_CNT_WIDTH BITS_TO_DWORD(4)
  188. #define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
  189. #define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32)
  190. #define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
  191. #define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1)
  192. #define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
  193. /* TCAM entries */
  194. enum tcam_sel {
  195. TCAM_SEL_ENTRY = BIT(0),
  196. TCAM_SEL_ACTION = BIT(1),
  197. TCAM_SEL_COUNTER = BIT(2),
  198. TCAM_SEL_ALL = VSC9953_BITMASK(3),
  199. };
  200. enum tcam_cmd {
  201. TCAM_CMD_WRITE = 0,
  202. TCAM_CMD_READ = 1,
  203. TCAM_CMD_MOVE_UP = 2,
  204. TCAM_CMD_MOVE_DOWN = 3,
  205. TCAM_CMD_INITIALIZE = 4,
  206. };
  207. struct vsc9953_mdio_info {
  208. struct vsc9953_mii_mng *regs;
  209. char *name;
  210. };
  211. /* VSC9953 ANA structure */
  212. struct vsc9953_ana_port {
  213. u32 vlan_cfg;
  214. u32 drop_cfg;
  215. u32 qos_cfg;
  216. u32 vcap_cfg;
  217. u32 vcap_s1_key_cfg[3];
  218. u32 vcap_s2_cfg;
  219. u32 qos_pcp_dei_map_cfg[16];
  220. u32 cpu_fwd_cfg;
  221. u32 cpu_fwd_bpdu_cfg;
  222. u32 cpu_fwd_garp_cfg;
  223. u32 cpu_fwd_ccm_cfg;
  224. u32 port_cfg;
  225. u32 pol_cfg;
  226. u32 reserved[34];
  227. };
  228. struct vsc9953_ana_pol {
  229. u32 pol_pir_cfg;
  230. u32 pol_cir_cfg;
  231. u32 pol_mode_cfg;
  232. u32 pol_pir_state;
  233. u32 pol_cir_state;
  234. u32 reserved1[3];
  235. };
  236. struct vsc9953_ana_ana_tables {
  237. u32 entry_lim[11];
  238. u32 an_moved;
  239. u32 mach_data;
  240. u32 macl_data;
  241. u32 mac_access;
  242. u32 mact_indx;
  243. u32 vlan_access;
  244. u32 vlan_tidx;
  245. };
  246. struct vsc9953_ana_ana {
  247. u32 adv_learn;
  248. u32 vlan_mask;
  249. u32 reserved;
  250. u32 anag_efil;
  251. u32 an_events;
  252. u32 storm_limit_burst;
  253. u32 storm_limit_cfg[4];
  254. u32 isolated_prts;
  255. u32 community_ports;
  256. u32 auto_age;
  257. u32 mac_options;
  258. u32 learn_disc;
  259. u32 agen_ctrl;
  260. u32 mirror_ports;
  261. u32 emirror_ports;
  262. u32 flooding;
  263. u32 flooding_ipmc;
  264. u32 sflow_cfg[11];
  265. u32 port_mode[12];
  266. };
  267. #define PGID_DST_START 0
  268. #define PGID_AGGR_START 64
  269. #define PGID_SRC_START 80
  270. struct vsc9953_ana_pgid {
  271. u32 port_grp_id[91];
  272. };
  273. struct vsc9953_ana_pfc {
  274. u32 pfc_cfg;
  275. u32 reserved1[15];
  276. };
  277. struct vsc9953_ana_pol_misc {
  278. u32 pol_flowc[10];
  279. u32 reserved1[17];
  280. u32 pol_hyst;
  281. };
  282. struct vsc9953_ana_common {
  283. u32 aggr_cfg;
  284. u32 cpuq_cfg;
  285. u32 cpuq_8021_cfg;
  286. u32 dscp_cfg;
  287. u32 dscp_rewr_cfg;
  288. u32 vcap_rng_type_cfg;
  289. u32 vcap_rng_val_cfg;
  290. u32 discard_cfg;
  291. u32 fid_cfg;
  292. };
  293. struct vsc9953_analyzer {
  294. struct vsc9953_ana_port port[11];
  295. u32 reserved1[9536];
  296. struct vsc9953_ana_pol pol[164];
  297. struct vsc9953_ana_ana_tables ana_tables;
  298. u32 reserved2[14];
  299. struct vsc9953_ana_ana ana;
  300. u32 reserved3[21];
  301. struct vsc9953_ana_pgid port_id_tbl;
  302. u32 reserved4[549];
  303. struct vsc9953_ana_pfc pfc[10];
  304. struct vsc9953_ana_pol_misc pol_misc;
  305. u32 reserved5[196];
  306. struct vsc9953_ana_common common;
  307. };
  308. /* END VSC9953 ANA structure t*/
  309. /* VSC9953 DEV_GMII structure */
  310. struct vsc9953_dev_gmii_port_mode {
  311. u32 clock_cfg;
  312. u32 port_misc;
  313. u32 reserved1;
  314. u32 eee_cfg;
  315. };
  316. struct vsc9953_dev_gmii_mac_cfg_status {
  317. u32 mac_ena_cfg;
  318. u32 mac_mode_cfg;
  319. u32 mac_maxlen_cfg;
  320. u32 mac_tags_cfg;
  321. u32 mac_adv_chk_cfg;
  322. u32 mac_ifg_cfg;
  323. u32 mac_hdx_cfg;
  324. u32 mac_fc_mac_low_cfg;
  325. u32 mac_fc_mac_high_cfg;
  326. u32 mac_sticky;
  327. };
  328. struct vsc9953_dev_gmii {
  329. struct vsc9953_dev_gmii_port_mode port_mode;
  330. struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
  331. };
  332. /* END VSC9953 DEV_GMII structure */
  333. /* VSC9953 QSYS structure */
  334. struct vsc9953_qsys_hsch {
  335. u32 cir_cfg;
  336. u32 reserved1;
  337. u32 se_cfg;
  338. u32 se_dwrr_cfg[8];
  339. u32 cir_state;
  340. u32 reserved2[20];
  341. };
  342. struct vsc9953_qsys_sys {
  343. u32 port_mode[12];
  344. u32 switch_port_mode[11];
  345. u32 stat_cnt_cfg;
  346. u32 eee_cfg[10];
  347. u32 eee_thrs;
  348. u32 igr_no_sharing;
  349. u32 egr_no_sharing;
  350. u32 sw_status[11];
  351. u32 ext_cpu_cfg;
  352. u32 cpu_group_map;
  353. u32 reserved1[23];
  354. };
  355. struct vsc9953_qsys_qos_cfg {
  356. u32 red_profile[16];
  357. u32 res_qos_mode;
  358. };
  359. struct vsc9953_qsys_drop_cfg {
  360. u32 egr_drop_mode;
  361. };
  362. struct vsc9953_qsys_mmgt {
  363. u32 eq_cntrl;
  364. u32 reserved1;
  365. };
  366. struct vsc9953_qsys_hsch_misc {
  367. u32 hsch_misc_cfg;
  368. u32 reserved1[546];
  369. };
  370. struct vsc9953_qsys_res_ctrl {
  371. u32 res_cfg;
  372. u32 res_stat;
  373. };
  374. struct vsc9953_qsys_reg {
  375. struct vsc9953_qsys_hsch hsch[108];
  376. struct vsc9953_qsys_sys sys;
  377. struct vsc9953_qsys_qos_cfg qos_cfg;
  378. struct vsc9953_qsys_drop_cfg drop_cfg;
  379. struct vsc9953_qsys_mmgt mmgt;
  380. struct vsc9953_qsys_hsch_misc hsch_misc;
  381. struct vsc9953_qsys_res_ctrl res_ctrl[1024];
  382. };
  383. /* END VSC9953 QSYS structure */
  384. /* VSC9953 SYS structure */
  385. struct vsc9953_rx_cntrs {
  386. u32 c_rx_oct;
  387. u32 c_rx_uc;
  388. u32 c_rx_mc;
  389. u32 c_rx_bc;
  390. u32 c_rx_short;
  391. u32 c_rx_frag;
  392. u32 c_rx_jabber;
  393. u32 c_rx_crc;
  394. u32 c_rx_symbol_err;
  395. u32 c_rx_sz_64;
  396. u32 c_rx_sz_65_127;
  397. u32 c_rx_sz_128_255;
  398. u32 c_rx_sz_256_511;
  399. u32 c_rx_sz_512_1023;
  400. u32 c_rx_sz_1024_1526;
  401. u32 c_rx_sz_jumbo;
  402. u32 c_rx_pause;
  403. u32 c_rx_control;
  404. u32 c_rx_long;
  405. u32 c_rx_cat_drop;
  406. u32 c_rx_red_prio_0;
  407. u32 c_rx_red_prio_1;
  408. u32 c_rx_red_prio_2;
  409. u32 c_rx_red_prio_3;
  410. u32 c_rx_red_prio_4;
  411. u32 c_rx_red_prio_5;
  412. u32 c_rx_red_prio_6;
  413. u32 c_rx_red_prio_7;
  414. u32 c_rx_yellow_prio_0;
  415. u32 c_rx_yellow_prio_1;
  416. u32 c_rx_yellow_prio_2;
  417. u32 c_rx_yellow_prio_3;
  418. u32 c_rx_yellow_prio_4;
  419. u32 c_rx_yellow_prio_5;
  420. u32 c_rx_yellow_prio_6;
  421. u32 c_rx_yellow_prio_7;
  422. u32 c_rx_green_prio_0;
  423. u32 c_rx_green_prio_1;
  424. u32 c_rx_green_prio_2;
  425. u32 c_rx_green_prio_3;
  426. u32 c_rx_green_prio_4;
  427. u32 c_rx_green_prio_5;
  428. u32 c_rx_green_prio_6;
  429. u32 c_rx_green_prio_7;
  430. u32 reserved[20];
  431. };
  432. struct vsc9953_tx_cntrs {
  433. u32 c_tx_oct;
  434. u32 c_tx_uc;
  435. u32 c_tx_mc;
  436. u32 c_tx_bc;
  437. u32 c_tx_col;
  438. u32 c_tx_drop;
  439. u32 c_tx_pause;
  440. u32 c_tx_sz_64;
  441. u32 c_tx_sz_65_127;
  442. u32 c_tx_sz_128_255;
  443. u32 c_tx_sz_256_511;
  444. u32 c_tx_sz_512_1023;
  445. u32 c_tx_sz_1024_1526;
  446. u32 c_tx_sz_jumbo;
  447. u32 c_tx_yellow_prio_0;
  448. u32 c_tx_yellow_prio_1;
  449. u32 c_tx_yellow_prio_2;
  450. u32 c_tx_yellow_prio_3;
  451. u32 c_tx_yellow_prio_4;
  452. u32 c_tx_yellow_prio_5;
  453. u32 c_tx_yellow_prio_6;
  454. u32 c_tx_yellow_prio_7;
  455. u32 c_tx_green_prio_0;
  456. u32 c_tx_green_prio_1;
  457. u32 c_tx_green_prio_2;
  458. u32 c_tx_green_prio_3;
  459. u32 c_tx_green_prio_4;
  460. u32 c_tx_green_prio_5;
  461. u32 c_tx_green_prio_6;
  462. u32 c_tx_green_prio_7;
  463. u32 c_tx_aged;
  464. u32 reserved[33];
  465. };
  466. struct vsc9953_drop_cntrs {
  467. u32 c_dr_local;
  468. u32 c_dr_tail;
  469. u32 c_dr_yellow_prio_0;
  470. u32 c_dr_yellow_prio_1;
  471. u32 c_dr_yellow_prio_2;
  472. u32 c_dr_yellow_prio_3;
  473. u32 c_dr_yellow_prio_4;
  474. u32 c_dr_yellow_prio_5;
  475. u32 c_dr_yellow_prio_6;
  476. u32 c_dr_yellow_prio_7;
  477. u32 c_dr_green_prio_0;
  478. u32 c_dr_green_prio_1;
  479. u32 c_dr_green_prio_2;
  480. u32 c_dr_green_prio_3;
  481. u32 c_dr_green_prio_4;
  482. u32 c_dr_green_prio_5;
  483. u32 c_dr_green_prio_6;
  484. u32 c_dr_green_prio_7;
  485. u32 reserved[46];
  486. };
  487. struct vsc9953_sys_stat {
  488. struct vsc9953_rx_cntrs rx_cntrs;
  489. struct vsc9953_tx_cntrs tx_cntrs;
  490. struct vsc9953_drop_cntrs drop_cntrs;
  491. u32 reserved1[6];
  492. };
  493. struct vsc9953_sys_sys {
  494. u32 reset_cfg;
  495. u32 reserved1;
  496. u32 vlan_etype_cfg;
  497. u32 port_mode[12];
  498. u32 front_port_mode[10];
  499. u32 frame_aging;
  500. u32 stat_cfg;
  501. u32 reserved2[50];
  502. };
  503. struct vsc9953_sys_pause_cfg {
  504. u32 pause_cfg[11];
  505. u32 pause_tot_cfg;
  506. u32 tail_drop_level[11];
  507. u32 tot_tail_drop_lvl;
  508. u32 mac_fc_cfg[10];
  509. };
  510. struct vsc9953_sys_mmgt {
  511. u16 free_cnt;
  512. };
  513. struct vsc9953_system_reg {
  514. struct vsc9953_sys_stat stat;
  515. struct vsc9953_sys_sys sys;
  516. struct vsc9953_sys_pause_cfg pause_cfg;
  517. struct vsc9953_sys_mmgt mmgt;
  518. };
  519. /* END VSC9953 SYS structure */
  520. /* VSC9953 REW structure */
  521. struct vsc9953_rew_port {
  522. u32 port_vlan_cfg;
  523. u32 port_tag_cfg;
  524. u32 port_port_cfg;
  525. u32 port_dscp_cfg;
  526. u32 port_pcp_dei_qos_map_cfg[16];
  527. u32 reserved[12];
  528. };
  529. struct vsc9953_rew_common {
  530. u32 reserve[4];
  531. u32 dscp_remap_dp1_cfg[64];
  532. u32 dscp_remap_cfg[64];
  533. };
  534. struct vsc9953_rew_reg {
  535. struct vsc9953_rew_port port[12];
  536. struct vsc9953_rew_common common;
  537. };
  538. /* END VSC9953 REW structure */
  539. /* VSC9953 DEVCPU_GCB structure */
  540. struct vsc9953_chip_regs {
  541. u32 chipd_id;
  542. u32 gpr;
  543. u32 soft_rst;
  544. };
  545. struct vsc9953_gpio {
  546. u32 gpio_out_set[10];
  547. u32 gpio_out_clr[10];
  548. u32 gpio_out[10];
  549. u32 gpio_in[10];
  550. };
  551. struct vsc9953_mii_mng {
  552. u32 miimstatus;
  553. u32 reserved1;
  554. u32 miimcmd;
  555. u32 miimdata;
  556. u32 miimcfg;
  557. u32 miimscan_0;
  558. u32 miimscan_1;
  559. u32 miiscan_lst_rslts;
  560. u32 miiscan_lst_rslts_valid;
  561. };
  562. struct vsc9953_mii_read_scan {
  563. u32 mii_scan_results_sticky[2];
  564. };
  565. struct vsc9953_devcpu_gcb {
  566. struct vsc9953_chip_regs chip_regs;
  567. struct vsc9953_gpio gpio;
  568. struct vsc9953_mii_mng mii_mng[2];
  569. struct vsc9953_mii_read_scan mii_read_scan;
  570. };
  571. /* END VSC9953 DEVCPU_GCB structure */
  572. /* VSC9953 IS* structure */
  573. struct vsc9953_vcap_core_cfg {
  574. u32 vcap_update_ctrl;
  575. u32 vcap_mv_cfg;
  576. };
  577. struct vsc9953_vcap {
  578. struct vsc9953_vcap_core_cfg vcap_core_cfg;
  579. };
  580. /* END VSC9953 IS* structure */
  581. #define VSC9953_PORT_INFO_INITIALIZER(idx) \
  582. { \
  583. .enabled = 0, \
  584. .phyaddr = 0, \
  585. .index = idx, \
  586. .phy_regs = NULL, \
  587. .enet_if = PHY_INTERFACE_MODE_NONE, \
  588. .bus = NULL, \
  589. .phydev = NULL, \
  590. }
  591. /* Structure to describe a VSC9953 port */
  592. struct vsc9953_port_info {
  593. u8 enabled;
  594. u8 phyaddr;
  595. int index;
  596. void *phy_regs;
  597. phy_interface_t enet_if;
  598. struct mii_dev *bus;
  599. struct phy_device *phydev;
  600. };
  601. /* Structure to describe a VSC9953 switch */
  602. struct vsc9953_info {
  603. struct vsc9953_port_info port[VSC9953_MAX_PORTS];
  604. };
  605. void vsc9953_init(bd_t *bis);
  606. void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
  607. void vsc9953_port_info_set_phy_address(int port_no, int address);
  608. void vsc9953_port_enable(int port_no);
  609. void vsc9953_port_disable(int port_no);
  610. void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
  611. #endif /* _VSC9953_H_ */