virtex2.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2002
  4. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  5. * Keith Outwater, keith_outwater@mvis.com
  6. */
  7. #ifndef _VIRTEX2_H_
  8. #define _VIRTEX2_H_
  9. #include <xilinx.h>
  10. /*
  11. * Slave SelectMap or Serial Implementation function table.
  12. */
  13. typedef struct {
  14. xilinx_pre_fn pre;
  15. xilinx_pgm_fn pgm;
  16. xilinx_init_fn init;
  17. xilinx_err_fn err;
  18. xilinx_done_fn done;
  19. xilinx_clk_fn clk;
  20. xilinx_cs_fn cs;
  21. xilinx_wr_fn wr;
  22. xilinx_rdata_fn rdata;
  23. xilinx_wdata_fn wdata;
  24. xilinx_bwr_fn wbulkdata;
  25. xilinx_busy_fn busy;
  26. xilinx_abort_fn abort;
  27. xilinx_post_fn post;
  28. } xilinx_virtex2_slave_fns;
  29. #if defined(CONFIG_FPGA_VIRTEX2)
  30. extern struct xilinx_fpga_op virtex2_op;
  31. # define FPGA_VIRTEX2_OPS &virtex2_op
  32. #else
  33. # define FPGA_VIRTEX2_OPS NULL
  34. #endif
  35. /* Device Image Sizes (in bytes)
  36. *********************************************************************/
  37. #define XILINX_XC2V40_SIZE (338208 / 8)
  38. #define XILINX_XC2V80_SIZE (597408 / 8)
  39. #define XILINX_XC2V250_SIZE (1591584 / 8)
  40. #define XILINX_XC2V500_SIZE (2557857 / 8)
  41. #define XILINX_XC2V1000_SIZE (3749408 / 8)
  42. #define XILINX_XC2V1500_SIZE (5166240 / 8)
  43. #define XILINX_XC2V2000_SIZE (6808352 / 8)
  44. #define XILINX_XC2V3000_SIZE (9589408 / 8)
  45. #define XILINX_XC2V4000_SIZE (14220192 / 8)
  46. #define XILINX_XC2V6000_SIZE (19752096 / 8)
  47. #define XILINX_XC2V8000_SIZE (26185120 / 8)
  48. #define XILINX_XC2V10000_SIZE (33519264 / 8)
  49. /* Descriptor Macros
  50. *********************************************************************/
  51. #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
  52. { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
  53. FPGA_VIRTEX2_OPS }
  54. #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
  55. { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
  56. FPGA_VIRTEX2_OPS }
  57. #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
  58. { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
  59. FPGA_VIRTEX2_OPS }
  60. #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
  61. { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
  62. FPGA_VIRTEX2_OPS }
  63. #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
  64. { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
  65. FPGA_VIRTEX2_OPS }
  66. #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
  67. { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
  68. FPGA_VIRTEX2_OPS }
  69. #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
  70. { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
  71. FPGA_VIRTEX2_OPS }
  72. #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
  73. { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
  74. FPGA_VIRTEX2_OPS }
  75. #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
  76. { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
  77. FPGA_VIRTEX2_OPS }
  78. #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
  79. { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
  80. FPGA_VIRTEX2_OPS }
  81. #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
  82. { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
  83. FPGA_VIRTEX2_OPS }
  84. #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
  85. { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
  86. FPGA_VIRTEX2_OPS }
  87. #endif /* _VIRTEX2_H_ */