fotg210.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Faraday USB 2.0 OTG Controller
  4. *
  5. * (C) Copyright 2010 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. */
  8. #ifndef _FOTG210_H
  9. #define _FOTG210_H
  10. struct fotg210_regs {
  11. /* USB Host Controller */
  12. struct {
  13. uint32_t data[4];
  14. } hccr; /* 0x00 - 0x0f: hccr */
  15. struct {
  16. uint32_t data[9];
  17. } hcor; /* 0x10 - 0x33: hcor */
  18. uint32_t rsvd1[3];
  19. uint32_t miscr; /* 0x40: Miscellaneous Register */
  20. uint32_t rsvd2[15];
  21. /* USB OTG Controller */
  22. uint32_t otgcsr;/* 0x80: OTG Control Status Register */
  23. uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
  24. uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
  25. uint32_t rsvd3[13];
  26. uint32_t isr; /* 0xC0: Global Interrupt Status Register */
  27. uint32_t imr; /* 0xC4: Global Interrupt Mask Register */
  28. uint32_t rsvd4[14];
  29. /* USB Device Controller */
  30. uint32_t dev_ctrl;/* 0x100: Device Control Register */
  31. uint32_t dev_addr;/* 0x104: Device Address Register */
  32. uint32_t dev_test;/* 0x108: Device Test Register */
  33. uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
  34. uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
  35. uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
  36. uint32_t rsvd5[2];
  37. uint32_t cxfifo;/* 0x120: CX FIFO Register */
  38. uint32_t idle; /* 0x124: IDLE Counter Register */
  39. uint32_t rsvd6[2];
  40. uint32_t gimr; /* 0x130: Group Interrupt Mask Register */
  41. uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
  42. uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
  43. uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
  44. uint32_t gisr; /* 0x140: Group Interrupt Status Register */
  45. uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
  46. uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
  47. uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
  48. uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
  49. uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
  50. uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
  51. uint32_t rsvd7[1];
  52. uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
  53. uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
  54. uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
  55. uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
  56. uint32_t fifomap;/* 0x1a8: FIFO Map Register */
  57. uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
  58. uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
  59. uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
  60. uint32_t rsvd8[1];
  61. uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
  62. uint32_t dma_addr; /* 0x1cc: DMA Address Register */
  63. uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */
  64. };
  65. /* Miscellaneous Register */
  66. #define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */
  67. #define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */
  68. #define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */
  69. #define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
  70. /* OTG Control Status Register */
  71. #define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */
  72. #define OTGCSR_SPD_LOW (1 << 22)
  73. #define OTGCSR_SPD_FULL (0 << 22)
  74. #define OTGCSR_SPD_MASK (3 << 22)
  75. #define OTGCSR_SPD_SHIFT 22
  76. #define OTGCSR_SPD(x) (((x) >> 22) & 0x03)
  77. #define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */
  78. #define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */
  79. #define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */
  80. #define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */
  81. #define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */
  82. #define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */
  83. #define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */
  84. #define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */
  85. #define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/
  86. #define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/
  87. #define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/
  88. #define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/
  89. #define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/
  90. #define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/
  91. #define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */
  92. #define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */
  93. #define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */
  94. #define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */
  95. #define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */
  96. #define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */
  97. #define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */
  98. #define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */
  99. #define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */
  100. /* OTG Interrupt Status Register */
  101. #define OTGISR_APRM (1 << 12) /* Mini-A plug removed */
  102. #define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */
  103. #define OTGISR_OVD (1 << 10) /* over-current detected */
  104. #define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */
  105. #define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */
  106. #define OTGISR_BSESSEND (1 << 6) /* B-device Session End */
  107. #define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */
  108. #define OTGISR_ASRP (1 << 4) /* A-device SRP detected */
  109. #define OTGISR_BSRP (1 << 0) /* B-device SRP complete */
  110. /* OTG Interrupt Enable Register */
  111. #define OTGIER_APRM (1 << 12) /* Mini-A plug removed */
  112. #define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */
  113. #define OTGIER_OVD (1 << 10) /* over-current detected */
  114. #define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */
  115. #define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */
  116. #define OTGIER_BSESSEND (1 << 6) /* B-device Session End */
  117. #define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */
  118. #define OTGIER_ASRP (1 << 4) /* A-device SRP detected */
  119. #define OTGIER_BSRP (1 << 0) /* B-device SRP complete */
  120. /* Global Interrupt Status Register (W1C) */
  121. #define ISR_HOST (1 << 2) /* USB Host interrupt */
  122. #define ISR_OTG (1 << 1) /* USB OTG interrupt */
  123. #define ISR_DEV (1 << 0) /* USB Device interrupt */
  124. #define ISR_MASK 0x07
  125. /* Global Interrupt Mask Register */
  126. #define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */
  127. #define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */
  128. #define IMR_HOST (1 << 2) /* USB Host interrupt */
  129. #define IMR_OTG (1 << 1) /* USB OTG interrupt */
  130. #define IMR_DEV (1 << 0) /* USB Device interrupt */
  131. #define IMR_MASK 0x0f
  132. /* Device Control Register */
  133. #define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */
  134. #define DEVCTRL_HS (1 << 6) /* High Speed Mode */
  135. #define DEVCTRL_FS (0 << 6) /* Full Speed Mode */
  136. #define DEVCTRL_EN (1 << 5) /* Chip Enable */
  137. #define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */
  138. #define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */
  139. #define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */
  140. #define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */
  141. #define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */
  142. /* Device Address Register */
  143. #define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */
  144. #define DEVADDR_ADDR(x) ((x) & 0x7f)
  145. #define DEVADDR_ADDR_MASK 0x7f
  146. /* Device Test Register */
  147. #define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */
  148. #define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */
  149. #define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */
  150. #define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */
  151. #define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */
  152. #define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */
  153. #define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */
  154. /* SOF Frame Number Register */
  155. #define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
  156. #define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */
  157. /* SOF Mask Timer Register */
  158. #define SOFMTR_TMR(x) ((x) & 0xffff)
  159. /* PHY Test Mode Selector Register */
  160. #define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */
  161. #define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */
  162. #define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */
  163. #define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */
  164. #define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */
  165. /* CX FIFO Register */
  166. #define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */
  167. #define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */
  168. #define CXFIFO_FIFOE_FIFO0 (1 << 8)
  169. #define CXFIFO_FIFOE_FIFO1 (1 << 9)
  170. #define CXFIFO_FIFOE_FIFO2 (1 << 10)
  171. #define CXFIFO_FIFOE_FIFO3 (1 << 11)
  172. #define CXFIFO_FIFOE_MASK (0x0f << 8)
  173. #define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */
  174. #define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */
  175. #define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */
  176. #define CXFIFO_CXSTALL (1 << 2) /* CX Stall */
  177. #define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */
  178. #define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */
  179. /* IDLE Counter Register */
  180. #define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */
  181. /* Group Interrupt Mask(Disable) Register */
  182. #define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */
  183. #define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */
  184. #define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */
  185. #define GIMR_MASK 0x07
  186. /* Group Interrupt Mask(Disable) Register 0 (CX) */
  187. #define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */
  188. #define GIMR0_CXERR (1 << 4) /* CX command error interrupt */
  189. #define GIMR0_CXEND (1 << 3) /* CX command end interrupt */
  190. #define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
  191. #define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
  192. #define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
  193. #define GIMR0_MASK 0x3f
  194. /* Group Interrupt Mask(Disable) Register 1 (FIFO) */
  195. #define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */
  196. #define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x)
  197. #define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */
  198. #define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */
  199. #define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x))
  200. #define GIMR1_MASK 0xf00ff
  201. /* Group Interrupt Mask(Disable) Register 2 (Device) */
  202. #define GIMR2_WAKEUP (1 << 10) /* Device waked up */
  203. #define GIMR2_IDLE (1 << 9) /* Device idle */
  204. #define GIMR2_DMAERR (1 << 8) /* DMA error */
  205. #define GIMR2_DMAFIN (1 << 7) /* DMA finished */
  206. #define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
  207. #define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
  208. #define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
  209. #define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
  210. #define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */
  211. #define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
  212. #define GIMR2_RESET (1 << 0) /* Reset Interrupt */
  213. #define GIMR2_MASK 0x7ff
  214. /* Group Interrupt Status Register */
  215. #define GISR_GRP2 (1 << 2) /* Interrupt group 2 */
  216. #define GISR_GRP1 (1 << 1) /* Interrupt group 1 */
  217. #define GISR_GRP0 (1 << 0) /* Interrupt group 0 */
  218. /* Group Interrupt Status Register 0 (CX) */
  219. #define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */
  220. #define GISR0_CXERR (1 << 4) /* CX command error interrupt */
  221. #define GISR0_CXEND (1 << 3) /* CX command end interrupt */
  222. #define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
  223. #define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
  224. #define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
  225. /* Group Interrupt Status Register 1 (FIFO) */
  226. #define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */
  227. #define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */
  228. #define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */
  229. #define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */
  230. /* Group Interrupt Status Register 2 (Device) */
  231. #define GISR2_WAKEUP (1 << 10) /* Device waked up */
  232. #define GISR2_IDLE (1 << 9) /* Device idle */
  233. #define GISR2_DMAERR (1 << 8) /* DMA error */
  234. #define GISR2_DMAFIN (1 << 7) /* DMA finished */
  235. #define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
  236. #define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
  237. #define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
  238. #define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
  239. #define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */
  240. #define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
  241. #define GISR2_RESET (1 << 0) /* Reset Interrupt */
  242. /* Receive Zero-Length-Packet Register */
  243. #define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
  244. /* Transfer Zero-Length-Packet Register */
  245. #define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
  246. /* ISOC Error/Abort Status Register */
  247. #define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
  248. /* IN Endpoint Register */
  249. #define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */
  250. #define IEP_TNRHB(x) (((x) & 0x03) << 13) \
  251. /* Transaction Number for High-Bandwidth EP(ISOC) */
  252. #define IEP_RESET (1 << 12) /* Reset Toggle Sequence */
  253. #define IEP_STALL (1 << 11) /* Stall */
  254. #define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
  255. /* OUT Endpoint Register */
  256. #define OEP_RESET (1 << 12) /* Reset Toggle Sequence */
  257. #define OEP_STALL (1 << 11) /* Stall */
  258. #define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
  259. /* Endpoint Map Register (EP1 ~ EP4) */
  260. #define EPMAP14_SET_IN(ep, fifo) \
  261. ((fifo) & 3) << (((ep) - 1) << 3 + 0)
  262. #define EPMAP14_SET_OUT(ep, fifo) \
  263. ((fifo) & 3) << (((ep) - 1) << 3 + 4)
  264. #define EPMAP14_SET(ep, in, out) \
  265. do { \
  266. EPMAP14_SET_IN(ep, in); \
  267. EPMAP14_SET_OUT(ep, out); \
  268. } while (0)
  269. #define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
  270. /* Endpoint Map Register (EP5 ~ EP8) */
  271. #define EPMAP58_SET_IN(ep, fifo) \
  272. ((fifo) & 3) << (((ep) - 5) << 3 + 0)
  273. #define EPMAP58_SET_OUT(ep, fifo) \
  274. ((fifo) & 3) << (((ep) - 5) << 3 + 4)
  275. #define EPMAP58_SET(ep, in, out) \
  276. do { \
  277. EPMAP58_SET_IN(ep, in); \
  278. EPMAP58_SET_OUT(ep, out); \
  279. } while (0)
  280. #define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */
  281. /* FIFO Map Register */
  282. #define FIFOMAP_BIDIR (2 << 4)
  283. #define FIFOMAP_IN (1 << 4)
  284. #define FIFOMAP_OUT (0 << 4)
  285. #define FIFOMAP_DIR_MASK 0x30
  286. #define FIFOMAP_EP(x) ((x) & 0x0f)
  287. #define FIFOMAP_EP_MASK 0x0f
  288. #define FIFOMAP_CFG_MASK 0x3f
  289. #define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
  290. #define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
  291. /* FIFO Configuration Register */
  292. #define FIFOCFG_EN (1 << 5)
  293. #define FIFOCFG_BLKSZ_1024 (1 << 4)
  294. #define FIFOCFG_BLKSZ_512 (0 << 4)
  295. #define FIFOCFG_3BLK (2 << 2)
  296. #define FIFOCFG_2BLK (1 << 2)
  297. #define FIFOCFG_1BLK (0 << 2)
  298. #define FIFOCFG_NBLK_MASK 3
  299. #define FIFOCFG_NBLK_SHIFT 2
  300. #define FIFOCFG_INTR (3 << 0)
  301. #define FIFOCFG_BULK (2 << 0)
  302. #define FIFOCFG_ISOC (1 << 0)
  303. #define FIFOCFG_RSVD (0 << 0) /* Reserved */
  304. #define FIFOCFG_TYPE_MASK 3
  305. #define FIFOCFG_TYPE_SHIFT 0
  306. #define FIFOCFG_CFG_MASK 0x3f
  307. #define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
  308. /* FIFO Control Status Register */
  309. #define FIFOCSR_RESET (1 << 12) /* FIFO Reset */
  310. #define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */
  311. /* DMA Target FIFO Register */
  312. #define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */
  313. #define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */
  314. /* DMA Control Register */
  315. #define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */
  316. #define DMACTRL_LEN_SHIFT 8
  317. #define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */
  318. #define DMACTRL_ABORT (1 << 3) /* DMA abort */
  319. #define DMACTRL_IO2IO (1 << 2) /* IO to IO */
  320. #define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */
  321. #define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */
  322. #define DMACTRL_START (1 << 0) /* DMA start */
  323. #endif