designware_udc.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef __DW_UDC_H
  7. #define __DW_UDC_H
  8. /*
  9. * Defines for USBD
  10. *
  11. * The udc_ahb controller has three AHB slaves:
  12. *
  13. * 1. THe UDC registers
  14. * 2. The plug detect
  15. * 3. The RX/TX FIFO
  16. */
  17. #define MAX_ENDPOINTS 16
  18. struct udc_endp_regs {
  19. u32 endp_cntl;
  20. u32 endp_status;
  21. u32 endp_bsorfn;
  22. u32 endp_maxpacksize;
  23. u32 reserved_1;
  24. u32 endp_desc_point;
  25. u32 reserved_2;
  26. u32 write_done;
  27. };
  28. /* Endpoint Control Register definitions */
  29. #define ENDP_CNTL_STALL 0x00000001
  30. #define ENDP_CNTL_FLUSH 0x00000002
  31. #define ENDP_CNTL_SNOOP 0x00000004
  32. #define ENDP_CNTL_POLL 0x00000008
  33. #define ENDP_CNTL_CONTROL 0x00000000
  34. #define ENDP_CNTL_ISO 0x00000010
  35. #define ENDP_CNTL_BULK 0x00000020
  36. #define ENDP_CNTL_INT 0x00000030
  37. #define ENDP_CNTL_NAK 0x00000040
  38. #define ENDP_CNTL_SNAK 0x00000080
  39. #define ENDP_CNTL_CNAK 0x00000100
  40. #define ENDP_CNTL_RRDY 0x00000200
  41. /* Endpoint Satus Register definitions */
  42. #define ENDP_STATUS_PIDMSK 0x0000000f
  43. #define ENDP_STATUS_OUTMSK 0x00000030
  44. #define ENDP_STATUS_OUT_NONE 0x00000000
  45. #define ENDP_STATUS_OUT_DATA 0x00000010
  46. #define ENDP_STATUS_OUT_SETUP 0x00000020
  47. #define ENDP_STATUS_IN 0x00000040
  48. #define ENDP_STATUS_BUFFNAV 0x00000080
  49. #define ENDP_STATUS_FATERR 0x00000100
  50. #define ENDP_STATUS_HOSTBUSERR 0x00000200
  51. #define ENDP_STATUS_TDC 0x00000400
  52. #define ENDP_STATUS_RXPKTMSK 0x003ff800
  53. struct udc_regs {
  54. struct udc_endp_regs in_regs[MAX_ENDPOINTS];
  55. struct udc_endp_regs out_regs[MAX_ENDPOINTS];
  56. u32 dev_conf;
  57. u32 dev_cntl;
  58. u32 dev_stat;
  59. u32 dev_int;
  60. u32 dev_int_mask;
  61. u32 endp_int;
  62. u32 endp_int_mask;
  63. u32 reserved_3[0x39];
  64. u32 reserved_4; /* offset 0x500 */
  65. u32 udc_endp_reg[MAX_ENDPOINTS];
  66. };
  67. /* Device Configuration Register definitions */
  68. #define DEV_CONF_HS_SPEED 0x00000000
  69. #define DEV_CONF_LS_SPEED 0x00000002
  70. #define DEV_CONF_FS_SPEED 0x00000003
  71. #define DEV_CONF_REMWAKEUP 0x00000004
  72. #define DEV_CONF_SELFPOW 0x00000008
  73. #define DEV_CONF_SYNCFRAME 0x00000010
  74. #define DEV_CONF_PHYINT_8 0x00000020
  75. #define DEV_CONF_PHYINT_16 0x00000000
  76. #define DEV_CONF_UTMI_BIDIR 0x00000040
  77. #define DEV_CONF_STATUS_STALL 0x00000080
  78. /* Device Control Register definitions */
  79. #define DEV_CNTL_RESUME 0x00000001
  80. #define DEV_CNTL_TFFLUSH 0x00000002
  81. #define DEV_CNTL_RXDMAEN 0x00000004
  82. #define DEV_CNTL_TXDMAEN 0x00000008
  83. #define DEV_CNTL_DESCRUPD 0x00000010
  84. #define DEV_CNTL_BIGEND 0x00000020
  85. #define DEV_CNTL_BUFFILL 0x00000040
  86. #define DEV_CNTL_TSHLDEN 0x00000080
  87. #define DEV_CNTL_BURSTEN 0x00000100
  88. #define DEV_CNTL_DMAMODE 0x00000200
  89. #define DEV_CNTL_SOFTDISCONNECT 0x00000400
  90. #define DEV_CNTL_SCALEDOWN 0x00000800
  91. #define DEV_CNTL_BURSTLENU 0x00010000
  92. #define DEV_CNTL_BURSTLENMSK 0x00ff0000
  93. #define DEV_CNTL_TSHLDLENU 0x01000000
  94. #define DEV_CNTL_TSHLDLENMSK 0xff000000
  95. /* Device Status Register definitions */
  96. #define DEV_STAT_CFG 0x0000000f
  97. #define DEV_STAT_INTF 0x000000f0
  98. #define DEV_STAT_ALT 0x00000f00
  99. #define DEV_STAT_SUSP 0x00001000
  100. #define DEV_STAT_ENUM 0x00006000
  101. #define DEV_STAT_ENUM_SPEED_HS 0x00000000
  102. #define DEV_STAT_ENUM_SPEED_FS 0x00002000
  103. #define DEV_STAT_ENUM_SPEED_LS 0x00004000
  104. #define DEV_STAT_RXFIFO_EMPTY 0x00008000
  105. #define DEV_STAT_PHY_ERR 0x00010000
  106. #define DEV_STAT_TS 0xf0000000
  107. /* Device Interrupt Register definitions */
  108. #define DEV_INT_MSK 0x0000007f
  109. #define DEV_INT_SETCFG 0x00000001
  110. #define DEV_INT_SETINTF 0x00000002
  111. #define DEV_INT_INACTIVE 0x00000004
  112. #define DEV_INT_USBRESET 0x00000008
  113. #define DEV_INT_SUSPUSB 0x00000010
  114. #define DEV_INT_SOF 0x00000020
  115. #define DEV_INT_ENUM 0x00000040
  116. /* Endpoint Interrupt Register definitions */
  117. #define ENDP0_INT_CTRLIN 0x00000001
  118. #define ENDP1_INT_BULKIN 0x00000002
  119. #define ENDP_INT_NONISOIN_MSK 0x0000AAAA
  120. #define ENDP2_INT_BULKIN 0x00000004
  121. #define ENDP0_INT_CTRLOUT 0x00010000
  122. #define ENDP1_INT_BULKOUT 0x00020000
  123. #define ENDP2_INT_BULKOUT 0x00040000
  124. #define ENDP_INT_NONISOOUT_MSK 0x55540000
  125. /* Endpoint Register definitions */
  126. #define ENDP_EPDIR_OUT 0x00000000
  127. #define ENDP_EPDIR_IN 0x00000010
  128. #define ENDP_EPTYPE_CNTL 0x0
  129. #define ENDP_EPTYPE_ISO 0x1
  130. #define ENDP_EPTYPE_BULK 0x2
  131. #define ENDP_EPTYPE_INT 0x3
  132. /*
  133. * Defines for Plug Detect
  134. */
  135. struct plug_regs {
  136. u32 plug_state;
  137. u32 plug_pending;
  138. };
  139. /* Plug State Register definitions */
  140. #define PLUG_STATUS_EN 0x1
  141. #define PLUG_STATUS_ATTACHED 0x2
  142. #define PLUG_STATUS_PHY_RESET 0x4
  143. #define PLUG_STATUS_PHY_MODE 0x8
  144. /*
  145. * Defines for UDC FIFO (Slave Mode)
  146. */
  147. struct udcfifo_regs {
  148. u32 *fifo_p;
  149. };
  150. /*
  151. * UDC endpoint definitions
  152. */
  153. #define UDC_EP0 0
  154. #define UDC_EP1 1
  155. #define UDC_EP2 2
  156. #define UDC_EP3 3
  157. #endif /* __DW_UDC_H */