tsec.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * tsec.h
  4. *
  5. * Driver for the Motorola Triple Speed Ethernet Controller
  6. *
  7. * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
  8. * (C) Copyright 2003, Motorola, Inc.
  9. * maintained by Xianghua Xiao (x.xiao@motorola.com)
  10. * author Andy Fleming
  11. */
  12. #ifndef __TSEC_H
  13. #define __TSEC_H
  14. #include <net.h>
  15. #include <config.h>
  16. #include <phy.h>
  17. #define TSEC_MDIO_REGS_OFFSET 0x520
  18. #ifndef CONFIG_DM_ETH
  19. #ifdef CONFIG_ARCH_LS1021A
  20. #define TSEC_SIZE 0x40000
  21. #define TSEC_MDIO_OFFSET 0x40000
  22. #else
  23. #define TSEC_SIZE 0x01000
  24. #define TSEC_MDIO_OFFSET 0x01000
  25. #endif
  26. #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
  27. #define TSEC_GET_REGS(num, offset) \
  28. (struct tsec __iomem *)\
  29. (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
  30. #define TSEC_GET_REGS_BASE(num) \
  31. TSEC_GET_REGS((num), TSEC_SIZE)
  32. #define TSEC_GET_MDIO_REGS(num, offset) \
  33. (struct tsec_mii_mng __iomem *)\
  34. (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
  35. #define TSEC_GET_MDIO_REGS_BASE(num) \
  36. TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
  37. #define DEFAULT_MII_NAME "FSL_MDIO"
  38. #define STD_TSEC_INFO(num) \
  39. { \
  40. .regs = TSEC_GET_REGS_BASE(num), \
  41. .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
  42. .devname = CONFIG_TSEC##num##_NAME, \
  43. .phyaddr = TSEC##num##_PHY_ADDR, \
  44. .flags = TSEC##num##_FLAGS, \
  45. .mii_devname = DEFAULT_MII_NAME \
  46. }
  47. #define SET_STD_TSEC_INFO(x, num) \
  48. { \
  49. x.regs = TSEC_GET_REGS_BASE(num); \
  50. x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
  51. x.devname = CONFIG_TSEC##num##_NAME; \
  52. x.phyaddr = TSEC##num##_PHY_ADDR; \
  53. x.flags = TSEC##num##_FLAGS;\
  54. x.mii_devname = DEFAULT_MII_NAME;\
  55. }
  56. #endif /* CONFIG_DM_ETH */
  57. #define MAC_ADDR_LEN 6
  58. /* #define TSEC_TIMEOUT 1000000 */
  59. #define TSEC_TIMEOUT 1000
  60. #define TOUT_LOOP 1000000
  61. /* TBI register addresses */
  62. #define TBI_CR 0x00
  63. #define TBI_SR 0x01
  64. #define TBI_ANA 0x04
  65. #define TBI_ANLPBPA 0x05
  66. #define TBI_ANEX 0x06
  67. #define TBI_TBICON 0x11
  68. /* TBI MDIO register bit fields*/
  69. #define TBICON_CLK_SELECT 0x0020
  70. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  71. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  72. #define TBIANA_HALF_DUPLEX 0x0040
  73. #define TBIANA_FULL_DUPLEX 0x0020
  74. #define TBICR_PHY_RESET 0x8000
  75. #define TBICR_ANEG_ENABLE 0x1000
  76. #define TBICR_RESTART_ANEG 0x0200
  77. #define TBICR_FULL_DUPLEX 0x0100
  78. #define TBICR_SPEED1_SET 0x0040
  79. /* MAC register bits */
  80. #define MACCFG1_SOFT_RESET 0x80000000
  81. #define MACCFG1_RESET_RX_MC 0x00080000
  82. #define MACCFG1_RESET_TX_MC 0x00040000
  83. #define MACCFG1_RESET_RX_FUN 0x00020000
  84. #define MACCFG1_RESET_TX_FUN 0x00010000
  85. #define MACCFG1_LOOPBACK 0x00000100
  86. #define MACCFG1_RX_FLOW 0x00000020
  87. #define MACCFG1_TX_FLOW 0x00000010
  88. #define MACCFG1_SYNCD_RX_EN 0x00000008
  89. #define MACCFG1_RX_EN 0x00000004
  90. #define MACCFG1_SYNCD_TX_EN 0x00000002
  91. #define MACCFG1_TX_EN 0x00000001
  92. #define MACCFG2_INIT_SETTINGS 0x00007205
  93. #define MACCFG2_FULL_DUPLEX 0x00000001
  94. #define MACCFG2_IF 0x00000300
  95. #define MACCFG2_GMII 0x00000200
  96. #define MACCFG2_MII 0x00000100
  97. #define ECNTRL_INIT_SETTINGS 0x00001000
  98. #define ECNTRL_TBI_MODE 0x00000020
  99. #define ECNTRL_REDUCED_MODE 0x00000010
  100. #define ECNTRL_R100 0x00000008
  101. #define ECNTRL_REDUCED_MII_MODE 0x00000004
  102. #define ECNTRL_SGMII_MODE 0x00000002
  103. #ifndef CONFIG_SYS_TBIPA_VALUE
  104. # define CONFIG_SYS_TBIPA_VALUE 0x1f
  105. #endif
  106. #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
  107. #define MINFLR_INIT_SETTINGS 0x00000040
  108. #define DMACTRL_INIT_SETTINGS 0x000000c3
  109. #define DMACTRL_GRS 0x00000010
  110. #define DMACTRL_GTS 0x00000008
  111. #define DMACTRL_LE 0x00008000
  112. #define TSTAT_CLEAR_THALT 0x80000000
  113. #define RSTAT_CLEAR_RHALT 0x00800000
  114. #define IEVENT_INIT_CLEAR 0xffffffff
  115. #define IEVENT_BABR 0x80000000
  116. #define IEVENT_RXC 0x40000000
  117. #define IEVENT_BSY 0x20000000
  118. #define IEVENT_EBERR 0x10000000
  119. #define IEVENT_MSRO 0x04000000
  120. #define IEVENT_GTSC 0x02000000
  121. #define IEVENT_BABT 0x01000000
  122. #define IEVENT_TXC 0x00800000
  123. #define IEVENT_TXE 0x00400000
  124. #define IEVENT_TXB 0x00200000
  125. #define IEVENT_TXF 0x00100000
  126. #define IEVENT_IE 0x00080000
  127. #define IEVENT_LC 0x00040000
  128. #define IEVENT_CRL 0x00020000
  129. #define IEVENT_XFUN 0x00010000
  130. #define IEVENT_RXB0 0x00008000
  131. #define IEVENT_GRSC 0x00000100
  132. #define IEVENT_RXF0 0x00000080
  133. #define IMASK_INIT_CLEAR 0x00000000
  134. #define IMASK_TXEEN 0x00400000
  135. #define IMASK_TXBEN 0x00200000
  136. #define IMASK_TXFEN 0x00100000
  137. #define IMASK_RXFEN0 0x00000080
  138. /* Default Attribute fields */
  139. #define ATTR_INIT_SETTINGS 0x000000c0
  140. #define ATTRELI_INIT_SETTINGS 0x00000000
  141. /* TxBD status field bits */
  142. #define TXBD_READY 0x8000
  143. #define TXBD_PADCRC 0x4000
  144. #define TXBD_WRAP 0x2000
  145. #define TXBD_INTERRUPT 0x1000
  146. #define TXBD_LAST 0x0800
  147. #define TXBD_CRC 0x0400
  148. #define TXBD_DEF 0x0200
  149. #define TXBD_HUGEFRAME 0x0080
  150. #define TXBD_LATECOLLISION 0x0080
  151. #define TXBD_RETRYLIMIT 0x0040
  152. #define TXBD_RETRYCOUNTMASK 0x003c
  153. #define TXBD_UNDERRUN 0x0002
  154. #define TXBD_STATS 0x03ff
  155. /* RxBD status field bits */
  156. #define RXBD_EMPTY 0x8000
  157. #define RXBD_RO1 0x4000
  158. #define RXBD_WRAP 0x2000
  159. #define RXBD_INTERRUPT 0x1000
  160. #define RXBD_LAST 0x0800
  161. #define RXBD_FIRST 0x0400
  162. #define RXBD_MISS 0x0100
  163. #define RXBD_BROADCAST 0x0080
  164. #define RXBD_MULTICAST 0x0040
  165. #define RXBD_LARGE 0x0020
  166. #define RXBD_NONOCTET 0x0010
  167. #define RXBD_SHORT 0x0008
  168. #define RXBD_CRCERR 0x0004
  169. #define RXBD_OVERRUN 0x0002
  170. #define RXBD_TRUNCATED 0x0001
  171. #define RXBD_STATS 0x003f
  172. struct txbd8 {
  173. uint16_t status; /* Status Fields */
  174. uint16_t length; /* Buffer length */
  175. uint32_t bufptr; /* Buffer Pointer */
  176. };
  177. struct rxbd8 {
  178. uint16_t status; /* Status Fields */
  179. uint16_t length; /* Buffer Length */
  180. uint32_t bufptr; /* Buffer Pointer */
  181. };
  182. struct tsec_rmon_mib {
  183. /* Transmit and Receive Counters */
  184. u32 tr64; /* Tx/Rx 64-byte Frame Counter */
  185. u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
  186. u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
  187. u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
  188. u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
  189. u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
  190. u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
  191. /* Receive Counters */
  192. u32 rbyt; /* Receive Byte Counter */
  193. u32 rpkt; /* Receive Packet Counter */
  194. u32 rfcs; /* Receive FCS Error Counter */
  195. u32 rmca; /* Receive Multicast Packet (Counter) */
  196. u32 rbca; /* Receive Broadcast Packet */
  197. u32 rxcf; /* Receive Control Frame Packet */
  198. u32 rxpf; /* Receive Pause Frame Packet */
  199. u32 rxuo; /* Receive Unknown OP Code */
  200. u32 raln; /* Receive Alignment Error */
  201. u32 rflr; /* Receive Frame Length Error */
  202. u32 rcde; /* Receive Code Error */
  203. u32 rcse; /* Receive Carrier Sense Error */
  204. u32 rund; /* Receive Undersize Packet */
  205. u32 rovr; /* Receive Oversize Packet */
  206. u32 rfrg; /* Receive Fragments */
  207. u32 rjbr; /* Receive Jabber */
  208. u32 rdrp; /* Receive Drop */
  209. /* Transmit Counters */
  210. u32 tbyt; /* Transmit Byte Counter */
  211. u32 tpkt; /* Transmit Packet */
  212. u32 tmca; /* Transmit Multicast Packet */
  213. u32 tbca; /* Transmit Broadcast Packet */
  214. u32 txpf; /* Transmit Pause Control Frame */
  215. u32 tdfr; /* Transmit Deferral Packet */
  216. u32 tedf; /* Transmit Excessive Deferral Packet */
  217. u32 tscl; /* Transmit Single Collision Packet */
  218. /* (0x2_n700) */
  219. u32 tmcl; /* Transmit Multiple Collision Packet */
  220. u32 tlcl; /* Transmit Late Collision Packet */
  221. u32 txcl; /* Transmit Excessive Collision Packet */
  222. u32 tncl; /* Transmit Total Collision */
  223. u32 res2;
  224. u32 tdrp; /* Transmit Drop Frame */
  225. u32 tjbr; /* Transmit Jabber Frame */
  226. u32 tfcs; /* Transmit FCS Error */
  227. u32 txcf; /* Transmit Control Frame */
  228. u32 tovr; /* Transmit Oversize Frame */
  229. u32 tund; /* Transmit Undersize Frame */
  230. u32 tfrg; /* Transmit Fragments Frame */
  231. /* General Registers */
  232. u32 car1; /* Carry Register One */
  233. u32 car2; /* Carry Register Two */
  234. u32 cam1; /* Carry Register One Mask */
  235. u32 cam2; /* Carry Register Two Mask */
  236. };
  237. struct tsec_hash_regs {
  238. u32 iaddr0; /* Individual Address Register 0 */
  239. u32 iaddr1; /* Individual Address Register 1 */
  240. u32 iaddr2; /* Individual Address Register 2 */
  241. u32 iaddr3; /* Individual Address Register 3 */
  242. u32 iaddr4; /* Individual Address Register 4 */
  243. u32 iaddr5; /* Individual Address Register 5 */
  244. u32 iaddr6; /* Individual Address Register 6 */
  245. u32 iaddr7; /* Individual Address Register 7 */
  246. u32 res1[24];
  247. u32 gaddr0; /* Group Address Register 0 */
  248. u32 gaddr1; /* Group Address Register 1 */
  249. u32 gaddr2; /* Group Address Register 2 */
  250. u32 gaddr3; /* Group Address Register 3 */
  251. u32 gaddr4; /* Group Address Register 4 */
  252. u32 gaddr5; /* Group Address Register 5 */
  253. u32 gaddr6; /* Group Address Register 6 */
  254. u32 gaddr7; /* Group Address Register 7 */
  255. u32 res2[24];
  256. };
  257. struct tsec {
  258. /* General Control and Status Registers (0x2_n000) */
  259. u32 res000[4];
  260. u32 ievent; /* Interrupt Event */
  261. u32 imask; /* Interrupt Mask */
  262. u32 edis; /* Error Disabled */
  263. u32 res01c;
  264. u32 ecntrl; /* Ethernet Control */
  265. u32 minflr; /* Minimum Frame Length */
  266. u32 ptv; /* Pause Time Value */
  267. u32 dmactrl; /* DMA Control */
  268. u32 tbipa; /* TBI PHY Address */
  269. u32 res034[3];
  270. u32 res040[48];
  271. /* Transmit Control and Status Registers (0x2_n100) */
  272. u32 tctrl; /* Transmit Control */
  273. u32 tstat; /* Transmit Status */
  274. u32 res108;
  275. u32 tbdlen; /* Tx BD Data Length */
  276. u32 res110[5];
  277. u32 ctbptr; /* Current TxBD Pointer */
  278. u32 res128[23];
  279. u32 tbptr; /* TxBD Pointer */
  280. u32 res188[30];
  281. /* (0x2_n200) */
  282. u32 res200;
  283. u32 tbase; /* TxBD Base Address */
  284. u32 res208[42];
  285. u32 ostbd; /* Out of Sequence TxBD */
  286. u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
  287. u32 res2b8[18];
  288. /* Receive Control and Status Registers (0x2_n300) */
  289. u32 rctrl; /* Receive Control */
  290. u32 rstat; /* Receive Status */
  291. u32 res308;
  292. u32 rbdlen; /* RxBD Data Length */
  293. u32 res310[4];
  294. u32 res320;
  295. u32 crbptr; /* Current Receive Buffer Pointer */
  296. u32 res328[6];
  297. u32 mrblr; /* Maximum Receive Buffer Length */
  298. u32 res344[16];
  299. u32 rbptr; /* RxBD Pointer */
  300. u32 res388[30];
  301. /* (0x2_n400) */
  302. u32 res400;
  303. u32 rbase; /* RxBD Base Address */
  304. u32 res408[62];
  305. /* MAC Registers (0x2_n500) */
  306. u32 maccfg1; /* MAC Configuration #1 */
  307. u32 maccfg2; /* MAC Configuration #2 */
  308. u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
  309. u32 hafdup; /* Half-duplex */
  310. u32 maxfrm; /* Maximum Frame */
  311. u32 res514;
  312. u32 res518;
  313. u32 res51c;
  314. u32 resmdio[6];
  315. u32 res538;
  316. u32 ifstat; /* Interface Status */
  317. u32 macstnaddr1; /* Station Address, part 1 */
  318. u32 macstnaddr2; /* Station Address, part 2 */
  319. u32 res548[46];
  320. /* (0x2_n600) */
  321. u32 res600[32];
  322. /* RMON MIB Registers (0x2_n680-0x2_n73c) */
  323. struct tsec_rmon_mib rmon;
  324. u32 res740[48];
  325. /* Hash Function Registers (0x2_n800) */
  326. struct tsec_hash_regs hash;
  327. u32 res900[128];
  328. /* Pattern Registers (0x2_nb00) */
  329. u32 resb00[62];
  330. u32 attr; /* Default Attribute Register */
  331. u32 attreli; /* Default Attribute Extract Length and Index */
  332. /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
  333. u32 resc00[256];
  334. };
  335. #define TSEC_GIGABIT (1 << 0)
  336. /* These flags currently only have meaning if we're using the eTSEC */
  337. #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
  338. #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
  339. #define TX_BUF_CNT 2
  340. struct tsec_private {
  341. struct txbd8 __iomem txbd[TX_BUF_CNT];
  342. struct rxbd8 __iomem rxbd[PKTBUFSRX];
  343. struct tsec __iomem *regs;
  344. struct tsec_mii_mng __iomem *phyregs_sgmii;
  345. struct phy_device *phydev;
  346. phy_interface_t interface;
  347. struct mii_dev *bus;
  348. uint phyaddr;
  349. uint tbiaddr;
  350. char mii_devname[16];
  351. u32 flags;
  352. uint rx_idx; /* index of the current RX buffer */
  353. uint tx_idx; /* index of the current TX buffer */
  354. #ifndef CONFIG_DM_ETH
  355. struct eth_device *dev;
  356. #else
  357. struct udevice *dev;
  358. #endif
  359. };
  360. struct tsec_info_struct {
  361. struct tsec __iomem *regs;
  362. struct tsec_mii_mng __iomem *miiregs_sgmii;
  363. char *devname;
  364. char *mii_devname;
  365. phy_interface_t interface;
  366. unsigned int phyaddr;
  367. u32 flags;
  368. };
  369. #ifndef CONFIG_DM_ETH
  370. int tsec_standard_init(bd_t *bis);
  371. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
  372. #endif
  373. #endif /* __TSEC_H */