sdhci.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #ifndef __SDHCI_HW_H
  10. #define __SDHCI_HW_H
  11. #include <asm/io.h>
  12. #include <mmc.h>
  13. #include <asm/gpio.h>
  14. /*
  15. * Controller registers
  16. */
  17. #define SDHCI_DMA_ADDRESS 0x00
  18. #define SDHCI_BLOCK_SIZE 0x04
  19. #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  20. #define SDHCI_BLOCK_COUNT 0x06
  21. #define SDHCI_ARGUMENT 0x08
  22. #define SDHCI_TRANSFER_MODE 0x0C
  23. #define SDHCI_TRNS_DMA BIT(0)
  24. #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
  25. #define SDHCI_TRNS_ACMD12 BIT(2)
  26. #define SDHCI_TRNS_READ BIT(4)
  27. #define SDHCI_TRNS_MULTI BIT(5)
  28. #define SDHCI_COMMAND 0x0E
  29. #define SDHCI_CMD_RESP_MASK 0x03
  30. #define SDHCI_CMD_CRC 0x08
  31. #define SDHCI_CMD_INDEX 0x10
  32. #define SDHCI_CMD_DATA 0x20
  33. #define SDHCI_CMD_ABORTCMD 0xC0
  34. #define SDHCI_CMD_RESP_NONE 0x00
  35. #define SDHCI_CMD_RESP_LONG 0x01
  36. #define SDHCI_CMD_RESP_SHORT 0x02
  37. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  38. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  39. #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  40. #define SDHCI_RESPONSE 0x10
  41. #define SDHCI_BUFFER 0x20
  42. #define SDHCI_PRESENT_STATE 0x24
  43. #define SDHCI_CMD_INHIBIT BIT(0)
  44. #define SDHCI_DATA_INHIBIT BIT(1)
  45. #define SDHCI_DOING_WRITE BIT(8)
  46. #define SDHCI_DOING_READ BIT(9)
  47. #define SDHCI_SPACE_AVAILABLE BIT(10)
  48. #define SDHCI_DATA_AVAILABLE BIT(11)
  49. #define SDHCI_CARD_PRESENT BIT(16)
  50. #define SDHCI_CARD_STATE_STABLE BIT(17)
  51. #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
  52. #define SDHCI_WRITE_PROTECT BIT(19)
  53. #define SDHCI_HOST_CONTROL 0x28
  54. #define SDHCI_CTRL_LED BIT(0)
  55. #define SDHCI_CTRL_4BITBUS BIT(1)
  56. #define SDHCI_CTRL_HISPD BIT(2)
  57. #define SDHCI_CTRL_DMA_MASK 0x18
  58. #define SDHCI_CTRL_SDMA 0x00
  59. #define SDHCI_CTRL_ADMA1 0x08
  60. #define SDHCI_CTRL_ADMA32 0x10
  61. #define SDHCI_CTRL_ADMA64 0x18
  62. #define SDHCI_CTRL_8BITBUS BIT(5)
  63. #define SDHCI_CTRL_CD_TEST_INS BIT(6)
  64. #define SDHCI_CTRL_CD_TEST BIT(7)
  65. #define SDHCI_POWER_CONTROL 0x29
  66. #define SDHCI_POWER_ON 0x01
  67. #define SDHCI_POWER_180 0x0A
  68. #define SDHCI_POWER_300 0x0C
  69. #define SDHCI_POWER_330 0x0E
  70. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  71. #define SDHCI_WAKE_UP_CONTROL 0x2B
  72. #define SDHCI_WAKE_ON_INT BIT(0)
  73. #define SDHCI_WAKE_ON_INSERT BIT(1)
  74. #define SDHCI_WAKE_ON_REMOVE BIT(2)
  75. #define SDHCI_CLOCK_CONTROL 0x2C
  76. #define SDHCI_DIVIDER_SHIFT 8
  77. #define SDHCI_DIVIDER_HI_SHIFT 6
  78. #define SDHCI_DIV_MASK 0xFF
  79. #define SDHCI_DIV_MASK_LEN 8
  80. #define SDHCI_DIV_HI_MASK 0x300
  81. #define SDHCI_PROG_CLOCK_MODE BIT(5)
  82. #define SDHCI_CLOCK_CARD_EN BIT(2)
  83. #define SDHCI_CLOCK_INT_STABLE BIT(1)
  84. #define SDHCI_CLOCK_INT_EN BIT(0)
  85. #define SDHCI_TIMEOUT_CONTROL 0x2E
  86. #define SDHCI_SOFTWARE_RESET 0x2F
  87. #define SDHCI_RESET_ALL 0x01
  88. #define SDHCI_RESET_CMD 0x02
  89. #define SDHCI_RESET_DATA 0x04
  90. #define SDHCI_INT_STATUS 0x30
  91. #define SDHCI_INT_ENABLE 0x34
  92. #define SDHCI_SIGNAL_ENABLE 0x38
  93. #define SDHCI_INT_RESPONSE BIT(0)
  94. #define SDHCI_INT_DATA_END BIT(1)
  95. #define SDHCI_INT_DMA_END BIT(3)
  96. #define SDHCI_INT_SPACE_AVAIL BIT(4)
  97. #define SDHCI_INT_DATA_AVAIL BIT(5)
  98. #define SDHCI_INT_CARD_INSERT BIT(6)
  99. #define SDHCI_INT_CARD_REMOVE BIT(7)
  100. #define SDHCI_INT_CARD_INT BIT(8)
  101. #define SDHCI_INT_ERROR BIT(15)
  102. #define SDHCI_INT_TIMEOUT BIT(16)
  103. #define SDHCI_INT_CRC BIT(17)
  104. #define SDHCI_INT_END_BIT BIT(18)
  105. #define SDHCI_INT_INDEX BIT(19)
  106. #define SDHCI_INT_DATA_TIMEOUT BIT(20)
  107. #define SDHCI_INT_DATA_CRC BIT(21)
  108. #define SDHCI_INT_DATA_END_BIT BIT(22)
  109. #define SDHCI_INT_BUS_POWER BIT(23)
  110. #define SDHCI_INT_ACMD12ERR BIT(24)
  111. #define SDHCI_INT_ADMA_ERROR BIT(25)
  112. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  113. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  114. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
  115. SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
  116. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
  117. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
  118. SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
  119. SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
  120. #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
  121. #define SDHCI_ACMD12_ERR 0x3C
  122. #define SDHCI_HOST_CONTROL2 0x3E
  123. #define SDHCI_CTRL_UHS_MASK 0x0007
  124. #define SDHCI_CTRL_UHS_SDR12 0x0000
  125. #define SDHCI_CTRL_UHS_SDR25 0x0001
  126. #define SDHCI_CTRL_UHS_SDR50 0x0002
  127. #define SDHCI_CTRL_UHS_SDR104 0x0003
  128. #define SDHCI_CTRL_UHS_DDR50 0x0004
  129. #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
  130. #define SDHCI_CTRL_VDD_180 0x0008
  131. #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
  132. #define SDHCI_CTRL_DRV_TYPE_B 0x0000
  133. #define SDHCI_CTRL_DRV_TYPE_A 0x0010
  134. #define SDHCI_CTRL_DRV_TYPE_C 0x0020
  135. #define SDHCI_CTRL_DRV_TYPE_D 0x0030
  136. #define SDHCI_CTRL_EXEC_TUNING 0x0040
  137. #define SDHCI_CTRL_TUNED_CLK 0x0080
  138. #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
  139. #define SDHCI_CAPABILITIES 0x40
  140. #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
  141. #define SDHCI_TIMEOUT_CLK_SHIFT 0
  142. #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
  143. #define SDHCI_CLOCK_BASE_MASK 0x00003F00
  144. #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
  145. #define SDHCI_CLOCK_BASE_SHIFT 8
  146. #define SDHCI_MAX_BLOCK_MASK 0x00030000
  147. #define SDHCI_MAX_BLOCK_SHIFT 16
  148. #define SDHCI_CAN_DO_8BIT BIT(18)
  149. #define SDHCI_CAN_DO_ADMA2 BIT(19)
  150. #define SDHCI_CAN_DO_ADMA1 BIT(20)
  151. #define SDHCI_CAN_DO_HISPD BIT(21)
  152. #define SDHCI_CAN_DO_SDMA BIT(22)
  153. #define SDHCI_CAN_VDD_330 BIT(24)
  154. #define SDHCI_CAN_VDD_300 BIT(25)
  155. #define SDHCI_CAN_VDD_180 BIT(26)
  156. #define SDHCI_CAN_64BIT BIT(28)
  157. #define SDHCI_CAPABILITIES_1 0x44
  158. #define SDHCI_SUPPORT_SDR50 0x00000001
  159. #define SDHCI_SUPPORT_SDR104 0x00000002
  160. #define SDHCI_SUPPORT_DDR50 0x00000004
  161. #define SDHCI_USE_SDR50_TUNING 0x00002000
  162. #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
  163. #define SDHCI_CLOCK_MUL_SHIFT 16
  164. #define SDHCI_MAX_CURRENT 0x48
  165. /* 4C-4F reserved for more max current */
  166. #define SDHCI_SET_ACMD12_ERROR 0x50
  167. #define SDHCI_SET_INT_ERROR 0x52
  168. #define SDHCI_ADMA_ERROR 0x54
  169. /* 55-57 reserved */
  170. #define SDHCI_ADMA_ADDRESS 0x58
  171. #define SDHCI_ADMA_ADDRESS_HI 0x5c
  172. /* 60-FB reserved */
  173. #define SDHCI_SLOT_INT_STATUS 0xFC
  174. #define SDHCI_HOST_VERSION 0xFE
  175. #define SDHCI_VENDOR_VER_MASK 0xFF00
  176. #define SDHCI_VENDOR_VER_SHIFT 8
  177. #define SDHCI_SPEC_VER_MASK 0x00FF
  178. #define SDHCI_SPEC_VER_SHIFT 0
  179. #define SDHCI_SPEC_100 0
  180. #define SDHCI_SPEC_200 1
  181. #define SDHCI_SPEC_300 2
  182. #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
  183. /*
  184. * End of controller registers.
  185. */
  186. #define SDHCI_MAX_DIV_SPEC_200 256
  187. #define SDHCI_MAX_DIV_SPEC_300 2046
  188. /*
  189. * quirks
  190. */
  191. #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
  192. #define SDHCI_QUIRK_REG32_RW (1 << 1)
  193. #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
  194. #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
  195. #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
  196. /*
  197. * SDHCI_QUIRK_BROKEN_HISPD_MODE
  198. * the hardware cannot operate correctly in high-speed mode,
  199. * this quirk forces the sdhci host-controller to non high-speed mode
  200. */
  201. #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
  202. #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
  203. #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
  204. #define SDHCI_QUIRK_NO_1_8_V (1 << 9)
  205. /* to make gcc happy */
  206. struct sdhci_host;
  207. /*
  208. * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
  209. */
  210. #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
  211. #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
  212. struct sdhci_ops {
  213. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  214. u32 (*read_l)(struct sdhci_host *host, int reg);
  215. u16 (*read_w)(struct sdhci_host *host, int reg);
  216. u8 (*read_b)(struct sdhci_host *host, int reg);
  217. void (*write_l)(struct sdhci_host *host, u32 val, int reg);
  218. void (*write_w)(struct sdhci_host *host, u16 val, int reg);
  219. void (*write_b)(struct sdhci_host *host, u8 val, int reg);
  220. #endif
  221. int (*get_cd)(struct sdhci_host *host);
  222. void (*set_control_reg)(struct sdhci_host *host);
  223. int (*set_ios_post)(struct sdhci_host *host);
  224. void (*set_clock)(struct sdhci_host *host, u32 div);
  225. int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
  226. void (*set_delay)(struct sdhci_host *host);
  227. };
  228. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  229. #define ADMA_MAX_LEN 65532
  230. #ifdef CONFIG_DMA_ADDR_T_64BIT
  231. #define ADMA_DESC_LEN 16
  232. #else
  233. #define ADMA_DESC_LEN 8
  234. #endif
  235. #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
  236. MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
  237. #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
  238. /* Decriptor table defines */
  239. #define ADMA_DESC_ATTR_VALID BIT(0)
  240. #define ADMA_DESC_ATTR_END BIT(1)
  241. #define ADMA_DESC_ATTR_INT BIT(2)
  242. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  243. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  244. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  245. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  246. struct sdhci_adma_desc {
  247. u8 attr;
  248. u8 reserved;
  249. u16 len;
  250. u32 addr_lo;
  251. #ifdef CONFIG_DMA_ADDR_T_64BIT
  252. u32 addr_hi;
  253. #endif
  254. } __packed;
  255. #endif
  256. struct sdhci_host {
  257. const char *name;
  258. void *ioaddr;
  259. unsigned int quirks;
  260. unsigned int host_caps;
  261. unsigned int version;
  262. unsigned int max_clk; /* Maximum Base Clock frequency */
  263. unsigned int clk_mul; /* Clock Multiplier value */
  264. unsigned int clock;
  265. struct mmc *mmc;
  266. const struct sdhci_ops *ops;
  267. int index;
  268. int bus_width;
  269. struct gpio_desc pwr_gpio; /* Power GPIO */
  270. struct gpio_desc cd_gpio; /* Card Detect GPIO */
  271. uint voltages;
  272. struct mmc_config cfg;
  273. dma_addr_t start_addr;
  274. int flags;
  275. #define USE_SDMA (0x1 << 0)
  276. #define USE_ADMA (0x1 << 1)
  277. #define USE_ADMA64 (0x1 << 2)
  278. #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
  279. dma_addr_t adma_addr;
  280. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  281. struct sdhci_adma_desc *adma_desc_table;
  282. uint desc_slot;
  283. #endif
  284. };
  285. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  286. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  287. {
  288. if (unlikely(host->ops->write_l))
  289. host->ops->write_l(host, val, reg);
  290. else
  291. writel(val, host->ioaddr + reg);
  292. }
  293. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  294. {
  295. if (unlikely(host->ops->write_w))
  296. host->ops->write_w(host, val, reg);
  297. else
  298. writew(val, host->ioaddr + reg);
  299. }
  300. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  301. {
  302. if (unlikely(host->ops->write_b))
  303. host->ops->write_b(host, val, reg);
  304. else
  305. writeb(val, host->ioaddr + reg);
  306. }
  307. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  308. {
  309. if (unlikely(host->ops->read_l))
  310. return host->ops->read_l(host, reg);
  311. else
  312. return readl(host->ioaddr + reg);
  313. }
  314. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  315. {
  316. if (unlikely(host->ops->read_w))
  317. return host->ops->read_w(host, reg);
  318. else
  319. return readw(host->ioaddr + reg);
  320. }
  321. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  322. {
  323. if (unlikely(host->ops->read_b))
  324. return host->ops->read_b(host, reg);
  325. else
  326. return readb(host->ioaddr + reg);
  327. }
  328. #else
  329. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  330. {
  331. writel(val, host->ioaddr + reg);
  332. }
  333. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  334. {
  335. writew(val, host->ioaddr + reg);
  336. }
  337. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  338. {
  339. writeb(val, host->ioaddr + reg);
  340. }
  341. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  342. {
  343. return readl(host->ioaddr + reg);
  344. }
  345. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  346. {
  347. return readw(host->ioaddr + reg);
  348. }
  349. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  350. {
  351. return readb(host->ioaddr + reg);
  352. }
  353. #endif
  354. #ifdef CONFIG_BLK
  355. /**
  356. * sdhci_setup_cfg() - Set up the configuration for DWMMC
  357. *
  358. * This is used to set up an SDHCI device when you are using CONFIG_BLK.
  359. *
  360. * This should be called from your MMC driver's probe() method once you have
  361. * the information required.
  362. *
  363. * Generally your driver will have a platform data structure which holds both
  364. * the configuration (struct mmc_config) and the MMC device info (struct mmc).
  365. * For example:
  366. *
  367. * struct msm_sdhc_plat {
  368. * struct mmc_config cfg;
  369. * struct mmc mmc;
  370. * };
  371. *
  372. * ...
  373. *
  374. * Inside U_BOOT_DRIVER():
  375. * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
  376. *
  377. * To access platform data:
  378. * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
  379. *
  380. * See msm_sdhci.c for an example.
  381. *
  382. * @cfg: Configuration structure to fill in (generally &plat->mmc)
  383. * @host: SDHCI host structure
  384. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  385. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  386. */
  387. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  388. u32 f_max, u32 f_min);
  389. /**
  390. * sdhci_bind() - Set up a new MMC block device
  391. *
  392. * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
  393. * It should be called from your driver's bind() method.
  394. *
  395. * See msm_sdhci.c for an example.
  396. *
  397. * @dev: Device to set up
  398. * @mmc: Pointer to mmc structure (normally &plat->mmc)
  399. * @cfg: Empty configuration structure (generally &plat->cfg). This is
  400. * normally all zeroes at this point. The only purpose of passing
  401. * this in is to set mmc->cfg to it.
  402. * @return 0 if OK, -ve if the block device could not be created
  403. */
  404. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  405. #else
  406. /**
  407. * add_sdhci() - Add a new SDHCI interface
  408. *
  409. * This is used when you are not using CONFIG_BLK. Convert your driver over!
  410. *
  411. * @host: SDHCI host structure
  412. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  413. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  414. * @return 0 if OK, -ve on error
  415. */
  416. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
  417. #endif /* !CONFIG_BLK */
  418. void sdhci_set_uhs_timing(struct sdhci_host *host);
  419. #ifdef CONFIG_DM_MMC
  420. /* Export the operations to drivers */
  421. int sdhci_probe(struct udevice *dev);
  422. int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
  423. extern const struct dm_mmc_ops sdhci_ops;
  424. #else
  425. #endif
  426. #endif /* __SDHCI_HW_H */