radeon.h 80 KB

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  1. #ifndef _RADEON_H
  2. #define _RADEON_H
  3. #define RADEON_REGSIZE 0x4000
  4. #define MM_INDEX 0x0000
  5. #define MM_DATA 0x0004
  6. #define BUS_CNTL 0x0030
  7. #define HI_STAT 0x004C
  8. #define BUS_CNTL1 0x0034
  9. #define I2C_CNTL_1 0x0094
  10. #define CONFIG_CNTL 0x00E0
  11. #define CONFIG_MEMSIZE 0x00F8
  12. #define CONFIG_APER_0_BASE 0x0100
  13. #define CONFIG_APER_1_BASE 0x0104
  14. #define CONFIG_APER_SIZE 0x0108
  15. #define CONFIG_REG_1_BASE 0x010C
  16. #define CONFIG_REG_APER_SIZE 0x0110
  17. #define PAD_AGPINPUT_DELAY 0x0164
  18. #define PAD_CTLR_STRENGTH 0x0168
  19. #define PAD_CTLR_UPDATE 0x016C
  20. #define PAD_CTLR_MISC 0x0aa0
  21. #define AGP_CNTL 0x0174
  22. #define BM_STATUS 0x0160
  23. #define CAP0_TRIG_CNTL 0x0950
  24. #define CAP1_TRIG_CNTL 0x09c0
  25. #define VIPH_CONTROL 0x0C40
  26. #define VENDOR_ID 0x0F00
  27. #define DEVICE_ID 0x0F02
  28. #define COMMAND 0x0F04
  29. #define STATUS 0x0F06
  30. #define REVISION_ID 0x0F08
  31. #define REGPROG_INF 0x0F09
  32. #define SUB_CLASS 0x0F0A
  33. #define BASE_CODE 0x0F0B
  34. #define CACHE_LINE 0x0F0C
  35. #define LATENCY 0x0F0D
  36. #define HEADER 0x0F0E
  37. #define BIST 0x0F0F
  38. #define REG_MEM_BASE 0x0F10
  39. #define REG_IO_BASE 0x0F14
  40. #define REG_REG_BASE 0x0F18
  41. #define ADAPTER_ID 0x0F2C
  42. #define BIOS_ROM 0x0F30
  43. #define CAPABILITIES_PTR 0x0F34
  44. #define INTERRUPT_LINE 0x0F3C
  45. #define INTERRUPT_PIN 0x0F3D
  46. #define MIN_GRANT 0x0F3E
  47. #define MAX_LATENCY 0x0F3F
  48. #define ADAPTER_ID_W 0x0F4C
  49. #define PMI_CAP_ID 0x0F50
  50. #define PMI_NXT_CAP_PTR 0x0F51
  51. #define PMI_PMC_REG 0x0F52
  52. #define PM_STATUS 0x0F54
  53. #define PMI_DATA 0x0F57
  54. #define AGP_CAP_ID 0x0F58
  55. #define AGP_STATUS 0x0F5C
  56. #define AGP_COMMAND 0x0F60
  57. #define AIC_CTRL 0x01D0
  58. #define AIC_STAT 0x01D4
  59. #define AIC_PT_BASE 0x01D8
  60. #define AIC_LO_ADDR 0x01DC
  61. #define AIC_HI_ADDR 0x01E0
  62. #define AIC_TLB_ADDR 0x01E4
  63. #define AIC_TLB_DATA 0x01E8
  64. #define DAC_CNTL 0x0058
  65. #define DAC_CNTL2 0x007c
  66. #define CRTC_GEN_CNTL 0x0050
  67. #define MEM_CNTL 0x0140
  68. #define MC_CNTL 0x0140
  69. #define EXT_MEM_CNTL 0x0144
  70. #define MC_TIMING_CNTL 0x0144
  71. #define MC_AGP_LOCATION 0x014C
  72. #define MEM_IO_CNTL_A0 0x0178
  73. #define MEM_REFRESH_CNTL 0x0178
  74. #define MEM_INIT_LATENCY_TIMER 0x0154
  75. #define MC_INIT_GFX_LAT_TIMER 0x0154
  76. #define MEM_SDRAM_MODE_REG 0x0158
  77. #define AGP_BASE 0x0170
  78. #define MEM_IO_CNTL_A1 0x017C
  79. #define MC_READ_CNTL_AB 0x017C
  80. #define MEM_IO_CNTL_B0 0x0180
  81. #define MC_INIT_MISC_LAT_TIMER 0x0180
  82. #define MEM_IO_CNTL_B1 0x0184
  83. #define MC_IOPAD_CNTL 0x0184
  84. #define MC_DEBUG 0x0188
  85. #define MC_STATUS 0x0150
  86. #define MEM_IO_OE_CNTL 0x018C
  87. #define MC_CHIP_IO_OE_CNTL_AB 0x018C
  88. #define MC_FB_LOCATION 0x0148
  89. /* #define MC_FB_LOCATION 0x0188 */
  90. #define HOST_PATH_CNTL 0x0130
  91. #define MEM_VGA_WP_SEL 0x0038
  92. #define MEM_VGA_RP_SEL 0x003C
  93. #define HDP_DEBUG 0x0138
  94. #define SW_SEMAPHORE 0x013C
  95. #define CRTC2_GEN_CNTL 0x03f8
  96. #define CRTC2_DISPLAY_BASE_ADDR 0x033c
  97. #define SURFACE_CNTL 0x0B00
  98. #define SURFACE0_LOWER_BOUND 0x0B04
  99. #define SURFACE1_LOWER_BOUND 0x0B14
  100. #define SURFACE2_LOWER_BOUND 0x0B24
  101. #define SURFACE3_LOWER_BOUND 0x0B34
  102. #define SURFACE4_LOWER_BOUND 0x0B44
  103. #define SURFACE5_LOWER_BOUND 0x0B54
  104. #define SURFACE6_LOWER_BOUND 0x0B64
  105. #define SURFACE7_LOWER_BOUND 0x0B74
  106. #define SURFACE0_UPPER_BOUND 0x0B08
  107. #define SURFACE1_UPPER_BOUND 0x0B18
  108. #define SURFACE2_UPPER_BOUND 0x0B28
  109. #define SURFACE3_UPPER_BOUND 0x0B38
  110. #define SURFACE4_UPPER_BOUND 0x0B48
  111. #define SURFACE5_UPPER_BOUND 0x0B58
  112. #define SURFACE6_UPPER_BOUND 0x0B68
  113. #define SURFACE7_UPPER_BOUND 0x0B78
  114. #define SURFACE0_INFO 0x0B0C
  115. #define SURFACE1_INFO 0x0B1C
  116. #define SURFACE2_INFO 0x0B2C
  117. #define SURFACE3_INFO 0x0B3C
  118. #define SURFACE4_INFO 0x0B4C
  119. #define SURFACE5_INFO 0x0B5C
  120. #define SURFACE6_INFO 0x0B6C
  121. #define SURFACE7_INFO 0x0B7C
  122. #define SURFACE_ACCESS_FLAGS 0x0BF8
  123. #define SURFACE_ACCESS_CLR 0x0BFC
  124. #define GEN_INT_CNTL 0x0040
  125. #define GEN_INT_STATUS 0x0044
  126. #define CRTC_EXT_CNTL 0x0054
  127. #define RB3D_CNTL 0x1C3C
  128. #define WAIT_UNTIL 0x1720
  129. #define ISYNC_CNTL 0x1724
  130. #define RBBM_GUICNTL 0x172C
  131. #define RBBM_STATUS 0x0E40
  132. #define RBBM_STATUS_alt_1 0x1740
  133. #define RBBM_CNTL 0x00EC
  134. #define RBBM_CNTL_alt_1 0x0E44
  135. #define RBBM_SOFT_RESET 0x00F0
  136. #define RBBM_SOFT_RESET_alt_1 0x0E48
  137. #define NQWAIT_UNTIL 0x0E50
  138. #define RBBM_DEBUG 0x0E6C
  139. #define RBBM_CMDFIFO_ADDR 0x0E70
  140. #define RBBM_CMDFIFO_DATAL 0x0E74
  141. #define RBBM_CMDFIFO_DATAH 0x0E78
  142. #define RBBM_CMDFIFO_STAT 0x0E7C
  143. #define CRTC_STATUS 0x005C
  144. #define GPIO_VGA_DDC 0x0060
  145. #define GPIO_DVI_DDC 0x0064
  146. #define GPIO_MONID 0x0068
  147. #define GPIO_CRT2_DDC 0x006c
  148. #define PALETTE_INDEX 0x00B0
  149. #define PALETTE_DATA 0x00B4
  150. #define PALETTE_30_DATA 0x00B8
  151. #define CRTC_H_TOTAL_DISP 0x0200
  152. #define CRTC_H_SYNC_STRT_WID 0x0204
  153. #define CRTC_H_SYNC_POL (1 << 23)
  154. #define CRTC_V_TOTAL_DISP 0x0208
  155. #define CRTC_V_SYNC_STRT_WID 0x020C
  156. #define CRTC_V_SYNC_POL (1 << 23)
  157. #define CRTC_VLINE_CRNT_VLINE 0x0210
  158. #define CRTC_CRNT_FRAME 0x0214
  159. #define CRTC_GUI_TRIG_VLINE 0x0218
  160. #define CRTC_DEBUG 0x021C
  161. #define CRTC_OFFSET_RIGHT 0x0220
  162. #define CRTC_OFFSET 0x0224
  163. #define CRTC_OFFSET_CNTL 0x0228
  164. #define CRTC_PITCH 0x022C
  165. #define OVR_CLR 0x0230
  166. #define OVR_WID_LEFT_RIGHT 0x0234
  167. #define OVR_WID_TOP_BOTTOM 0x0238
  168. #define DISPLAY_BASE_ADDR 0x023C
  169. #define SNAPSHOT_VH_COUNTS 0x0240
  170. #define SNAPSHOT_F_COUNT 0x0244
  171. #define N_VIF_COUNT 0x0248
  172. #define SNAPSHOT_VIF_COUNT 0x024C
  173. #define FP_CRTC_H_TOTAL_DISP 0x0250
  174. #define FP_CRTC_V_TOTAL_DISP 0x0254
  175. #define CRT_CRTC_H_SYNC_STRT_WID 0x0258
  176. #define CRT_CRTC_V_SYNC_STRT_WID 0x025C
  177. #define CUR_OFFSET 0x0260
  178. #define CUR_HORZ_VERT_POSN 0x0264
  179. #define CUR_HORZ_VERT_OFF 0x0268
  180. #define CUR_CLR0 0x026C
  181. #define CUR_CLR1 0x0270
  182. #define FP_HORZ_VERT_ACTIVE 0x0278
  183. #define CRTC_MORE_CNTL 0x027C
  184. #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
  185. #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
  186. #define DAC_EXT_CNTL 0x0280
  187. #define FP_GEN_CNTL 0x0284
  188. #define FP_HORZ_STRETCH 0x028C
  189. #define FP_VERT_STRETCH 0x0290
  190. #define FP_H_SYNC_STRT_WID 0x02C4
  191. #define FP_V_SYNC_STRT_WID 0x02C8
  192. #define AUX_WINDOW_HORZ_CNTL 0x02D8
  193. #define AUX_WINDOW_VERT_CNTL 0x02DC
  194. /* #define DDA_CONFIG 0x02e0 */
  195. /* #define DDA_ON_OFF 0x02e4 */
  196. #define DVI_I2C_CNTL_1 0x02e4
  197. #define GRPH_BUFFER_CNTL 0x02F0
  198. #define GRPH2_BUFFER_CNTL 0x03F0
  199. #define VGA_BUFFER_CNTL 0x02F4
  200. #define OV0_Y_X_START 0x0400
  201. #define OV0_Y_X_END 0x0404
  202. #define OV0_PIPELINE_CNTL 0x0408
  203. #define OV0_REG_LOAD_CNTL 0x0410
  204. #define OV0_SCALE_CNTL 0x0420
  205. #define OV0_V_INC 0x0424
  206. #define OV0_P1_V_ACCUM_INIT 0x0428
  207. #define OV0_P23_V_ACCUM_INIT 0x042C
  208. #define OV0_P1_BLANK_LINES_AT_TOP 0x0430
  209. #define OV0_P23_BLANK_LINES_AT_TOP 0x0434
  210. #define OV0_BASE_ADDR 0x043C
  211. #define OV0_VID_BUF0_BASE_ADRS 0x0440
  212. #define OV0_VID_BUF1_BASE_ADRS 0x0444
  213. #define OV0_VID_BUF2_BASE_ADRS 0x0448
  214. #define OV0_VID_BUF3_BASE_ADRS 0x044C
  215. #define OV0_VID_BUF4_BASE_ADRS 0x0450
  216. #define OV0_VID_BUF5_BASE_ADRS 0x0454
  217. #define OV0_VID_BUF_PITCH0_VALUE 0x0460
  218. #define OV0_VID_BUF_PITCH1_VALUE 0x0464
  219. #define OV0_AUTO_FLIP_CNTRL 0x0470
  220. #define OV0_DEINTERLACE_PATTERN 0x0474
  221. #define OV0_SUBMIT_HISTORY 0x0478
  222. #define OV0_H_INC 0x0480
  223. #define OV0_STEP_BY 0x0484
  224. #define OV0_P1_H_ACCUM_INIT 0x0488
  225. #define OV0_P23_H_ACCUM_INIT 0x048C
  226. #define OV0_P1_X_START_END 0x0494
  227. #define OV0_P2_X_START_END 0x0498
  228. #define OV0_P3_X_START_END 0x049C
  229. #define OV0_FILTER_CNTL 0x04A0
  230. #define OV0_FOUR_TAP_COEF_0 0x04B0
  231. #define OV0_FOUR_TAP_COEF_1 0x04B4
  232. #define OV0_FOUR_TAP_COEF_2 0x04B8
  233. #define OV0_FOUR_TAP_COEF_3 0x04BC
  234. #define OV0_FOUR_TAP_COEF_4 0x04C0
  235. #define OV0_FLAG_CNTRL 0x04DC
  236. #define OV0_SLICE_CNTL 0x04E0
  237. #define OV0_VID_KEY_CLR_LOW 0x04E4
  238. #define OV0_VID_KEY_CLR_HIGH 0x04E8
  239. #define OV0_GRPH_KEY_CLR_LOW 0x04EC
  240. #define OV0_GRPH_KEY_CLR_HIGH 0x04F0
  241. #define OV0_KEY_CNTL 0x04F4
  242. #define OV0_TEST 0x04F8
  243. #define SUBPIC_CNTL 0x0540
  244. #define SUBPIC_DEFCOLCON 0x0544
  245. #define SUBPIC_Y_X_START 0x054C
  246. #define SUBPIC_Y_X_END 0x0550
  247. #define SUBPIC_V_INC 0x0554
  248. #define SUBPIC_H_INC 0x0558
  249. #define SUBPIC_BUF0_OFFSET 0x055C
  250. #define SUBPIC_BUF1_OFFSET 0x0560
  251. #define SUBPIC_LC0_OFFSET 0x0564
  252. #define SUBPIC_LC1_OFFSET 0x0568
  253. #define SUBPIC_PITCH 0x056C
  254. #define SUBPIC_BTN_HLI_COLCON 0x0570
  255. #define SUBPIC_BTN_HLI_Y_X_START 0x0574
  256. #define SUBPIC_BTN_HLI_Y_X_END 0x0578
  257. #define SUBPIC_PALETTE_INDEX 0x057C
  258. #define SUBPIC_PALETTE_DATA 0x0580
  259. #define SUBPIC_H_ACCUM_INIT 0x0584
  260. #define SUBPIC_V_ACCUM_INIT 0x0588
  261. #define DISP_MISC_CNTL 0x0D00
  262. #define DAC_MACRO_CNTL 0x0D04
  263. #define DISP_PWR_MAN 0x0D08
  264. #define DISP_TEST_DEBUG_CNTL 0x0D10
  265. #define DISP_HW_DEBUG 0x0D14
  266. #define DAC_CRC_SIG1 0x0D18
  267. #define DAC_CRC_SIG2 0x0D1C
  268. #define OV0_LIN_TRANS_A 0x0D20
  269. #define OV0_LIN_TRANS_B 0x0D24
  270. #define OV0_LIN_TRANS_C 0x0D28
  271. #define OV0_LIN_TRANS_D 0x0D2C
  272. #define OV0_LIN_TRANS_E 0x0D30
  273. #define OV0_LIN_TRANS_F 0x0D34
  274. #define OV0_GAMMA_0_F 0x0D40
  275. #define OV0_GAMMA_10_1F 0x0D44
  276. #define OV0_GAMMA_20_3F 0x0D48
  277. #define OV0_GAMMA_40_7F 0x0D4C
  278. #define OV0_GAMMA_380_3BF 0x0D50
  279. #define OV0_GAMMA_3C0_3FF 0x0D54
  280. #define DISP_MERGE_CNTL 0x0D60
  281. #define DISP_OUTPUT_CNTL 0x0D64
  282. #define DISP_LIN_TRANS_GRPH_A 0x0D80
  283. #define DISP_LIN_TRANS_GRPH_B 0x0D84
  284. #define DISP_LIN_TRANS_GRPH_C 0x0D88
  285. #define DISP_LIN_TRANS_GRPH_D 0x0D8C
  286. #define DISP_LIN_TRANS_GRPH_E 0x0D90
  287. #define DISP_LIN_TRANS_GRPH_F 0x0D94
  288. #define DISP_LIN_TRANS_VID_A 0x0D98
  289. #define DISP_LIN_TRANS_VID_B 0x0D9C
  290. #define DISP_LIN_TRANS_VID_C 0x0DA0
  291. #define DISP_LIN_TRANS_VID_D 0x0DA4
  292. #define DISP_LIN_TRANS_VID_E 0x0DA8
  293. #define DISP_LIN_TRANS_VID_F 0x0DAC
  294. #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
  295. #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
  296. #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
  297. #define RMX_HORZ_PHASE 0x0DBC
  298. #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
  299. #define DAC_BROAD_PULSE 0x0DC4
  300. #define DAC_SKEW_CLKS 0x0DC8
  301. #define DAC_INCR 0x0DCC
  302. #define DAC_NEG_SYNC_LEVEL 0x0DD0
  303. #define DAC_POS_SYNC_LEVEL 0x0DD4
  304. #define DAC_BLANK_LEVEL 0x0DD8
  305. #define CLOCK_CNTL_INDEX 0x0008
  306. #define CLOCK_CNTL_DATA 0x000C
  307. #define CP_RB_CNTL 0x0704
  308. #define CP_RB_BASE 0x0700
  309. #define CP_RB_RPTR_ADDR 0x070C
  310. #define CP_RB_RPTR 0x0710
  311. #define CP_RB_WPTR 0x0714
  312. #define CP_RB_WPTR_DELAY 0x0718
  313. #define CP_IB_BASE 0x0738
  314. #define CP_IB_BUFSZ 0x073C
  315. #define SCRATCH_REG0 0x15E0
  316. #define GUI_SCRATCH_REG0 0x15E0
  317. #define SCRATCH_REG1 0x15E4
  318. #define GUI_SCRATCH_REG1 0x15E4
  319. #define SCRATCH_REG2 0x15E8
  320. #define GUI_SCRATCH_REG2 0x15E8
  321. #define SCRATCH_REG3 0x15EC
  322. #define GUI_SCRATCH_REG3 0x15EC
  323. #define SCRATCH_REG4 0x15F0
  324. #define GUI_SCRATCH_REG4 0x15F0
  325. #define SCRATCH_REG5 0x15F4
  326. #define GUI_SCRATCH_REG5 0x15F4
  327. #define SCRATCH_UMSK 0x0770
  328. #define SCRATCH_ADDR 0x0774
  329. #define DP_BRUSH_FRGD_CLR 0x147C
  330. #define DP_BRUSH_BKGD_CLR 0x1478
  331. #define DST_LINE_START 0x1600
  332. #define DST_LINE_END 0x1604
  333. #define SRC_OFFSET 0x15AC
  334. #define SRC_PITCH 0x15B0
  335. #define SRC_TILE 0x1704
  336. #define SRC_PITCH_OFFSET 0x1428
  337. #define SRC_X 0x1414
  338. #define SRC_Y 0x1418
  339. #define SRC_X_Y 0x1590
  340. #define SRC_Y_X 0x1434
  341. #define DST_Y_X 0x1438
  342. #define DST_WIDTH_HEIGHT 0x1598
  343. #define DST_HEIGHT_WIDTH 0x143c
  344. #define DST_OFFSET 0x1404
  345. #define SRC_CLUT_ADDRESS 0x1780
  346. #define SRC_CLUT_DATA 0x1784
  347. #define SRC_CLUT_DATA_RD 0x1788
  348. #define HOST_DATA0 0x17C0
  349. #define HOST_DATA1 0x17C4
  350. #define HOST_DATA2 0x17C8
  351. #define HOST_DATA3 0x17CC
  352. #define HOST_DATA4 0x17D0
  353. #define HOST_DATA5 0x17D4
  354. #define HOST_DATA6 0x17D8
  355. #define HOST_DATA7 0x17DC
  356. #define HOST_DATA_LAST 0x17E0
  357. #define DP_SRC_ENDIAN 0x15D4
  358. #define DP_SRC_FRGD_CLR 0x15D8
  359. #define DP_SRC_BKGD_CLR 0x15DC
  360. #define SC_LEFT 0x1640
  361. #define SC_RIGHT 0x1644
  362. #define SC_TOP 0x1648
  363. #define SC_BOTTOM 0x164C
  364. #define SRC_SC_RIGHT 0x1654
  365. #define SRC_SC_BOTTOM 0x165C
  366. #define DP_CNTL 0x16C0
  367. #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
  368. #define DP_DATATYPE 0x16C4
  369. #define DP_MIX 0x16C8
  370. #define DP_WRITE_MSK 0x16CC
  371. #define DP_XOP 0x17F8
  372. #define CLR_CMP_CLR_SRC 0x15C4
  373. #define CLR_CMP_CLR_DST 0x15C8
  374. #define CLR_CMP_CNTL 0x15C0
  375. #define CLR_CMP_MSK 0x15CC
  376. #define DSTCACHE_MODE 0x1710
  377. #define DSTCACHE_CTLSTAT 0x1714
  378. #define DEFAULT_PITCH_OFFSET 0x16E0
  379. #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
  380. #define DEFAULT_SC_TOP_LEFT 0x16EC
  381. #define SRC_PITCH_OFFSET 0x1428
  382. #define DST_PITCH_OFFSET 0x142C
  383. #define DP_GUI_MASTER_CNTL 0x146C
  384. #define SC_TOP_LEFT 0x16EC
  385. #define SC_BOTTOM_RIGHT 0x16F0
  386. #define SRC_SC_BOTTOM_RIGHT 0x16F4
  387. #define RB2D_DSTCACHE_MODE 0x3428
  388. #define RB2D_DSTCACHE_CTLSTAT 0x342C
  389. #define LVDS_GEN_CNTL 0x02d0
  390. #define LVDS_PLL_CNTL 0x02d4
  391. #define FP2_GEN_CNTL 0x0288
  392. #define TMDS_CNTL 0x0294
  393. #define TMDS_CRC 0x02a0
  394. #define TMDS_TRANSMITTER_CNTL 0x02a4
  395. #define MPP_TB_CONFIG 0x01c0
  396. #define PAMAC0_DLY_CNTL 0x0a94
  397. #define PAMAC1_DLY_CNTL 0x0a98
  398. #define PAMAC2_DLY_CNTL 0x0a9c
  399. #define FW_CNTL 0x0118
  400. #define FCP_CNTL 0x0910
  401. #define VGA_DDA_ON_OFF 0x02ec
  402. #define TV_MASTER_CNTL 0x0800
  403. /* #define BASE_CODE 0x0f0b */
  404. #define BIOS_0_SCRATCH 0x0010
  405. #define BIOS_1_SCRATCH 0x0014
  406. #define BIOS_2_SCRATCH 0x0018
  407. #define BIOS_3_SCRATCH 0x001c
  408. #define BIOS_4_SCRATCH 0x0020
  409. #define BIOS_5_SCRATCH 0x0024
  410. #define BIOS_6_SCRATCH 0x0028
  411. #define BIOS_7_SCRATCH 0x002c
  412. #define HDP_SOFT_RESET (1 << 26)
  413. #define TV_DAC_CNTL 0x088c
  414. #define GPIOPAD_MASK 0x0198
  415. #define GPIOPAD_A 0x019c
  416. #define GPIOPAD_EN 0x01a0
  417. #define GPIOPAD_Y 0x01a4
  418. #define ZV_LCDPAD_MASK 0x01a8
  419. #define ZV_LCDPAD_A 0x01ac
  420. #define ZV_LCDPAD_EN 0x01b0
  421. #define ZV_LCDPAD_Y 0x01b4
  422. /* PLL Registers */
  423. #define CLK_PIN_CNTL 0x0001
  424. #define PPLL_CNTL 0x0002
  425. #define PPLL_REF_DIV 0x0003
  426. #define PPLL_DIV_0 0x0004
  427. #define PPLL_DIV_1 0x0005
  428. #define PPLL_DIV_2 0x0006
  429. #define PPLL_DIV_3 0x0007
  430. #define VCLK_ECP_CNTL 0x0008
  431. #define HTOTAL_CNTL 0x0009
  432. #define M_SPLL_REF_FB_DIV 0x000a
  433. #define AGP_PLL_CNTL 0x000b
  434. #define SPLL_CNTL 0x000c
  435. #define SCLK_CNTL 0x000d
  436. #define MPLL_CNTL 0x000e
  437. #define MDLL_CKO 0x000f
  438. #define MDLL_RDCKA 0x0010
  439. #define MCLK_CNTL 0x0012
  440. #define AGP_PLL_CNTL 0x000b
  441. #define PLL_TEST_CNTL 0x0013
  442. #define CLK_PWRMGT_CNTL 0x0014
  443. #define PLL_PWRMGT_CNTL 0x0015
  444. #define MCLK_MISC 0x001f
  445. #define P2PLL_CNTL 0x002a
  446. #define P2PLL_REF_DIV 0x002b
  447. #define PIXCLKS_CNTL 0x002d
  448. #define SCLK_MORE_CNTL 0x0035
  449. /* MCLK_CNTL bit constants */
  450. #define FORCEON_MCLKA (1 << 16)
  451. #define FORCEON_MCLKB (1 << 17)
  452. #define FORCEON_YCLKA (1 << 18)
  453. #define FORCEON_YCLKB (1 << 19)
  454. #define FORCEON_MC (1 << 20)
  455. #define FORCEON_AIC (1 << 21)
  456. /* SCLK_CNTL bit constants */
  457. #define DYN_STOP_LAT_MASK 0x00007ff8
  458. #define CP_MAX_DYN_STOP_LAT 0x0008
  459. #define SCLK_FORCEON_MASK 0xffff8000
  460. /* SCLK_MORE_CNTL bit constants */
  461. #define SCLK_MORE_FORCEON 0x0700
  462. /* BUS_CNTL bit constants */
  463. #define BUS_DBL_RESYNC 0x00000001
  464. #define BUS_MSTR_RESET 0x00000002
  465. #define BUS_FLUSH_BUF 0x00000004
  466. #define BUS_STOP_REQ_DIS 0x00000008
  467. #define BUS_ROTATION_DIS 0x00000010
  468. #define BUS_MASTER_DIS 0x00000040
  469. #define BUS_ROM_WRT_EN 0x00000080
  470. #define BUS_DIS_ROM 0x00001000
  471. #define BUS_PCI_READ_RETRY_EN 0x00002000
  472. #define BUS_AGP_AD_STEPPING_EN 0x00004000
  473. #define BUS_PCI_WRT_RETRY_EN 0x00008000
  474. #define BUS_MSTR_RD_MULT 0x00100000
  475. #define BUS_MSTR_RD_LINE 0x00200000
  476. #define BUS_SUSPEND 0x00400000
  477. #define LAT_16X 0x00800000
  478. #define BUS_RD_DISCARD_EN 0x01000000
  479. #define BUS_RD_ABORT_EN 0x02000000
  480. #define BUS_MSTR_WS 0x04000000
  481. #define BUS_PARKING_DIS 0x08000000
  482. #define BUS_MSTR_DISCONNECT_EN 0x10000000
  483. #define BUS_WRT_BURST 0x20000000
  484. #define BUS_READ_BURST 0x40000000
  485. #define BUS_RDY_READ_DLY 0x80000000
  486. /* PIXCLKS_CNTL */
  487. #define PIX2CLK_SRC_SEL_MASK 0x03
  488. #define PIX2CLK_SRC_SEL_CPUCLK 0x00
  489. #define PIX2CLK_SRC_SEL_PSCANCLK 0x01
  490. #define PIX2CLK_SRC_SEL_BYTECLK 0x02
  491. #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
  492. #define PIX2CLK_ALWAYS_ONb (1<<6)
  493. #define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
  494. #define PIXCLK_TV_SRC_SEL (1 << 8)
  495. #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
  496. #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
  497. /* CLOCK_CNTL_INDEX bit constants */
  498. #define PLL_WR_EN 0x00000080
  499. /* CONFIG_CNTL bit constants */
  500. #define CONFIG_SYS_VGA_RAM_EN 0x00000100
  501. #define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16)
  502. #define CONFIG_SYS_ATI_REV_A11 (0 << 16)
  503. #define CONFIG_SYS_ATI_REV_A12 (1 << 16)
  504. #define CONFIG_SYS_ATI_REV_A13 (2 << 16)
  505. /* CRTC_EXT_CNTL bit constants */
  506. #define VGA_ATI_LINEAR 0x00000008
  507. #define VGA_128KAP_PAGING 0x00000010
  508. #define XCRT_CNT_EN (1 << 6)
  509. #define CRTC_HSYNC_DIS (1 << 8)
  510. #define CRTC_VSYNC_DIS (1 << 9)
  511. #define CRTC_DISPLAY_DIS (1 << 10)
  512. #define CRTC_CRT_ON (1 << 15)
  513. /* DSTCACHE_CTLSTAT bit constants */
  514. #define RB2D_DC_FLUSH (3 << 0)
  515. #define RB2D_DC_FLUSH_ALL 0xf
  516. #define RB2D_DC_BUSY (1 << 31)
  517. /* CRTC_GEN_CNTL bit constants */
  518. #define CRTC_DBL_SCAN_EN 0x00000001
  519. #define CRTC_CUR_EN 0x00010000
  520. #define CRTC_INTERLACE_EN (1 << 1)
  521. #define CRTC_BYPASS_LUT_EN (1 << 14)
  522. #define CRTC_EXT_DISP_EN (1 << 24)
  523. #define CRTC_EN (1 << 25)
  524. #define CRTC_DISP_REQ_EN_B (1 << 26)
  525. /* CRTC_STATUS bit constants */
  526. #define CRTC_VBLANK 0x00000001
  527. /* CRTC2_GEN_CNTL bit constants */
  528. #define CRT2_ON (1 << 7)
  529. #define CRTC2_DISPLAY_DIS (1 << 23)
  530. #define CRTC2_EN (1 << 25)
  531. #define CRTC2_DISP_REQ_EN_B (1 << 26)
  532. /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
  533. #define CUR_LOCK 0x80000000
  534. /* GPIO bit constants */
  535. #define GPIO_A_0 (1 << 0)
  536. #define GPIO_A_1 (1 << 1)
  537. #define GPIO_Y_0 (1 << 8)
  538. #define GPIO_Y_1 (1 << 9)
  539. #define GPIO_EN_0 (1 << 16)
  540. #define GPIO_EN_1 (1 << 17)
  541. #define GPIO_MASK_0 (1 << 24)
  542. #define GPIO_MASK_1 (1 << 25)
  543. #define VGA_DDC_DATA_OUTPUT GPIO_A_0
  544. #define VGA_DDC_CLK_OUTPUT GPIO_A_1
  545. #define VGA_DDC_DATA_INPUT GPIO_Y_0
  546. #define VGA_DDC_CLK_INPUT GPIO_Y_1
  547. #define VGA_DDC_DATA_OUT_EN GPIO_EN_0
  548. #define VGA_DDC_CLK_OUT_EN GPIO_EN_1
  549. /* FP bit constants */
  550. #define FP_CRTC_H_TOTAL_MASK 000003ff
  551. #define FP_CRTC_H_DISP_MASK 0x01ff0000
  552. #define FP_CRTC_V_TOTAL_MASK 0x00000fff
  553. #define FP_CRTC_V_DISP_MASK 0x0fff0000
  554. #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
  555. #define FP_H_SYNC_WID_MASK 0x003f0000
  556. #define FP_V_SYNC_STRT_MASK 0x00000fff
  557. #define FP_V_SYNC_WID_MASK 0x001f0000
  558. #define FP_CRTC_H_TOTAL_SHIFT 0x00000000
  559. #define FP_CRTC_H_DISP_SHIFT 0x00000010
  560. #define FP_CRTC_V_TOTAL_SHIFT 0x00000000
  561. #define FP_CRTC_V_DISP_SHIFT 0x00000010
  562. #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
  563. #define FP_H_SYNC_WID_SHIFT 0x00000010
  564. #define FP_V_SYNC_STRT_SHIFT 0x00000000
  565. #define FP_V_SYNC_WID_SHIFT 0x00000010
  566. /* FP_GEN_CNTL bit constants */
  567. #define FP_FPON (1 << 0)
  568. #define FP_TMDS_EN (1 << 2)
  569. #define FP_PANEL_FORMAT (1 << 3)
  570. #define FP_EN_TMDS (1 << 7)
  571. #define FP_DETECT_SENSE (1 << 8)
  572. #define R200_FP_SOURCE_SEL_MASK (3 << 10)
  573. #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
  574. #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
  575. #define R200_FP_SOURCE_SEL_RMX (2 << 10)
  576. #define R200_FP_SOURCE_SEL_TRANS (3 << 10)
  577. #define FP_SEL_CRTC1 (0 << 13)
  578. #define FP_SEL_CRTC2 (1 << 13)
  579. #define FP_USE_VGA_HSYNC (1 << 14)
  580. #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
  581. #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
  582. #define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
  583. #define FP_CRTC_USE_SHADOW_VEND (1 << 18)
  584. #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
  585. #define FP_DFP_SYNC_SEL (1 << 21)
  586. #define FP_CRTC_LOCK_8DOT (1 << 22)
  587. #define FP_CRT_SYNC_SEL (1 << 23)
  588. #define FP_USE_SHADOW_EN (1 << 24)
  589. #define FP_CRT_SYNC_ALT (1 << 26)
  590. /* FP2_GEN_CNTL bit constants */
  591. #define FP2_BLANK_EN (1 << 1)
  592. #define FP2_ON (1 << 2)
  593. #define FP2_PANEL_FORMAT (1 << 3)
  594. #define FP2_SOURCE_SEL_MASK (3 << 10)
  595. #define FP2_SOURCE_SEL_CRTC2 (1 << 10)
  596. #define FP2_SRC_SEL_MASK (3 << 13)
  597. #define FP2_SRC_SEL_CRTC2 (1 << 13)
  598. #define FP2_FP_POL (1 << 16)
  599. #define FP2_LP_POL (1 << 17)
  600. #define FP2_SCK_POL (1 << 18)
  601. #define FP2_LCD_CNTL_MASK (7 << 19)
  602. #define FP2_PAD_FLOP_EN (1 << 22)
  603. #define FP2_CRC_EN (1 << 23)
  604. #define FP2_CRC_READ_EN (1 << 24)
  605. #define FP2_DV0_EN (1 << 25)
  606. #define FP2_DV0_RATE_SEL_SDR (1 << 26)
  607. /* LVDS_GEN_CNTL bit constants */
  608. #define LVDS_ON (1 << 0)
  609. #define LVDS_DISPLAY_DIS (1 << 1)
  610. #define LVDS_PANEL_TYPE (1 << 2)
  611. #define LVDS_PANEL_FORMAT (1 << 3)
  612. #define LVDS_EN (1 << 7)
  613. #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
  614. #define LVDS_BL_MOD_LEVEL_SHIFT 8
  615. #define LVDS_BL_MOD_EN (1 << 16)
  616. #define LVDS_DIGON (1 << 18)
  617. #define LVDS_BLON (1 << 19)
  618. #define LVDS_SEL_CRTC2 (1 << 23)
  619. #define LVDS_STATE_MASK \
  620. (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
  621. /* LVDS_PLL_CNTL bit constatns */
  622. #define HSYNC_DELAY_SHIFT 0x1c
  623. #define HSYNC_DELAY_MASK (0xf << 0x1c)
  624. /* TMDS_TRANSMITTER_CNTL bit constants */
  625. #define TMDS_PLL_EN (1 << 0)
  626. #define TMDS_PLLRST (1 << 1)
  627. #define TMDS_RAN_PAT_RST (1 << 7)
  628. #define TMDS_ICHCSEL (1 << 28)
  629. /* FP_HORZ_STRETCH bit constants */
  630. #define HORZ_STRETCH_RATIO_MASK 0xffff
  631. #define HORZ_STRETCH_RATIO_MAX 4096
  632. #define HORZ_PANEL_SIZE (0x1ff << 16)
  633. #define HORZ_PANEL_SHIFT 16
  634. #define HORZ_STRETCH_PIXREP (0 << 25)
  635. #define HORZ_STRETCH_BLEND (1 << 26)
  636. #define HORZ_STRETCH_ENABLE (1 << 25)
  637. #define HORZ_AUTO_RATIO (1 << 27)
  638. #define HORZ_FP_LOOP_STRETCH (0x7 << 28)
  639. #define HORZ_AUTO_RATIO_INC (1 << 31)
  640. /* FP_VERT_STRETCH bit constants */
  641. #define VERT_STRETCH_RATIO_MASK 0xfff
  642. #define VERT_STRETCH_RATIO_MAX 4096
  643. #define VERT_PANEL_SIZE (0xfff << 12)
  644. #define VERT_PANEL_SHIFT 12
  645. #define VERT_STRETCH_LINREP (0 << 26)
  646. #define VERT_STRETCH_BLEND (1 << 26)
  647. #define VERT_STRETCH_ENABLE (1 << 25)
  648. #define VERT_AUTO_RATIO_EN (1 << 27)
  649. #define VERT_FP_LOOP_STRETCH (0x7 << 28)
  650. #define VERT_STRETCH_RESERVED 0xf1000000
  651. /* DAC_CNTL bit constants */
  652. #define DAC_8BIT_EN 0x00000100
  653. #define DAC_4BPP_PIX_ORDER 0x00000200
  654. #define DAC_CRC_EN 0x00080000
  655. #define DAC_MASK_ALL (0xff << 24)
  656. #define DAC_PDWN (1 << 15)
  657. #define DAC_EXPAND_MODE (1 << 14)
  658. #define DAC_VGA_ADR_EN (1 << 13)
  659. #define DAC_RANGE_CNTL (3 << 0)
  660. #define DAC_RANGE_CNTL_MASK 0x03
  661. #define DAC_BLANKING (1 << 2)
  662. #define DAC_CMP_EN (1 << 3)
  663. #define DAC_CMP_OUTPUT (1 << 7)
  664. /* DAC_CNTL2 bit constants */
  665. #define DAC2_EXPAND_MODE (1 << 14)
  666. #define DAC2_CMP_EN (1 << 7)
  667. #define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
  668. /* DAC_EXT_CNTL bit constants */
  669. #define DAC_FORCE_BLANK_OFF_EN (1 << 4)
  670. #define DAC_FORCE_DATA_EN (1 << 5)
  671. #define DAC_FORCE_DATA_SEL_MASK (3 << 6)
  672. #define DAC_FORCE_DATA_MASK 0x0003ff00
  673. #define DAC_FORCE_DATA_SHIFT 8
  674. /* GEN_RESET_CNTL bit constants */
  675. #define SOFT_RESET_GUI 0x00000001
  676. #define SOFT_RESET_VCLK 0x00000100
  677. #define SOFT_RESET_PCLK 0x00000200
  678. #define SOFT_RESET_ECP 0x00000400
  679. #define SOFT_RESET_DISPENG_XCLK 0x00000800
  680. /* MEM_CNTL bit constants */
  681. #define MEM_CTLR_STATUS_IDLE 0x00000000
  682. #define MEM_CTLR_STATUS_BUSY 0x00100000
  683. #define MEM_SEQNCR_STATUS_IDLE 0x00000000
  684. #define MEM_SEQNCR_STATUS_BUSY 0x00200000
  685. #define MEM_ARBITER_STATUS_IDLE 0x00000000
  686. #define MEM_ARBITER_STATUS_BUSY 0x00400000
  687. #define MEM_REQ_UNLOCK 0x00000000
  688. #define MEM_REQ_LOCK 0x00800000
  689. #define MEM_NUM_CHANNELS_MASK 0x00000001
  690. #define MEM_USE_B_CH_ONLY 0x00000002
  691. #define RV100_MEM_HALF_MODE 0x00000008
  692. #define R300_MEM_NUM_CHANNELS_MASK 0x00000003
  693. #define R300_MEM_USE_CD_CH_ONLY 0x00000004
  694. /* RBBM_SOFT_RESET bit constants */
  695. #define SOFT_RESET_CP (1 << 0)
  696. #define SOFT_RESET_HI (1 << 1)
  697. #define SOFT_RESET_SE (1 << 2)
  698. #define SOFT_RESET_RE (1 << 3)
  699. #define SOFT_RESET_PP (1 << 4)
  700. #define SOFT_RESET_E2 (1 << 5)
  701. #define SOFT_RESET_RB (1 << 6)
  702. #define SOFT_RESET_HDP (1 << 7)
  703. /* SURFACE_CNTL bit consants */
  704. #define SURF_TRANSLATION_DIS (1 << 8)
  705. #define NONSURF_AP0_SWP_16BPP (1 << 20)
  706. #define NONSURF_AP0_SWP_32BPP (1 << 21)
  707. #define NONSURF_AP1_SWP_16BPP (1 << 22)
  708. #define NONSURF_AP1_SWP_32BPP (1 << 23)
  709. #define R200_SURF_TILE_COLOR_MACRO (1 << 16)
  710. /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
  711. #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
  712. #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
  713. /* MM_INDEX bit constants */
  714. #define MM_APER 0x80000000
  715. /* CLR_CMP_CNTL bit constants */
  716. #define COMPARE_SRC_FALSE 0x00000000
  717. #define COMPARE_SRC_TRUE 0x00000001
  718. #define COMPARE_SRC_NOT_EQUAL 0x00000004
  719. #define COMPARE_SRC_EQUAL 0x00000005
  720. #define COMPARE_SRC_EQUAL_FLIP 0x00000007
  721. #define COMPARE_DST_FALSE 0x00000000
  722. #define COMPARE_DST_TRUE 0x00000100
  723. #define COMPARE_DST_NOT_EQUAL 0x00000400
  724. #define COMPARE_DST_EQUAL 0x00000500
  725. #define COMPARE_DESTINATION 0x00000000
  726. #define COMPARE_SOURCE 0x01000000
  727. #define COMPARE_SRC_AND_DST 0x02000000
  728. /* DP_CNTL bit constants */
  729. #define DST_X_RIGHT_TO_LEFT 0x00000000
  730. #define DST_X_LEFT_TO_RIGHT 0x00000001
  731. #define DST_Y_BOTTOM_TO_TOP 0x00000000
  732. #define DST_Y_TOP_TO_BOTTOM 0x00000002
  733. #define DST_X_MAJOR 0x00000000
  734. #define DST_Y_MAJOR 0x00000004
  735. #define DST_X_TILE 0x00000008
  736. #define DST_Y_TILE 0x00000010
  737. #define DST_LAST_PEL 0x00000020
  738. #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
  739. #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
  740. #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
  741. #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
  742. #define DST_BRES_SIGN 0x00000100
  743. #define DST_HOST_BIG_ENDIAN_EN 0x00000200
  744. #define DST_POLYLINE_NONLAST 0x00008000
  745. #define DST_RASTER_STALL 0x00010000
  746. #define DST_POLY_EDGE 0x00040000
  747. /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
  748. #define DST_X_MAJOR_S 0x00000000
  749. #define DST_Y_MAJOR_S 0x00000001
  750. #define DST_Y_BOTTOM_TO_TOP_S 0x00000000
  751. #define DST_Y_TOP_TO_BOTTOM_S 0x00008000
  752. #define DST_X_RIGHT_TO_LEFT_S 0x00000000
  753. #define DST_X_LEFT_TO_RIGHT_S 0x80000000
  754. /* DP_DATATYPE bit constants */
  755. #define DST_8BPP 0x00000002
  756. #define DST_15BPP 0x00000003
  757. #define DST_16BPP 0x00000004
  758. #define DST_24BPP 0x00000005
  759. #define DST_32BPP 0x00000006
  760. #define DST_8BPP_RGB332 0x00000007
  761. #define DST_8BPP_Y8 0x00000008
  762. #define DST_8BPP_RGB8 0x00000009
  763. #define DST_16BPP_VYUY422 0x0000000b
  764. #define DST_16BPP_YVYU422 0x0000000c
  765. #define DST_32BPP_AYUV444 0x0000000e
  766. #define DST_16BPP_ARGB4444 0x0000000f
  767. #define BRUSH_SOLIDCOLOR 0x00000d00
  768. #define SRC_MONO 0x00000000
  769. #define SRC_MONO_LBKGD 0x00010000
  770. #define SRC_DSTCOLOR 0x00030000
  771. #define BYTE_ORDER_MSB_TO_LSB 0x00000000
  772. #define BYTE_ORDER_LSB_TO_MSB 0x40000000
  773. #define DP_CONVERSION_TEMP 0x80000000
  774. #define HOST_BIG_ENDIAN_EN (1 << 29)
  775. /* DP_GUI_MASTER_CNTL bit constants */
  776. #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
  777. #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
  778. #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
  779. #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
  780. #define GMC_SRC_CLIP_DEFAULT 0x00000000
  781. #define GMC_SRC_CLIP_LEAVE 0x00000004
  782. #define GMC_DST_CLIP_DEFAULT 0x00000000
  783. #define GMC_DST_CLIP_LEAVE 0x00000008
  784. #define GMC_BRUSH_8x8MONO 0x00000000
  785. #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
  786. #define GMC_BRUSH_8x1MONO 0x00000020
  787. #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
  788. #define GMC_BRUSH_1x8MONO 0x00000040
  789. #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
  790. #define GMC_BRUSH_32x1MONO 0x00000060
  791. #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
  792. #define GMC_BRUSH_32x32MONO 0x00000080
  793. #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
  794. #define GMC_BRUSH_8x8COLOR 0x000000a0
  795. #define GMC_BRUSH_8x1COLOR 0x000000b0
  796. #define GMC_BRUSH_1x8COLOR 0x000000c0
  797. #define GMC_BRUSH_SOLID_COLOR 0x000000d0
  798. #define GMC_DST_8BPP 0x00000200
  799. #define GMC_DST_15BPP 0x00000300
  800. #define GMC_DST_16BPP 0x00000400
  801. #define GMC_DST_24BPP 0x00000500
  802. #define GMC_DST_32BPP 0x00000600
  803. #define GMC_DST_8BPP_RGB332 0x00000700
  804. #define GMC_DST_8BPP_Y8 0x00000800
  805. #define GMC_DST_8BPP_RGB8 0x00000900
  806. #define GMC_DST_16BPP_VYUY422 0x00000b00
  807. #define GMC_DST_16BPP_YVYU422 0x00000c00
  808. #define GMC_DST_32BPP_AYUV444 0x00000e00
  809. #define GMC_DST_16BPP_ARGB4444 0x00000f00
  810. #define GMC_SRC_MONO 0x00000000
  811. #define GMC_SRC_MONO_LBKGD 0x00001000
  812. #define GMC_SRC_DSTCOLOR 0x00003000
  813. #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
  814. #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
  815. #define GMC_DP_CONVERSION_TEMP_9300 0x00008000
  816. #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
  817. #define GMC_DP_SRC_RECT 0x02000000
  818. #define GMC_DP_SRC_HOST 0x03000000
  819. #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
  820. #define GMC_3D_FCN_EN_CLR 0x00000000
  821. #define GMC_3D_FCN_EN_SET 0x08000000
  822. #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
  823. #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
  824. #define GMC_AUX_CLIP_LEAVE 0x00000000
  825. #define GMC_AUX_CLIP_CLEAR 0x20000000
  826. #define GMC_WRITE_MASK_LEAVE 0x00000000
  827. #define GMC_WRITE_MASK_SET 0x40000000
  828. #define GMC_CLR_CMP_CNTL_DIS (1 << 28)
  829. #define GMC_SRC_DATATYPE_COLOR (3 << 12)
  830. #define ROP3_S 0x00cc0000
  831. #define ROP3_SRCCOPY 0x00cc0000
  832. #define ROP3_P 0x00f00000
  833. #define ROP3_PATCOPY 0x00f00000
  834. #define DP_SRC_SOURCE_MASK (7 << 24)
  835. #define GMC_BRUSH_NONE (15 << 4)
  836. #define DP_SRC_SOURCE_MEMORY (2 << 24)
  837. #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
  838. /* DP_MIX bit constants */
  839. #define DP_SRC_RECT 0x00000200
  840. #define DP_SRC_HOST 0x00000300
  841. #define DP_SRC_HOST_BYTEALIGN 0x00000400
  842. /* MPLL_CNTL bit constants */
  843. #define MPLL_RESET 0x00000001
  844. /* MDLL_CKO bit constants */
  845. #define MCKOA_SLEEP 0x00000001
  846. #define MCKOA_RESET 0x00000002
  847. #define MCKOA_REF_SKEW_MASK 0x00000700
  848. #define MCKOA_FB_SKEW_MASK 0x00007000
  849. /* MDLL_RDCKA bit constants */
  850. #define MRDCKA0_SLEEP 0x00000001
  851. #define MRDCKA0_RESET 0x00000002
  852. #define MRDCKA1_SLEEP 0x00010000
  853. #define MRDCKA1_RESET 0x00020000
  854. /* VCLK_ECP_CNTL constants */
  855. #define VCLK_SRC_SEL_MASK 0x03
  856. #define VCLK_SRC_SEL_CPUCLK 0x00
  857. #define VCLK_SRC_SEL_PSCANCLK 0x01
  858. #define VCLK_SRC_SEL_BYTECLK 0x02
  859. #define VCLK_SRC_SEL_PPLLCLK 0x03
  860. #define PIXCLK_ALWAYS_ONb 0x00000040
  861. #define PIXCLK_DAC_ALWAYS_ONb 0x00000080
  862. /* BUS_CNTL1 constants */
  863. #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
  864. #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
  865. #define BUS_CNTL1_AGPCLK_VALID 0x80000000
  866. /* PLL_PWRMGT_CNTL constants */
  867. #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
  868. #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
  869. #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
  870. #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
  871. #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
  872. #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
  873. #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
  874. /* TV_DAC_CNTL constants */
  875. #define TV_DAC_CNTL_BGSLEEP 0x00000040
  876. #define TV_DAC_CNTL_DETECT 0x00000010
  877. #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
  878. #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
  879. #define TV_DAC_CNTL_BGADJ__SHIFT 16
  880. #define TV_DAC_CNTL_DACADJ__SHIFT 20
  881. #define TV_DAC_CNTL_RDACPD 0x01000000
  882. #define TV_DAC_CNTL_GDACPD 0x02000000
  883. #define TV_DAC_CNTL_BDACPD 0x04000000
  884. /* DISP_MISC_CNTL constants */
  885. #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
  886. #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
  887. #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
  888. #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
  889. #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
  890. #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
  891. #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
  892. #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
  893. #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
  894. #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
  895. #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
  896. #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
  897. /* DISP_PWR_MAN constants */
  898. #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
  899. #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
  900. #define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
  901. #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
  902. #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
  903. #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
  904. #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
  905. #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
  906. #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
  907. #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
  908. #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
  909. #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
  910. #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
  911. /* masks */
  912. #define CONFIG_MEMSIZE_MASK 0x1f000000
  913. #define MEM_CFG_TYPE 0x40000000
  914. #define DST_OFFSET_MASK 0x003fffff
  915. #define DST_PITCH_MASK 0x3fc00000
  916. #define DEFAULT_TILE_MASK 0xc0000000
  917. #define PPLL_DIV_SEL_MASK 0x00000300
  918. #define PPLL_RESET 0x00000001
  919. #define PPLL_SLEEP 0x00000002
  920. #define PPLL_ATOMIC_UPDATE_EN 0x00010000
  921. #define PPLL_REF_DIV_MASK 0x000003ff
  922. #define PPLL_FB3_DIV_MASK 0x000007ff
  923. #define PPLL_POST3_DIV_MASK 0x00070000
  924. #define PPLL_ATOMIC_UPDATE_R 0x00008000
  925. #define PPLL_ATOMIC_UPDATE_W 0x00008000
  926. #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
  927. #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
  928. #define R300_PPLL_REF_DIV_ACC_SHIFT 18
  929. #define GUI_ACTIVE 0x80000000
  930. #define MC_IND_INDEX 0x01F8
  931. #define MC_IND_DATA 0x01FC
  932. /* PAD_CTLR_STRENGTH */
  933. #define PAD_MANUAL_OVERRIDE 0x80000000
  934. /* pllCLK_PIN_CNTL */
  935. #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
  936. #define CLK_PIN_CNTL__OSC_EN 0x00000001L
  937. #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
  938. #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
  939. #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
  940. #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
  941. #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
  942. #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
  943. #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
  944. #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
  945. #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
  946. #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
  947. #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
  948. #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
  949. #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
  950. #define CLK_PIN_CNTL__CG_SPARE 0x00004000L
  951. #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
  952. #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
  953. #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
  954. #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
  955. #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
  956. #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
  957. #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
  958. #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
  959. /* pllCLK_PWRMGT_CNTL */
  960. #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
  961. #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
  962. #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
  963. #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
  964. #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
  965. #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
  966. #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
  967. #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
  968. #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
  969. #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
  970. #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
  971. #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
  972. #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
  973. #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
  974. #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
  975. #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
  976. #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
  977. #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
  978. #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
  979. #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
  980. #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
  981. #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
  982. #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
  983. /* pllP2PLL_CNTL */
  984. #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
  985. #define P2PLL_CNTL__P2PLL_RESET 0x00000001L
  986. #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
  987. #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
  988. #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
  989. #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
  990. #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
  991. #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
  992. #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
  993. #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
  994. #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
  995. #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
  996. #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
  997. #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
  998. #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
  999. #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
  1000. #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
  1001. #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
  1002. #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
  1003. #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
  1004. #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
  1005. #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
  1006. #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
  1007. /* pllPIXCLKS_CNTL */
  1008. #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
  1009. #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
  1010. #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
  1011. #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
  1012. #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
  1013. #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
  1014. #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
  1015. #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
  1016. #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
  1017. #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
  1018. #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
  1019. /* pllPIXCLKS_CNTL */
  1020. #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
  1021. #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
  1022. #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
  1023. #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
  1024. #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
  1025. #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
  1026. #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
  1027. #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
  1028. #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
  1029. #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
  1030. #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
  1031. #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
  1032. #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
  1033. #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
  1034. #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
  1035. #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
  1036. #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
  1037. #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
  1038. #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
  1039. /* pllP2PLL_DIV_0 */
  1040. #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
  1041. #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
  1042. #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
  1043. #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
  1044. #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
  1045. #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
  1046. /* pllSCLK_CNTL */
  1047. #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
  1048. #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
  1049. #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
  1050. #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
  1051. #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
  1052. #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
  1053. #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
  1054. #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
  1055. #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
  1056. #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
  1057. #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
  1058. #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
  1059. #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
  1060. #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
  1061. #define SCLK_CNTL__FORCE_DISP2 0x00008000L
  1062. #define SCLK_CNTL__FORCE_CP 0x00010000L
  1063. #define SCLK_CNTL__FORCE_HDP 0x00020000L
  1064. #define SCLK_CNTL__FORCE_DISP1 0x00040000L
  1065. #define SCLK_CNTL__FORCE_TOP 0x00080000L
  1066. #define SCLK_CNTL__FORCE_E2 0x00100000L
  1067. #define SCLK_CNTL__FORCE_SE 0x00200000L
  1068. #define SCLK_CNTL__FORCE_IDCT 0x00400000L
  1069. #define SCLK_CNTL__FORCE_VIP 0x00800000L
  1070. #define SCLK_CNTL__FORCE_RE 0x01000000L
  1071. #define SCLK_CNTL__FORCE_PB 0x02000000L
  1072. #define SCLK_CNTL__FORCE_TAM 0x04000000L
  1073. #define SCLK_CNTL__FORCE_TDM 0x08000000L
  1074. #define SCLK_CNTL__FORCE_RB 0x10000000L
  1075. #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
  1076. #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
  1077. #define SCLK_CNTL__FORCE_OV0 0x80000000L
  1078. #define SCLK_CNTL__R300_FORCE_VAP (1<<21)
  1079. #define SCLK_CNTL__R300_FORCE_SR (1<<25)
  1080. #define SCLK_CNTL__R300_FORCE_PX (1<<26)
  1081. #define SCLK_CNTL__R300_FORCE_TX (1<<27)
  1082. #define SCLK_CNTL__R300_FORCE_US (1<<28)
  1083. #define SCLK_CNTL__R300_FORCE_SU (1<<30)
  1084. #define SCLK_CNTL__FORCEON_MASK 0xffff8000L
  1085. /* pllSCLK_CNTL2 */
  1086. #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
  1087. #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
  1088. #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
  1089. #define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
  1090. #define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
  1091. #define SCLK_CNTL2__R300_FORCE_GA (1<<15)
  1092. /* SCLK_MORE_CNTL */
  1093. #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
  1094. #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
  1095. #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
  1096. #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
  1097. #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
  1098. #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
  1099. #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
  1100. #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
  1101. #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
  1102. #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
  1103. #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
  1104. #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
  1105. #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
  1106. #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
  1107. #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
  1108. #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
  1109. #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
  1110. #define SCLK_MORE_CNTL__FORCEON 0x00000700L
  1111. /* MCLK_CNTL */
  1112. #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
  1113. #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
  1114. #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
  1115. #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
  1116. #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
  1117. #define MCLK_CNTL__FORCE_MCLKA 0x00010000L
  1118. #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
  1119. #define MCLK_CNTL__FORCE_MCLKB 0x00020000L
  1120. #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
  1121. #define MCLK_CNTL__FORCE_YCLKA 0x00040000L
  1122. #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
  1123. #define MCLK_CNTL__FORCE_YCLKB 0x00080000L
  1124. #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
  1125. #define MCLK_CNTL__FORCE_MC 0x00100000L
  1126. #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
  1127. #define MCLK_CNTL__FORCE_AIC 0x00200000L
  1128. #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
  1129. #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
  1130. #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
  1131. #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
  1132. #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
  1133. #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
  1134. /* MCLK_MISC */
  1135. #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
  1136. #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
  1137. #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
  1138. #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
  1139. #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
  1140. #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
  1141. #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
  1142. #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
  1143. #define MCLK_MISC__DLL_READY_LAT 0x00000100L
  1144. #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
  1145. #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
  1146. #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
  1147. #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
  1148. #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
  1149. #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
  1150. #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
  1151. #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
  1152. #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
  1153. #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
  1154. #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
  1155. #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
  1156. #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
  1157. #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
  1158. #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
  1159. #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
  1160. #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
  1161. #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
  1162. #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
  1163. /* VCLK_ECP_CNTL */
  1164. #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
  1165. #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
  1166. #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
  1167. #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
  1168. #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
  1169. #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
  1170. #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
  1171. #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
  1172. #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
  1173. /* PLL_PWRMGT_CNTL */
  1174. #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
  1175. #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
  1176. #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
  1177. #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
  1178. #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
  1179. #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
  1180. #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
  1181. #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
  1182. #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
  1183. #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
  1184. #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
  1185. #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
  1186. #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
  1187. #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
  1188. #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
  1189. #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
  1190. #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
  1191. #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
  1192. #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
  1193. #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
  1194. #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
  1195. #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
  1196. #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
  1197. #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
  1198. #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
  1199. #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
  1200. #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
  1201. #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
  1202. #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
  1203. #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
  1204. #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
  1205. #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
  1206. /* CLK_PWRMGT_CNTL */
  1207. #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
  1208. #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
  1209. #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
  1210. #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
  1211. #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
  1212. #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
  1213. #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
  1214. #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
  1215. #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
  1216. #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
  1217. #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
  1218. #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
  1219. #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
  1220. #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
  1221. #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
  1222. #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
  1223. #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
  1224. #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
  1225. #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
  1226. #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
  1227. #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
  1228. #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
  1229. #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
  1230. #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
  1231. #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
  1232. #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
  1233. #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
  1234. #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
  1235. #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
  1236. #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
  1237. #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
  1238. #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
  1239. #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
  1240. #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
  1241. #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
  1242. #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
  1243. #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
  1244. #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
  1245. #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
  1246. #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
  1247. #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
  1248. #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
  1249. #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
  1250. /* BUS_CNTL1 */
  1251. #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
  1252. #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
  1253. #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
  1254. #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
  1255. #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
  1256. #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
  1257. #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
  1258. #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
  1259. #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
  1260. #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
  1261. #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
  1262. #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
  1263. #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
  1264. #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
  1265. #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
  1266. #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
  1267. #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
  1268. #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
  1269. #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
  1270. #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
  1271. #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
  1272. #define BUS_CNTL1__AGPCLK_VALID 0x80000000L
  1273. /* BUS_CNTL1 */
  1274. #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
  1275. #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
  1276. #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
  1277. #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
  1278. #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
  1279. #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
  1280. #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
  1281. #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
  1282. #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
  1283. #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
  1284. #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
  1285. #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
  1286. /* CRTC_OFFSET_CNTL */
  1287. #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
  1288. #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
  1289. #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
  1290. #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
  1291. #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
  1292. #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
  1293. #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
  1294. #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
  1295. #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
  1296. #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
  1297. #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
  1298. #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
  1299. #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
  1300. #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
  1301. #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
  1302. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
  1303. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
  1304. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
  1305. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
  1306. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
  1307. #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
  1308. #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
  1309. #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
  1310. /* CRTC_GEN_CNTL */
  1311. #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
  1312. #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
  1313. #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
  1314. #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
  1315. #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
  1316. #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
  1317. #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
  1318. #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
  1319. #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
  1320. #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
  1321. #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
  1322. #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
  1323. #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
  1324. #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
  1325. #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
  1326. #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
  1327. #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
  1328. #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
  1329. #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
  1330. /* CRTC2_GEN_CNTL */
  1331. #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
  1332. #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
  1333. #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
  1334. #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
  1335. #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
  1336. #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
  1337. #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
  1338. #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
  1339. #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
  1340. #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
  1341. #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
  1342. #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
  1343. #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
  1344. #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
  1345. #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
  1346. #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
  1347. #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
  1348. #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
  1349. #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
  1350. #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
  1351. #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
  1352. #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
  1353. #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
  1354. #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
  1355. #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
  1356. #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
  1357. #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
  1358. #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
  1359. #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
  1360. #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
  1361. /* AGP_CNTL */
  1362. #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
  1363. #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
  1364. #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
  1365. #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
  1366. #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
  1367. #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
  1368. #define AGP_CNTL__EN_2X_STBB 0x00000400L
  1369. #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
  1370. #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
  1371. #define AGP_CNTL__SBA_DIS_MASK 0x00001000L
  1372. #define AGP_CNTL__SBA_DIS 0x00001000L
  1373. #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
  1374. #define AGP_CNTL__AGP_REV_ID 0x00002000L
  1375. #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
  1376. #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
  1377. #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
  1378. #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
  1379. #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
  1380. #define AGP_CNTL__FORCE_INT_VREF 0x00010000L
  1381. #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
  1382. #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
  1383. #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
  1384. #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
  1385. #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
  1386. #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
  1387. #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
  1388. #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
  1389. #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
  1390. #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
  1391. #define AGP_CNTL__EN_RBFCALM 0x00800000L
  1392. #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
  1393. #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
  1394. #define AGP_CNTL__DIS_RBF_MASK 0x02000000L
  1395. #define AGP_CNTL__DIS_RBF 0x02000000L
  1396. #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
  1397. #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
  1398. #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
  1399. #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
  1400. /* AGP_CNTL */
  1401. #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
  1402. #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
  1403. #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
  1404. #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
  1405. #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
  1406. #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
  1407. #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
  1408. #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
  1409. #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
  1410. #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
  1411. #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
  1412. #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
  1413. #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
  1414. #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
  1415. #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
  1416. #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
  1417. #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
  1418. #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
  1419. #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
  1420. #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
  1421. #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
  1422. /* DISP_MISC_CNTL */
  1423. #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
  1424. #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
  1425. #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
  1426. #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
  1427. #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
  1428. #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
  1429. #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
  1430. #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
  1431. #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
  1432. #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
  1433. #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
  1434. #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
  1435. #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
  1436. #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
  1437. #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
  1438. #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
  1439. #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
  1440. #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
  1441. #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
  1442. #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
  1443. #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
  1444. #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
  1445. #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
  1446. #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
  1447. #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
  1448. #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
  1449. #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
  1450. #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
  1451. #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
  1452. #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
  1453. /* DISP_PWR_MAN */
  1454. #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
  1455. #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
  1456. #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
  1457. #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
  1458. #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
  1459. #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
  1460. #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
  1461. #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
  1462. #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
  1463. #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
  1464. #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
  1465. #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
  1466. #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
  1467. #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
  1468. #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
  1469. #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
  1470. #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
  1471. #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
  1472. #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
  1473. #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
  1474. #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
  1475. #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
  1476. #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
  1477. #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
  1478. #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
  1479. #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
  1480. #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
  1481. /* MC_IND_INDEX */
  1482. #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
  1483. #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
  1484. #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
  1485. /* MC_IND_DATA */
  1486. #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
  1487. /* MC_CHP_IO_CNTL_A1 */
  1488. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
  1489. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
  1490. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
  1491. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
  1492. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
  1493. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
  1494. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
  1495. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
  1496. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
  1497. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
  1498. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
  1499. #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
  1500. #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
  1501. #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
  1502. #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
  1503. #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
  1504. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
  1505. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
  1506. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
  1507. #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
  1508. #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
  1509. #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
  1510. #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
  1511. /* MC_CHP_IO_CNTL_B1 */
  1512. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
  1513. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
  1514. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
  1515. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
  1516. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
  1517. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
  1518. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
  1519. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
  1520. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
  1521. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
  1522. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
  1523. #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
  1524. #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
  1525. #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
  1526. #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
  1527. #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
  1528. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
  1529. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
  1530. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
  1531. #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
  1532. #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
  1533. #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
  1534. #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
  1535. /* MC_CHP_IO_CNTL_A1 */
  1536. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
  1537. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
  1538. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
  1539. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
  1540. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
  1541. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
  1542. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
  1543. #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
  1544. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
  1545. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
  1546. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
  1547. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
  1548. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
  1549. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
  1550. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
  1551. #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
  1552. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
  1553. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
  1554. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
  1555. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
  1556. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
  1557. #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
  1558. #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
  1559. #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
  1560. #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
  1561. #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
  1562. #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
  1563. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
  1564. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
  1565. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
  1566. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
  1567. #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
  1568. #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
  1569. #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
  1570. #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
  1571. #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
  1572. #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
  1573. #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
  1574. #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
  1575. /* MC_CHP_IO_CNTL_B1 */
  1576. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
  1577. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
  1578. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
  1579. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
  1580. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
  1581. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
  1582. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
  1583. #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
  1584. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
  1585. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
  1586. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
  1587. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
  1588. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
  1589. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
  1590. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
  1591. #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
  1592. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
  1593. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
  1594. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
  1595. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
  1596. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
  1597. #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
  1598. #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
  1599. #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
  1600. #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
  1601. #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
  1602. #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
  1603. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
  1604. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
  1605. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
  1606. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
  1607. #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
  1608. #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
  1609. #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
  1610. #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
  1611. #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
  1612. #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
  1613. #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
  1614. #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
  1615. /* MEM_SDRAM_MODE_REG */
  1616. #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
  1617. #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
  1618. #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
  1619. #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
  1620. #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
  1621. #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
  1622. #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
  1623. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
  1624. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
  1625. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
  1626. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
  1627. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
  1628. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
  1629. #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
  1630. #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
  1631. #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
  1632. #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
  1633. #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
  1634. #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
  1635. #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
  1636. #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
  1637. /* MEM_SDRAM_MODE_REG */
  1638. #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
  1639. #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
  1640. #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
  1641. #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
  1642. #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
  1643. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
  1644. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
  1645. #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
  1646. #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
  1647. #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
  1648. #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
  1649. #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
  1650. /* MEM_REFRESH_CNTL */
  1651. #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
  1652. #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
  1653. #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
  1654. #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
  1655. #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
  1656. #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
  1657. #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
  1658. #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
  1659. #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
  1660. #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
  1661. #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
  1662. #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
  1663. #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
  1664. #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
  1665. #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
  1666. #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
  1667. #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
  1668. #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
  1669. #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
  1670. #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
  1671. #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
  1672. #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
  1673. #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
  1674. #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
  1675. #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
  1676. #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
  1677. #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
  1678. #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
  1679. /* MC_STATUS */
  1680. #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
  1681. #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
  1682. #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
  1683. #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
  1684. #define MC_STATUS__MC_IDLE_MASK 0x00000004L
  1685. #define MC_STATUS__MC_IDLE 0x00000004L
  1686. #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
  1687. #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
  1688. #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
  1689. #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
  1690. #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
  1691. #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
  1692. #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
  1693. #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
  1694. #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
  1695. #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
  1696. /* MDLL_CKO */
  1697. #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
  1698. #define MDLL_CKO__MCKOA_SLEEP 0x00000001L
  1699. #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
  1700. #define MDLL_CKO__MCKOA_RESET 0x00000002L
  1701. #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
  1702. #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
  1703. #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
  1704. #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
  1705. #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
  1706. #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
  1707. #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
  1708. #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
  1709. #define MDLL_CKO__MCKOB_SLEEP 0x00010000L
  1710. #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
  1711. #define MDLL_CKO__MCKOB_RESET 0x00020000L
  1712. #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
  1713. #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
  1714. #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
  1715. #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
  1716. #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
  1717. #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
  1718. #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
  1719. /* MDLL_RDCKA */
  1720. #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
  1721. #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
  1722. #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
  1723. #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
  1724. #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
  1725. #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
  1726. #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
  1727. #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
  1728. #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
  1729. #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
  1730. #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
  1731. #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
  1732. #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
  1733. #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
  1734. #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
  1735. #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
  1736. #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
  1737. #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
  1738. #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
  1739. #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
  1740. #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
  1741. #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
  1742. #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
  1743. #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
  1744. #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
  1745. #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
  1746. /* MDLL_RDCKB */
  1747. #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
  1748. #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
  1749. #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
  1750. #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
  1751. #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
  1752. #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
  1753. #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
  1754. #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
  1755. #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
  1756. #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
  1757. #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
  1758. #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
  1759. #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
  1760. #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
  1761. #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
  1762. #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
  1763. #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
  1764. #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
  1765. #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
  1766. #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
  1767. #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
  1768. #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
  1769. #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
  1770. #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
  1771. #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
  1772. #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
  1773. #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
  1774. #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
  1775. #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
  1776. #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
  1777. #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
  1778. #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
  1779. #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
  1780. #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
  1781. #define pllCLK_PIN_CNTL 0x0001
  1782. #define pllPPLL_CNTL 0x0002
  1783. #define pllPPLL_REF_DIV 0x0003
  1784. #define pllPPLL_DIV_0 0x0004
  1785. #define pllPPLL_DIV_1 0x0005
  1786. #define pllPPLL_DIV_2 0x0006
  1787. #define pllPPLL_DIV_3 0x0007
  1788. #define pllVCLK_ECP_CNTL 0x0008
  1789. #define pllHTOTAL_CNTL 0x0009
  1790. #define pllM_SPLL_REF_FB_DIV 0x000A
  1791. #define pllAGP_PLL_CNTL 0x000B
  1792. #define pllSPLL_CNTL 0x000C
  1793. #define pllSCLK_CNTL 0x000D
  1794. #define pllMPLL_CNTL 0x000E
  1795. #define pllMDLL_CKO 0x000F
  1796. #define pllMDLL_RDCKA 0x0010
  1797. #define pllMDLL_RDCKB 0x0011
  1798. #define pllMCLK_CNTL 0x0012
  1799. #define pllPLL_TEST_CNTL 0x0013
  1800. #define pllCLK_PWRMGT_CNTL 0x0014
  1801. #define pllPLL_PWRMGT_CNTL 0x0015
  1802. #define pllCG_TEST_MACRO_RW_WRITE 0x0016
  1803. #define pllCG_TEST_MACRO_RW_READ 0x0017
  1804. #define pllCG_TEST_MACRO_RW_DATA 0x0018
  1805. #define pllCG_TEST_MACRO_RW_CNTL 0x0019
  1806. #define pllDISP_TEST_MACRO_RW_WRITE 0x001A
  1807. #define pllDISP_TEST_MACRO_RW_READ 0x001B
  1808. #define pllDISP_TEST_MACRO_RW_DATA 0x001C
  1809. #define pllDISP_TEST_MACRO_RW_CNTL 0x001D
  1810. #define pllSCLK_CNTL2 0x001E
  1811. #define pllMCLK_MISC 0x001F
  1812. #define pllTV_PLL_FINE_CNTL 0x0020
  1813. #define pllTV_PLL_CNTL 0x0021
  1814. #define pllTV_PLL_CNTL1 0x0022
  1815. #define pllTV_DTO_INCREMENTS 0x0023
  1816. #define pllSPLL_AUX_CNTL 0x0024
  1817. #define pllMPLL_AUX_CNTL 0x0025
  1818. #define pllP2PLL_CNTL 0x002A
  1819. #define pllP2PLL_REF_DIV 0x002B
  1820. #define pllP2PLL_DIV_0 0x002C
  1821. #define pllPIXCLKS_CNTL 0x002D
  1822. #define pllHTOTAL2_CNTL 0x002E
  1823. #define pllSSPLL_CNTL 0x0030
  1824. #define pllSSPLL_REF_DIV 0x0031
  1825. #define pllSSPLL_DIV_0 0x0032
  1826. #define pllSS_INT_CNTL 0x0033
  1827. #define pllSS_TST_CNTL 0x0034
  1828. #define pllSCLK_MORE_CNTL 0x0035
  1829. #define ixMC_PERF_CNTL 0x0000
  1830. #define ixMC_PERF_SEL 0x0001
  1831. #define ixMC_PERF_REGION_0 0x0002
  1832. #define ixMC_PERF_REGION_1 0x0003
  1833. #define ixMC_PERF_COUNT_0 0x0004
  1834. #define ixMC_PERF_COUNT_1 0x0005
  1835. #define ixMC_PERF_COUNT_2 0x0006
  1836. #define ixMC_PERF_COUNT_3 0x0007
  1837. #define ixMC_PERF_COUNT_MEMCH_A 0x0008
  1838. #define ixMC_PERF_COUNT_MEMCH_B 0x0009
  1839. #define ixMC_IMP_CNTL 0x000A
  1840. #define ixMC_CHP_IO_CNTL_A0 0x000B
  1841. #define ixMC_CHP_IO_CNTL_A1 0x000C
  1842. #define ixMC_CHP_IO_CNTL_B0 0x000D
  1843. #define ixMC_CHP_IO_CNTL_B1 0x000E
  1844. #define ixMC_IMP_CNTL_0 0x000F
  1845. #define ixTC_MISMATCH_1 0x0010
  1846. #define ixTC_MISMATCH_2 0x0011
  1847. #define ixMC_BIST_CTRL 0x0012
  1848. #define ixREG_COLLAR_WRITE 0x0013
  1849. #define ixREG_COLLAR_READ 0x0014
  1850. #define ixR300_MC_IMP_CNTL 0x0018
  1851. #define ixR300_MC_CHP_IO_CNTL_A0 0x0019
  1852. #define ixR300_MC_CHP_IO_CNTL_A1 0x001a
  1853. #define ixR300_MC_CHP_IO_CNTL_B0 0x001b
  1854. #define ixR300_MC_CHP_IO_CNTL_B1 0x001c
  1855. #define ixR300_MC_CHP_IO_CNTL_C0 0x001d
  1856. #define ixR300_MC_CHP_IO_CNTL_C1 0x001e
  1857. #define ixR300_MC_CHP_IO_CNTL_D0 0x001f
  1858. #define ixR300_MC_CHP_IO_CNTL_D1 0x0020
  1859. #define ixR300_MC_IMP_CNTL_0 0x0021
  1860. #define ixR300_MC_ELPIDA_CNTL 0x0022
  1861. #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
  1862. #define ixR300_MC_READ_CNTL_CD 0x0024
  1863. #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
  1864. #define ixR300_MC_DEBUG_CNTL 0x0026
  1865. #define ixR300_MC_BIST_CNTL_0 0x0028
  1866. #define ixR300_MC_BIST_CNTL_1 0x0029
  1867. #define ixR300_MC_BIST_CNTL_2 0x002a
  1868. #define ixR300_MC_BIST_CNTL_3 0x002b
  1869. #define ixR300_MC_BIST_CNTL_4 0x002c
  1870. #define ixR300_MC_BIST_CNTL_5 0x002d
  1871. #define ixR300_MC_IMP_STATUS 0x002e
  1872. #define ixR300_MC_DLL_CNTL 0x002f
  1873. #define NB_TOM 0x15C
  1874. #endif /* _RADEON_H */