tps65090.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #ifndef __TPS65090_PMIC_H_
  7. #define __TPS65090_PMIC_H_
  8. /* I2C device address for TPS65090 PMU */
  9. #define TPS65090_I2C_ADDR 0x48
  10. /* TPS65090 register addresses */
  11. enum {
  12. REG_IRQ1 = 0,
  13. REG_CG_CTRL0 = 4,
  14. REG_CG_STATUS1 = 0xa,
  15. REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */
  16. REG_FET1_CTRL,
  17. REG_FET2_CTRL,
  18. REG_FET3_CTRL,
  19. REG_FET4_CTRL,
  20. REG_FET5_CTRL,
  21. REG_FET6_CTRL,
  22. REG_FET7_CTRL,
  23. TPS65090_NUM_REGS,
  24. };
  25. enum {
  26. IRQ1_VBATG = 1 << 3,
  27. CG_CTRL0_ENC_MASK = 0x01,
  28. MAX_FET_NUM = 7,
  29. MAX_CTRL_READ_TRIES = 5,
  30. /* TPS65090 FET_CTRL register values */
  31. FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
  32. FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
  33. FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
  34. FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
  35. FET_CTRL_ENFET = 1 << 0, /* Enable FET */
  36. };
  37. enum {
  38. /* Status register fields */
  39. TPS65090_ST1_OTC = 1 << 0,
  40. TPS65090_ST1_OCC = 1 << 1,
  41. TPS65090_ST1_STATE_SHIFT = 4,
  42. TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT,
  43. };
  44. /* Drivers name */
  45. #define TPS65090_FET_DRIVER "tps65090_fet"
  46. #endif /* __TPS65090_PMIC_H_ */