stpmic1.h 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111
  1. /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #ifndef __PMIC_STPMIC1_H_
  6. #define __PMIC_STPMIC1_H_
  7. #define STPMIC1_MAIN_CR 0x10
  8. #define STPMIC1_BUCKS_MRST_CR 0x18
  9. #define STPMIC1_LDOS_MRST_CR 0x1a
  10. #define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
  11. #define STPMIC1_REFDDR_MAIN_CR 0x24
  12. #define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
  13. #define STPMIC1_BST_SW_CR 0x40
  14. #define STPMIC1_NVM_SR 0xb8
  15. #define STPMIC1_NVM_CR 0xb9
  16. /* Main PMIC Control Register (MAIN_CR) */
  17. #define STPMIC1_SWOFF BIT(0)
  18. #define STPMIC1_RREQ_EN BIT(1)
  19. /* BUCKS_MRST_CR */
  20. #define STPMIC1_MRST_BUCK(buck) BIT(buck)
  21. #define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
  22. STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
  23. /* LDOS_MRST_CR */
  24. #define STPMIC1_MRST_LDO(ldo) BIT(ldo)
  25. #define STPMIC1_MRST_LDO_DEBUG 0
  26. /* BUCKx_MAIN_CR (x=1...4) */
  27. #define STPMIC1_BUCK_ENA BIT(0)
  28. #define STPMIC1_BUCK_PREG_MODE BIT(1)
  29. #define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
  30. #define STPMIC1_BUCK_VOUT_SHIFT 2
  31. #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
  32. #define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
  33. #define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
  34. #define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
  35. /* REFDDR_MAIN_CR */
  36. #define STPMIC1_VREF_ENA BIT(0)
  37. /* LDOX_MAIN_CR */
  38. #define STPMIC1_LDO_ENA BIT(0)
  39. #define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
  40. #define STPMIC1_LDO12356_VOUT_SHIFT 2
  41. #define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
  42. #define STPMIC1_LDO3_MODE BIT(7)
  43. #define STPMIC1_LDO3_DDR_SEL 31
  44. #define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
  45. #define STPMIC1_LDO4_UV 3300000
  46. /* BST_SW_CR */
  47. #define STPMIC1_BST_ON BIT(0)
  48. #define STPMIC1_VBUSOTG_ON BIT(1)
  49. #define STPMIC1_SWOUT_ON BIT(2)
  50. #define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
  51. /* NVM_SR */
  52. #define STPMIC1_NVM_BUSY BIT(0)
  53. /* NVM_CR */
  54. #define STPMIC1_NVM_CMD_PROGRAM 1
  55. #define STPMIC1_NVM_CMD_READ 2
  56. /* Timeout */
  57. #define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
  58. #define STPMIC1_DEFAULT_STOP_DELAY_MS 5
  59. #define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
  60. enum {
  61. STPMIC1_BUCK1,
  62. STPMIC1_BUCK2,
  63. STPMIC1_BUCK3,
  64. STPMIC1_BUCK4,
  65. STPMIC1_MAX_BUCK,
  66. };
  67. enum {
  68. STPMIC1_PREG_MODE_HP,
  69. STPMIC1_PREG_MODE_LP,
  70. };
  71. enum {
  72. STPMIC1_LDO1,
  73. STPMIC1_LDO2,
  74. STPMIC1_LDO3,
  75. STPMIC1_LDO4,
  76. STPMIC1_LDO5,
  77. STPMIC1_LDO6,
  78. STPMIC1_MAX_LDO,
  79. };
  80. enum {
  81. STPMIC1_LDO_MODE_NORMAL,
  82. STPMIC1_LDO_MODE_BYPASS,
  83. STPMIC1_LDO_MODE_SINK_SOURCE,
  84. };
  85. enum {
  86. STPMIC1_PWR_SW1,
  87. STPMIC1_PWR_SW2,
  88. STPMIC1_MAX_PWR_SW,
  89. };
  90. #endif