s5m8767.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. */
  5. #ifndef __S5M8767_H_
  6. #define __S5M8767_H_
  7. enum s5m8767_regnum {
  8. S5M8767_BUCK1 = 0,
  9. S5M8767_BUCK2,
  10. S5M8767_BUCK3,
  11. S5M8767_BUCK4,
  12. S5M8767_BUCK5,
  13. S5M8767_BUCK6,
  14. S5M8767_BUCK7,
  15. S5M8767_BUCK8,
  16. S5M8767_BUCK9,
  17. S5M8767_LDO1,
  18. S5M8767_LDO2,
  19. S5M8767_LDO3,
  20. S5M8767_LDO4,
  21. S5M8767_LDO5,
  22. S5M8767_LDO6,
  23. S5M8767_LDO7,
  24. S5M8767_LDO8,
  25. S5M8767_LDO9,
  26. S5M8767_LDO10,
  27. S5M8767_LDO11,
  28. S5M8767_LDO12,
  29. S5M8767_LDO13,
  30. S5M8767_LDO14,
  31. S5M8767_LDO15,
  32. S5M8767_LDO16,
  33. S5M8767_LDO17,
  34. S5M8767_LDO18,
  35. S5M8767_LDO19,
  36. S5M8767_LDO20,
  37. S5M8767_LDO21,
  38. S5M8767_LDO22,
  39. S5M8767_LDO23,
  40. S5M8767_LDO24,
  41. S5M8767_LDO25,
  42. S5M8767_LDO26,
  43. S5M8767_LDO27,
  44. S5M8767_LDO28,
  45. S5M8767_EN32KHZ_CP,
  46. S5M8767_NUM_OF_REGS,
  47. };
  48. struct sec_voltage_desc {
  49. int max;
  50. int min;
  51. int step;
  52. };
  53. /**
  54. * struct s5m8767_para - s5m8767 register parameters
  55. * @param vol_addr i2c address of the given buck/ldo register
  56. * @param vol_bitpos bit position to be set or clear within register
  57. * @param vol_bitmask bit mask value
  58. * @param reg_enaddr control register address, which enable the given
  59. * given buck/ldo.
  60. * @param reg_enbiton value to be written to buck/ldo to make it ON
  61. * @param vol Voltage information
  62. */
  63. struct s5m8767_para {
  64. enum s5m8767_regnum regnum;
  65. u8 vol_addr;
  66. u8 vol_bitpos;
  67. u8 vol_bitmask;
  68. u8 reg_enaddr;
  69. u8 reg_enbiton;
  70. const struct sec_voltage_desc *vol;
  71. };
  72. /* Drivers name */
  73. #define S5M8767_LDO_DRIVER "s5m8767_ldo"
  74. #define S5M8767_BUCK_DRIVER "s5m8767_buck"
  75. int s5m8767_enable_32khz_cp(struct udevice *dev);
  76. #endif /* __S5M8767_PMIC_H_ */