rk8xx_pmic.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #ifndef _PMIC_RK8XX_H_
  7. #define _PMIC_RK8XX_H_
  8. enum {
  9. REG_SECONDS = 0x00,
  10. REG_MINUTES,
  11. REG_HOURS,
  12. REG_DAYS,
  13. REG_MONTHS,
  14. REG_YEARS,
  15. REG_WEEKS,
  16. REG_ALARM_SECONDS,
  17. REG_ALARM_MINUTES,
  18. REG_ALARM_HOURS,
  19. REG_ALARM_DAYS,
  20. REG_ALARM_MONTHS,
  21. REG_ALARM_YEARS,
  22. REG_RTC_CTRL = 0x10,
  23. REG_RTC_STATUS,
  24. REG_RTC_INT,
  25. REG_RTC_COMP_LSB,
  26. REG_RTC_COMP_MSB,
  27. ID_MSB = 0x17,
  28. ID_LSB,
  29. REG_CLK32OUT = 0x20,
  30. REG_VB_MON,
  31. REG_THERMAL,
  32. REG_DCDC_EN,
  33. REG_LDO_EN,
  34. REG_SLEEP_SET_OFF1,
  35. REG_SLEEP_SET_OFF2,
  36. REG_DCDC_UV_STS,
  37. REG_DCDC_UV_ACT,
  38. REG_LDO_UV_STS,
  39. REG_LDO_UV_ACT,
  40. REG_DCDC_PG,
  41. REG_LDO_PG,
  42. REG_VOUT_MON_TDB,
  43. REG_BUCK1_CONFIG,
  44. REG_BUCK1_ON_VSEL,
  45. REG_BUCK1_SLP_VSEL,
  46. REG_BUCK1_DVS_VSEL,
  47. REG_BUCK2_CONFIG,
  48. REG_BUCK2_ON_VSEL,
  49. REG_BUCK2_SLP_VSEL,
  50. REG_BUCK2_DVS_VSEL,
  51. REG_BUCK3_CONFIG,
  52. REG_BUCK4_CONFIG,
  53. REG_BUCK4_ON_VSEL,
  54. REG_BUCK4_SLP_VSEL,
  55. REG_BOOST_CONFIG_REG,
  56. REG_LDO1_ON_VSEL,
  57. REG_LDO1_SLP_VSEL,
  58. REG_LDO2_ON_VSEL,
  59. REG_LDO2_SLP_VSEL,
  60. REG_LDO3_ON_VSEL,
  61. REG_LDO3_SLP_VSEL,
  62. REG_LDO4_ON_VSEL,
  63. REG_LDO4_SLP_VSEL,
  64. REG_LDO5_ON_VSEL,
  65. REG_LDO5_SLP_VSEL,
  66. REG_LDO6_ON_VSEL,
  67. REG_LDO6_SLP_VSEL,
  68. REG_LDO7_ON_VSEL,
  69. REG_LDO7_SLP_VSEL,
  70. REG_LDO8_ON_VSEL,
  71. REG_LDO8_SLP_VSEL,
  72. REG_DEVCTRL,
  73. REG_INT_STS1,
  74. REG_INT_STS_MSK1,
  75. REG_INT_STS2,
  76. REG_INT_STS_MSK2,
  77. REG_IO_POL,
  78. REG_OTP_VDD_EN,
  79. REG_H5V_EN,
  80. REG_SLEEP_SET_OFF,
  81. REG_BOOST_LDO9_ON_VSEL,
  82. REG_BOOST_LDO9_SLP_VSEL,
  83. REG_BOOST_CTRL,
  84. /* Not sure what this does */
  85. REG_DCDC_ILMAX = 0x90,
  86. REG_CHRG_COMP = 0x9a,
  87. REG_SUP_STS = 0xa0,
  88. REG_USB_CTRL,
  89. REG1_CHRG_CTRL,
  90. REG2_CHRG_CTRL,
  91. REG3_CHRG_CTRL,
  92. REG_BAT_CTRL,
  93. REG_BAT_HTS_TS1,
  94. REG_BAT_LTS_TS1,
  95. REG_BAT_HTS_TS2,
  96. REG_BAT_LTS_TS2,
  97. REG_TS_CTRL,
  98. REG_ADC_CTRL,
  99. REG_ON_SOURCE,
  100. REG_OFF_SOURCE,
  101. REG_GGCON,
  102. REG_GGSTS,
  103. REG_FRAME_SMP_INTERV,
  104. REG_AUTO_SLP_CUR_THR,
  105. REG3_GASCNT_CAL,
  106. REG2_GASCNT_CAL,
  107. REG1_GASCNT_CAL,
  108. REG0_GASCNT_CAL,
  109. REG3_GASCNT,
  110. REG2_GASCNT,
  111. REG1_GASCNT,
  112. REG0_GASCNT,
  113. REGH_BAT_CUR_AVG,
  114. REGL_BAT_CUR_AVG,
  115. REGH_TS1_ADC,
  116. REGL_TS1_ADC,
  117. REGH_TS2_ADC,
  118. REGL_TS2_ADC,
  119. REGH_BAT_OCV,
  120. REGL_BAT_OCV,
  121. REGH_BAT_VOL,
  122. REGL_BAT_VOL,
  123. REGH_RELAX_ENTRY_THRES,
  124. REGL_RELAX_ENTRY_THRES,
  125. REGH_RELAX_EXIT_THRES,
  126. REGL_RELAX_EXIT_THRES,
  127. REGH_RELAX_VOL1,
  128. REGL_RELAX_VOL1,
  129. REGH_RELAX_VOL2,
  130. REGL_RELAX_VOL2,
  131. REGH_BAT_CUR_R_CALC,
  132. REGL_BAT_CUR_R_CALC,
  133. REGH_BAT_VOL_R_CALC,
  134. REGL_BAT_VOL_R_CALC,
  135. REGH_CAL_OFFSET,
  136. REGL_CAL_OFFSET,
  137. REG_NON_ACT_TIMER_CNT,
  138. REGH_VCALIB0,
  139. REGL_VCALIB0,
  140. REGH_VCALIB1,
  141. REGL_VCALIB1,
  142. REGH_IOFFSET,
  143. REGL_IOFFSET,
  144. REG_SOC,
  145. REG3_REMAIN_CAP,
  146. REG2_REMAIN_CAP,
  147. REG1_REMAIN_CAP,
  148. REG0_REMAIN_CAP,
  149. REG_UPDAT_LEVE,
  150. REG3_NEW_FCC,
  151. REG2_NEW_FCC,
  152. REG1_NEW_FCC,
  153. REG0_NEW_FCC,
  154. REG_NON_ACT_TIMER_CNT_SAVE,
  155. REG_OCV_VOL_VALID,
  156. REG_REBOOT_CNT,
  157. REG_POFFSET,
  158. REG_MISC_MARK,
  159. REG_HALT_CNT,
  160. REGH_CALC_REST,
  161. REGL_CALC_REST,
  162. SAVE_DATA19,
  163. RK808_NUM_OF_REGS,
  164. };
  165. enum {
  166. RK817_REG_SYS_CFG3 = 0xf4,
  167. };
  168. enum {
  169. RK816_REG_DCDC_EN1 = 0x23,
  170. RK816_REG_DCDC_EN2,
  171. RK816_REG_DCDC_SLP_EN,
  172. RK816_REG_LDO_SLP_EN,
  173. RK816_REG_LDO_EN1 = 0x27,
  174. RK816_REG_LDO_EN2,
  175. };
  176. enum {
  177. RK805_ID = 0x8050,
  178. RK808_ID = 0x0000,
  179. RK809_ID = 0x8090,
  180. RK816_ID = 0x8160,
  181. RK817_ID = 0x8170,
  182. RK818_ID = 0x8180,
  183. };
  184. enum {
  185. RK817_POWER_EN0 = 0xb1,
  186. RK817_POWER_EN1,
  187. RK817_POWER_EN2,
  188. RK817_POWER_EN3,
  189. };
  190. #define RK817_POWER_EN_SAVE0 0x99
  191. #define RK817_POWER_EN_SAVE1 0xa4
  192. #define RK817_ID_MSB 0xed
  193. #define RK817_ID_LSB 0xee
  194. #define RK8XX_ID_MSK 0xfff0
  195. #define RK817_PMIC_SYS_CFG3 0xf4
  196. #define RK817_GPIO_INT_CFG 0xfe
  197. #define RK8XX_ON_SOURCE 0xae
  198. #define RK8XX_OFF_SOURCE 0xaf
  199. #define RK817_BUCK4_CMIN 0xc6
  200. #define RK817_ON_SOURCE 0xf5
  201. #define RK817_OFF_SOURCE 0xf6
  202. struct reg_data {
  203. u8 reg;
  204. u8 val;
  205. u8 mask;
  206. };
  207. struct rk8xx_reg_table {
  208. char *name;
  209. u8 reg_ctl;
  210. u8 reg_vol;
  211. };
  212. struct rk8xx_priv {
  213. int variant;
  214. };
  215. int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
  216. int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
  217. int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
  218. #endif