bd71837.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /* Copyright (C) 2018 ROHM Semiconductors */
  3. #ifndef BD718XX_H_
  4. #define BD718XX_H_
  5. #define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
  6. enum {
  7. ROHM_CHIP_TYPE_BD71837 = 0,
  8. ROHM_CHIP_TYPE_BD71847,
  9. ROHM_CHIP_TYPE_BD70528,
  10. ROHM_CHIP_TYPE_AMOUNT
  11. };
  12. enum {
  13. BD718XX_REV = 0x00,
  14. BD718XX_SWRESET = 0x01,
  15. BD718XX_I2C_DEV = 0x02,
  16. BD718XX_PWRCTRL0 = 0x03,
  17. BD718XX_PWRCTRL1 = 0x04,
  18. BD718XX_BUCK1_CTRL = 0x05,
  19. BD718XX_BUCK2_CTRL = 0x06,
  20. BD71837_BUCK3_CTRL = 0x07,
  21. BD71837_BUCK4_CTRL = 0x08,
  22. BD718XX_1ST_NODVS_BUCK_CTRL = 0x09,
  23. BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a,
  24. BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b,
  25. BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c,
  26. BD718XX_BUCK1_VOLT_RUN = 0x0d,
  27. BD718XX_BUCK1_VOLT_IDLE = 0x0e,
  28. BD718XX_BUCK1_VOLT_SUSP = 0x0f,
  29. BD718XX_BUCK2_VOLT_RUN = 0x10,
  30. BD718XX_BUCK2_VOLT_IDLE = 0x11,
  31. BD71837_BUCK3_VOLT_RUN = 0x12,
  32. BD71837_BUCK4_VOLT_RUN = 0x13,
  33. BD718XX_1ST_NODVS_BUCK_VOLT = 0x14,
  34. BD718XX_2ND_NODVS_BUCK_VOLT = 0x15,
  35. BD718XX_3RD_NODVS_BUCK_VOLT = 0x16,
  36. BD718XX_4TH_NODVS_BUCK_VOLT = 0x17,
  37. BD718XX_LDO1_VOLT = 0x18,
  38. BD718XX_LDO2_VOLT = 0x19,
  39. BD718XX_LDO3_VOLT = 0x1a,
  40. BD718XX_LDO4_VOLT = 0x1b,
  41. BD718XX_LDO5_VOLT = 0x1c,
  42. BD718XX_LDO6_VOLT = 0x1d,
  43. BD71837_LDO7_VOLT = 0x1e,
  44. BD718XX_TRANS_COND0 = 0x1f,
  45. BD718XX_TRANS_COND1 = 0x20,
  46. BD718XX_VRFAULTEN = 0x21,
  47. BD718XX_MVRFLTMASK0 = 0x22,
  48. BD718XX_MVRFLTMASK1 = 0x23,
  49. BD718XX_MVRFLTMASK2 = 0x24,
  50. BD718XX_RCVCFG = 0x25,
  51. BD718XX_RCVNUM = 0x26,
  52. BD718XX_PWRONCONFIG0 = 0x27,
  53. BD718XX_PWRONCONFIG1 = 0x28,
  54. BD718XX_RESETSRC = 0x29,
  55. BD718XX_MIRQ = 0x2a,
  56. BD718XX_IRQ = 0x2b,
  57. BD718XX_IN_MON = 0x2c,
  58. BD718XX_POW_STATE = 0x2d,
  59. BD718XX_OUT32K = 0x2e,
  60. BD718XX_REGLOCK = 0x2f,
  61. BD718XX_MUXSW_EN = 0x30,
  62. BD718XX_REG_OTPVER = 0xff,
  63. BD718XX_MAX_REGISTER = 0x100,
  64. };
  65. #define BD718XX_REGLOCK_PWRSEQ 0x1
  66. #define BD718XX_REGLOCK_VREG 0x10
  67. #define BD718XX_BUCK_EN 0x01
  68. #define BD718XX_LDO_EN 0x40
  69. #define BD718XX_BUCK_SEL 0x02
  70. #define BD718XX_LDO_SEL 0x80
  71. #define DVS_BUCK_RUN_MASK 0x3f
  72. #define BD718XX_1ST_NODVS_BUCK_MASK 0x07
  73. #define BD718XX_3RD_NODVS_BUCK_MASK 0x07
  74. #define BD718XX_4TH_NODVS_BUCK_MASK 0x3f
  75. #define BD71847_BUCK3_MASK 0x07
  76. #define BD71847_BUCK3_RANGE_MASK 0xc0
  77. #define BD71847_BUCK4_MASK 0x03
  78. #define BD71847_BUCK4_RANGE_MASK 0x40
  79. #define BD71837_BUCK5_RANGE_MASK 0x80
  80. #define BD71837_BUCK6_MASK 0x03
  81. #define BD718XX_LDO1_MASK 0x03
  82. #define BD718XX_LDO1_RANGE_MASK 0x20
  83. #define BD718XX_LDO2_MASK 0x20
  84. #define BD718XX_LDO3_MASK 0x0f
  85. #define BD718XX_LDO4_MASK 0x0f
  86. #define BD718XX_LDO6_MASK 0x0f
  87. #define BD71837_LDO5_MASK 0x0f
  88. #define BD71847_LDO5_MASK 0x0f
  89. #define BD71847_LDO5_RANGE_MASK 0x20
  90. #define BD71837_LDO7_MASK 0x0f
  91. #endif