pch.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #ifndef __pch_h
  7. #define __pch_h
  8. #define PCH_RCBA 0xf0
  9. #define BIOS_CTRL_BIOSWE BIT(0)
  10. /* All the supported PCH ioctls */
  11. enum pch_req_t {
  12. /* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
  13. PCH_REQ_HDA_CONFIG,
  14. /* Fills out a struct pch_pmbase_info if available */
  15. PCH_REQ_PMBASE_INFO,
  16. PCH_REQ_TEST1, /* Test requests for sandbox driver */
  17. PCH_REQ_TEST2,
  18. PCH_REQ_TEST3,
  19. PCH_REQ_COUNT, /* Number of ioctrls supported */
  20. };
  21. /**
  22. * struct pch_pmbase_info - Information filled in by PCH_REQ_PMBASE_INFO
  23. *
  24. * @pmbase: IO address of power-management controller
  25. * @gpio0_en_ofs: Offset of GPIO0 enable register
  26. * @pm1_sts_ofs: Offset of status register
  27. * @pm1_cnt_ofs: Offset of control register
  28. */
  29. struct pch_pmbase_info {
  30. u16 base;
  31. u8 gpio0_en_ofs;
  32. u8 pm1_sts_ofs;
  33. u8 pm1_cnt_ofs;
  34. };
  35. /**
  36. * struct pch_ops - Operations for the Platform Controller Hub
  37. *
  38. * Consider using ioctl() to add rarely used or driver-specific operations.
  39. */
  40. struct pch_ops {
  41. /**
  42. * get_spi_base() - get the address of SPI base
  43. *
  44. * @dev: PCH device to check
  45. * @sbasep: Returns address of SPI base if available, else 0
  46. * @return 0 if OK, -ve on error (e.g. there is no SPI base)
  47. */
  48. int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
  49. /**
  50. * set_spi_protect() - set whether SPI flash is protected or not
  51. *
  52. * @dev: PCH device to adjust
  53. * @protect: true to protect, false to unprotect
  54. *
  55. * @return 0 on success, -ENOSYS if not implemented
  56. */
  57. int (*set_spi_protect)(struct udevice *dev, bool protect);
  58. /**
  59. * get_gpio_base() - get the address of GPIO base
  60. *
  61. * @dev: PCH device to check
  62. * @gbasep: Returns address of GPIO base if available, else 0
  63. * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
  64. */
  65. int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
  66. /**
  67. * get_io_base() - get the address of IO base
  68. *
  69. * @dev: PCH device to check
  70. * @iobasep: Returns address of IO base if available, else 0
  71. * @return 0 if OK, -ve on error (e.g. there is no IO base)
  72. */
  73. int (*get_io_base)(struct udevice *dev, u32 *iobasep);
  74. /**
  75. * ioctl() - perform misc read/write operations
  76. *
  77. * This is a catch-all operation intended to avoid adding lots of
  78. * methods to this uclass, of which few are commonly used. Uncommon
  79. * operations that pertain only to a few devices in this uclass should
  80. * use this method instead of adding new methods.
  81. *
  82. * @dev: PCH device to check
  83. * @req: PCH request ID
  84. * @data: Input/output data
  85. * @size: Size of input data (and maximum size of output data)
  86. * @return size of output data on sucesss, -ve on error
  87. */
  88. int (*ioctl)(struct udevice *dev, enum pch_req_t req, void *data,
  89. int size);
  90. };
  91. #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
  92. /**
  93. * pch_get_spi_base() - get the address of SPI base
  94. *
  95. * @dev: PCH device to check
  96. * @sbasep: Returns address of SPI base if available, else 0
  97. * @return 0 if OK, -ve on error (e.g. there is no SPI base)
  98. */
  99. int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
  100. /**
  101. * set_spi_protect() - set whether SPI flash is protected or not
  102. *
  103. * @dev: PCH device to adjust
  104. * @protect: true to protect, false to unprotect
  105. *
  106. * @return 0 on success, -ENOSYS if not implemented
  107. */
  108. int pch_set_spi_protect(struct udevice *dev, bool protect);
  109. /**
  110. * pch_get_gpio_base() - get the address of GPIO base
  111. *
  112. * @dev: PCH device to check
  113. * @gbasep: Returns address of GPIO base if available, else 0
  114. * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
  115. */
  116. int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
  117. /**
  118. * pch_get_io_base() - get the address of IO base
  119. *
  120. * @dev: PCH device to check
  121. * @iobasep: Returns address of IO base if available, else 0
  122. * @return 0 if OK, -ve on error (e.g. there is no IO base)
  123. */
  124. int pch_get_io_base(struct udevice *dev, u32 *iobasep);
  125. /**
  126. * pch_ioctl() - perform misc read/write operations
  127. *
  128. * This is a catch-all operation intended to avoid adding lots of
  129. * methods to this uclass, of which few are commonly used. Uncommon
  130. * operations that pertain only to a few devices in this uclass should
  131. * use this method instead of adding new methods.
  132. *
  133. * @dev: PCH device to check
  134. * @req: PCH request ID
  135. * @data: Input/output data
  136. * @size: Size of input data (and maximum size of output data)
  137. * @return size of output data on sucesss, -ve on error
  138. */
  139. int pch_ioctl(struct udevice *dev, ulong req, void *data, int size);
  140. #endif