ns87308.h 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2000
  4. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  5. */
  6. #ifndef _NS87308_H_
  7. #define _NS87308_H_
  8. #include <asm/pci_io.h>
  9. /* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
  10. functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
  11. void initialise_ns87308(void);
  12. /*
  13. * The following struct represents the GPIO registers on the NS87308/NS97307
  14. */
  15. struct GPIO
  16. {
  17. unsigned char dta1; /* 0 data port 1 */
  18. unsigned char dir1; /* 1 direction port 1 */
  19. unsigned char out1; /* 2 output type port 1 */
  20. unsigned char puc1; /* 3 pull-up control port 1 */
  21. unsigned char dta2; /* 4 data port 2 */
  22. unsigned char dir2; /* 5 direction port 2 */
  23. unsigned char out2; /* 6 output type port 2 */
  24. unsigned char puc2; /* 7 pull-up control port 2 */
  25. };
  26. /*
  27. * The following represents the power management registers on the NS87308/NS97307
  28. */
  29. #define PWM_FER1 0 /* 0 function enable reg. 1 */
  30. #define PWM_FER2 1 /* 1 function enable reg. 2 */
  31. #define PWM_PMC1 2 /* 2 power mgmt. control 1 */
  32. #define PWM_PMC2 3 /* 3 power mgmt. control 2 */
  33. #define PWM_PMC3 4 /* 4 power mgmt. control 3 */
  34. #define PWM_WDTO 5 /* 5 watchdog time-out */
  35. #define PWM_WDCF 6 /* 6 watchdog config. */
  36. #define PWM_WDST 7 /* 7 watchdog status */
  37. /*PNP config registers:
  38. * these depend on the stated of BADDR1 and BADDR0 on startup
  39. * so there's three versions here with the last two digits indicating
  40. * for which configuration their valid
  41. * the 1st of the two digits indicates the state of BADDR1
  42. * the 2st of the two digits indicates the state of BADDR0
  43. */
  44. #define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
  45. #define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
  46. #define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
  47. #define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
  48. #define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
  49. #define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
  50. #if defined(CONFIG_SYS_NS87308_BADDR_0x)
  51. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
  52. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
  53. #elif defined(CONFIG_SYS_NS87308_BADDR_10)
  54. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
  55. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
  56. #elif defined(CONFIG_SYS_NS87308_BADDR_11)
  57. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
  58. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
  59. #endif
  60. /* PnP register definitions */
  61. #define SET_RD_DATA_PORT 0x00
  62. #define SERIAL_ISOLATION 0x01
  63. #define CONFIG_CONTROL 0x02
  64. #define WAKE_CSN 0x03
  65. #define RES_DATA 0x04
  66. #define STATUS 0x05
  67. #define SET_CSN 0x06
  68. #define LOGICAL_DEVICE 0x07
  69. /*vendor defined values */
  70. #define SID_REG 0x20
  71. #define SUPOERIO_CONF1 0x21
  72. #define SUPOERIO_CONF2 0x22
  73. #define PGCS_INDEX 0x23
  74. #define PGCS_DATA 0x24
  75. /* values above 30 are different for each logical device
  76. but I can't be arsed to enter them all. the ones here
  77. are pretty consistent between all logical devices
  78. feel free to correct the situation if you want.. ;)
  79. */
  80. #define ACTIVATE 0x30
  81. #define ACTIVATE_OFF 0x00
  82. #define ACTIVATE_ON 0x01
  83. #define BASE_ADDR_HIGH 0x60
  84. #define BASE_ADDR_LOW 0x61
  85. #define LUN_CONFIG_REG 0xF0
  86. #define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
  87. #define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
  88. #define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
  89. #define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
  90. /* the logical devices*/
  91. #define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
  92. #define LDEV_KBC2 0x01
  93. #define LDEV_MOUSE 0x01
  94. #define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
  95. #define LDEV_FDC 0x03 /*floppy disk controller*/
  96. #define LDEV_PARP 0x04 /*Parallel port*/
  97. #define LDEV_UART2 0x05
  98. #define LDEV_UART1 0x06
  99. #define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
  100. #define LDEV_POWRMAN 0x08 /*Power Managment*/
  101. #define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
  102. #define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
  103. #define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
  104. #define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
  105. #define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
  106. #define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
  107. #define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
  108. #define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
  109. #define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
  110. #define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
  111. /*some functions and macro's for doing configuration */
  112. static inline void read_pnp_config(unsigned char index, unsigned char *data)
  113. {
  114. pci_writeb(index,IO_INDEX);
  115. pci_readb(IO_DATA, *data);
  116. }
  117. static inline void write_pnp_config(unsigned char index, unsigned char data)
  118. {
  119. pci_writeb(index,IO_INDEX);
  120. pci_writeb(data, IO_DATA);
  121. }
  122. static inline void pnp_set_device(unsigned char dev)
  123. {
  124. write_pnp_config(LOGICAL_DEVICE, dev);
  125. }
  126. static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
  127. {
  128. pci_writeb(index, CONFIG_SYS_ISA_IO + base);
  129. eieio();
  130. pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
  131. }
  132. /*void write_pnp_config(unsigned char index, unsigned char data);
  133. void pnp_set_device(unsigned char dev);
  134. */
  135. #define PNP_SET_DEVICE_BASE(dev,base) \
  136. pnp_set_device(dev); \
  137. write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
  138. write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
  139. write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
  140. write_pnp_config(ACTIVATE, ACTIVATE_ON);
  141. #define PNP_ACTIVATE_DEVICE(dev) \
  142. pnp_set_device(dev); \
  143. write_pnp_config(ACTIVATE, ACTIVATE_ON);
  144. #define PNP_DEACTIVATE_DEVICE(dev) \
  145. pnp_set_device(dev); \
  146. write_pnp_config(ACTIVATE, ACTIVATE_OFF);
  147. static inline void write_pgcs_config(unsigned char index, unsigned char data)
  148. {
  149. write_pnp_config(PGCS_INDEX, index);
  150. write_pnp_config(PGCS_DATA, data);
  151. }
  152. /* these macrose configure the 3 CS lines
  153. on the sandpoint board these controll NVRAM
  154. CS0 is connected to NVRAMCS
  155. CS1 is connected to NVRAMAS0
  156. CS2 is connected to NVRAMAS1
  157. */
  158. #define PGCS_CS_ASSERT_ON_WRITE 0x10
  159. #define PGCS_CS_ASSERT_ON_READ 0x20
  160. #define PNP_PGCS_CSLINE_BASE(cs, base) \
  161. write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
  162. write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
  163. #define PNP_PGCS_CSLINE_CONF(cs, conf) \
  164. write_pgcs_config(((cs) << 2) + 2, (conf) );
  165. /* The following sections are for 87308 extensions to the standard compoents it emulates */
  166. /* extensions to 16550*/
  167. #define MCR_MDSL_MSK 0xe0 /*mode select mask*/
  168. #define MCR_MDSL_UART 0x00 /*uart, default*/
  169. #define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
  170. #define MCR_MDSL_SIR 0x03 /*SIR*/
  171. #define MCR_MDSL_CIR 0x06 /*Consumer IR*/
  172. #define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
  173. #define FCR_TXFTH1 0x20 /* for interrupt trigger */
  174. /*
  175. * Default NS87308 configuration
  176. */
  177. #ifndef CONFIG_SYS_NS87308_KBC1_BASE
  178. #define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
  179. #endif
  180. #ifndef CONFIG_SYS_NS87308_RTC_BASE
  181. #define CONFIG_SYS_NS87308_RTC_BASE 0x0070
  182. #endif
  183. #ifndef CONFIG_SYS_NS87308_FDC_BASE
  184. #define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
  185. #endif
  186. #ifndef CONFIG_SYS_NS87308_LPT_BASE
  187. #define CONFIG_SYS_NS87308_LPT_BASE 0x0278
  188. #endif
  189. #ifndef CONFIG_SYS_NS87308_UART1_BASE
  190. #define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
  191. #endif
  192. #ifndef CONFIG_SYS_NS87308_UART2_BASE
  193. #define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
  194. #endif
  195. #endif /*_NS87308_H_*/