pfe_eth.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #ifndef __PFE_ETH_H__
  7. #define __PFE_ETH_H__
  8. #include <linux/sizes.h>
  9. #include <asm/io.h>
  10. #include <miiphy.h>
  11. #include <malloc.h>
  12. #include "pfe_driver.h"
  13. #define BMU2_DDR_BASEADDR 0
  14. #define BMU2_BUF_COUNT (3 * SZ_1K)
  15. #define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
  16. #define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
  17. #define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
  18. #define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
  19. #define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
  20. #define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
  21. #define HIF_RX_DESC_SIZE (16 * HIF_RX_DESC_NT)
  22. #define HIF_TX_DESC_SIZE (16 * HIF_TX_DESC_NT)
  23. #define UTIL_CODE_BASEADDR 0x780000
  24. #define UTIL_CODE_SIZE (128 * SZ_1K)
  25. #define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
  26. #define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
  27. #define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
  28. #define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
  29. #define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
  30. #define TMU_DDR_DATA_SIZE (32 * SZ_1K)
  31. #define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
  32. #define TMU_LLM_QUEUE_LEN (16 * 256)
  33. /* Must be power of two and at least 16 * 8 = 128 bytes */
  34. #define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN)
  35. /* (4 TMU's x 16 queues x queue_len) */
  36. #define ROUTE_TABLE_BASEADDR 0x800000
  37. #define ROUTE_TABLE_HASH_BITS_MAX 15 /* 32K entries */
  38. #define ROUTE_TABLE_HASH_BITS 8 /* 256 entries */
  39. #define ROUTE_TABLE_SIZE (BIT(ROUTE_TABLE_HASH_BITS_MAX) \
  40. * CLASS_ROUTE_SIZE)
  41. #define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
  42. #if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
  43. #error DDR mapping above 12MiB
  44. #endif
  45. /* LMEM Mapping */
  46. #define BMU1_LMEM_BASEADDR 0
  47. #define BMU1_BUF_COUNT 256
  48. #define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
  49. struct gemac_s {
  50. void *gemac_base;
  51. void *egpi_base;
  52. /* GEMAC config */
  53. int gemac_mode;
  54. int gemac_speed;
  55. int gemac_duplex;
  56. int flags;
  57. /* phy iface */
  58. int phy_address;
  59. int phy_mode;
  60. struct mii_dev *bus;
  61. };
  62. struct pfe_mdio_info {
  63. void *reg_base;
  64. char *name;
  65. };
  66. struct pfe_eth_dev {
  67. int gemac_port;
  68. struct gemac_s *gem;
  69. struct pfe_ddr_address pfe_addr;
  70. struct udevice *dev;
  71. #ifdef CONFIG_PHYLIB
  72. struct phy_device *phydev;
  73. #endif
  74. };
  75. int pfe_remove(struct pfe_ddr_address *pfe_addr);
  76. struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info);
  77. void pfe_set_mdio(int dev_id, struct mii_dev *bus);
  78. void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
  79. int gemac_initialize(bd_t *bis, int dev_id, char *devname);
  80. int pfe_init(struct pfe_ddr_address *pfe_addr);
  81. int pfe_eth_board_init(struct udevice *dev);
  82. #endif /* __PFE_ETH_H__ */