mpc83xx.h 49 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __MPC83XX_H__
  6. #define __MPC83XX_H__
  7. #include <config.h>
  8. #include <asm/fsl_lbc.h>
  9. #if defined(CONFIG_E300)
  10. #include <asm/e300.h>
  11. #endif
  12. /*
  13. * MPC83xx cpu provide RCR register to do reset thing specially
  14. */
  15. #define MPC83xx_RESET
  16. /*
  17. * System reset offset (PowerPC standard)
  18. */
  19. #define EXC_OFF_SYS_RESET 0x0100
  20. #define _START_OFFSET EXC_OFF_SYS_RESET
  21. /*
  22. * IMMRBAR - Internal Memory Register Base Address
  23. */
  24. #ifndef CONFIG_DEFAULT_IMMR
  25. /* Default IMMR base address */
  26. #define CONFIG_DEFAULT_IMMR 0xFF400000
  27. #endif
  28. /* Register offset to immr */
  29. #define IMMRBAR 0x0000
  30. #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
  31. #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
  32. /*
  33. * LAWBAR - Local Access Window Base Address Register
  34. */
  35. /* Register offset to immr */
  36. #define LBLAWBAR0 0x0020
  37. #define LBLAWAR0 0x0024
  38. #define LBLAWBAR1 0x0028
  39. #define LBLAWAR1 0x002C
  40. #define LBLAWBAR2 0x0030
  41. #define LBLAWAR2 0x0034
  42. #define LBLAWBAR3 0x0038
  43. #define LBLAWAR3 0x003C
  44. #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
  45. /*
  46. * SPRIDR - System Part and Revision ID Register
  47. */
  48. #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
  49. #define SPRIDR_REVID 0x0000FFFF /* Revision Id */
  50. #if defined(CONFIG_ARCH_MPC834X)
  51. #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
  52. #define REVID_MINOR(spridr) (spridr & 0x000000FF)
  53. #else
  54. #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
  55. #define REVID_MINOR(spridr) (spridr & 0x0000000F)
  56. #endif
  57. #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
  58. #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
  59. #define SPR_8308 0x8100
  60. #define SPR_8309 0x8110
  61. #define SPR_831X_FAMILY 0x80B
  62. #define SPR_8311 0x80B2
  63. #define SPR_8313 0x80B0
  64. #define SPR_8314 0x80B6
  65. #define SPR_8315 0x80B4
  66. #define SPR_832X_FAMILY 0x806
  67. #define SPR_8321 0x8066
  68. #define SPR_8323 0x8062
  69. #define SPR_834X_FAMILY 0x803
  70. #define SPR_8343 0x8036
  71. #define SPR_8347_TBGA_ 0x8032
  72. #define SPR_8347_PBGA_ 0x8034
  73. #define SPR_8349 0x8030
  74. #define SPR_836X_FAMILY 0x804
  75. #define SPR_8358_TBGA_ 0x804A
  76. #define SPR_8358_PBGA_ 0x804E
  77. #define SPR_8360 0x8048
  78. #define SPR_837X_FAMILY 0x80C
  79. #define SPR_8377 0x80C6
  80. #define SPR_8378 0x80C4
  81. #define SPR_8379 0x80C2
  82. /*
  83. * SPCR - System Priority Configuration Register
  84. */
  85. /* PCI Highest Priority Enable */
  86. #define SPCR_PCIHPE 0x10000000
  87. #define SPCR_PCIHPE_SHIFT (31-3)
  88. /* PCI bridge system bus request priority */
  89. #define SPCR_PCIPR 0x03000000
  90. #define SPCR_PCIPR_SHIFT (31-7)
  91. #define SPCR_OPT 0x00800000 /* Optimize */
  92. #define SPCR_OPT_SHIFT (31-8)
  93. /* E300 PowerPC core time base unit enable */
  94. #define SPCR_TBEN 0x00400000
  95. #define SPCR_TBEN_SHIFT (31-9)
  96. /* E300 PowerPC Core system bus request priority */
  97. #define SPCR_COREPR 0x00300000
  98. #define SPCR_COREPR_SHIFT (31-11)
  99. #if defined(CONFIG_ARCH_MPC834X)
  100. /* SPCR bits - MPC8349 specific */
  101. /* TSEC1 data priority */
  102. #define SPCR_TSEC1DP 0x00003000
  103. #define SPCR_TSEC1DP_SHIFT (31-19)
  104. /* TSEC1 buffer descriptor priority */
  105. #define SPCR_TSEC1BDP 0x00000C00
  106. #define SPCR_TSEC1BDP_SHIFT (31-21)
  107. /* TSEC1 emergency priority */
  108. #define SPCR_TSEC1EP 0x00000300
  109. #define SPCR_TSEC1EP_SHIFT (31-23)
  110. /* TSEC2 data priority */
  111. #define SPCR_TSEC2DP 0x00000030
  112. #define SPCR_TSEC2DP_SHIFT (31-27)
  113. /* TSEC2 buffer descriptor priority */
  114. #define SPCR_TSEC2BDP 0x0000000C
  115. #define SPCR_TSEC2BDP_SHIFT (31-29)
  116. /* TSEC2 emergency priority */
  117. #define SPCR_TSEC2EP 0x00000003
  118. #define SPCR_TSEC2EP_SHIFT (31-31)
  119. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  120. defined(CONFIG_ARCH_MPC837X)
  121. /* SPCR bits - MPC8308, MPC831x and MPC837X specific */
  122. /* TSEC data priority */
  123. #define SPCR_TSECDP 0x00003000
  124. #define SPCR_TSECDP_SHIFT (31-19)
  125. /* TSEC buffer descriptor priority */
  126. #define SPCR_TSECBDP 0x00000C00
  127. #define SPCR_TSECBDP_SHIFT (31-21)
  128. /* TSEC emergency priority */
  129. #define SPCR_TSECEP 0x00000300
  130. #define SPCR_TSECEP_SHIFT (31-23)
  131. #endif
  132. /* SICRL/H - System I/O Configuration Register Low/High
  133. */
  134. #if defined(CONFIG_ARCH_MPC834X)
  135. /* SICRL bits - MPC8349 specific */
  136. #define SICRL_LDP_A 0x80000000
  137. #define SICRL_USB1 0x40000000
  138. #define SICRL_USB0 0x20000000
  139. #define SICRL_UART 0x0C000000
  140. #define SICRL_GPIO1_A 0x02000000
  141. #define SICRL_GPIO1_B 0x01000000
  142. #define SICRL_GPIO1_C 0x00800000
  143. #define SICRL_GPIO1_D 0x00400000
  144. #define SICRL_GPIO1_E 0x00200000
  145. #define SICRL_GPIO1_F 0x00180000
  146. #define SICRL_GPIO1_G 0x00040000
  147. #define SICRL_GPIO1_H 0x00020000
  148. #define SICRL_GPIO1_I 0x00010000
  149. #define SICRL_GPIO1_J 0x00008000
  150. #define SICRL_GPIO1_K 0x00004000
  151. #define SICRL_GPIO1_L 0x00003000
  152. /* SICRH bits - MPC8349 specific */
  153. #define SICRH_DDR 0x80000000
  154. #define SICRH_TSEC1_A 0x10000000
  155. #define SICRH_TSEC1_B 0x08000000
  156. #define SICRH_TSEC1_C 0x04000000
  157. #define SICRH_TSEC1_D 0x02000000
  158. #define SICRH_TSEC1_E 0x01000000
  159. #define SICRH_TSEC1_F 0x00800000
  160. #define SICRH_TSEC2_A 0x00400000
  161. #define SICRH_TSEC2_B 0x00200000
  162. #define SICRH_TSEC2_C 0x00100000
  163. #define SICRH_TSEC2_D 0x00080000
  164. #define SICRH_TSEC2_E 0x00040000
  165. #define SICRH_TSEC2_F 0x00020000
  166. #define SICRH_TSEC2_G 0x00010000
  167. #define SICRH_TSEC2_H 0x00008000
  168. #define SICRH_GPIO2_A 0x00004000
  169. #define SICRH_GPIO2_B 0x00002000
  170. #define SICRH_GPIO2_C 0x00001000
  171. #define SICRH_GPIO2_D 0x00000800
  172. #define SICRH_GPIO2_E 0x00000400
  173. #define SICRH_GPIO2_F 0x00000200
  174. #define SICRH_GPIO2_G 0x00000180
  175. #define SICRH_GPIO2_H 0x00000060
  176. #define SICRH_TSOBI1 0x00000002
  177. #define SICRH_TSOBI2 0x00000001
  178. #elif defined(CONFIG_ARCH_MPC8360)
  179. /* SICRL bits - MPC8360 specific */
  180. #define SICRL_LDP_A 0xC0000000
  181. #define SICRL_LCLK_1 0x10000000
  182. #define SICRL_LCLK_2 0x08000000
  183. #define SICRL_SRCID_A 0x03000000
  184. #define SICRL_IRQ_CKSTP_A 0x00C00000
  185. /* SICRH bits - MPC8360 specific */
  186. #define SICRH_DDR 0x80000000
  187. #define SICRH_SECONDARY_DDR 0x40000000
  188. #define SICRH_SDDROE 0x20000000
  189. #define SICRH_IRQ3 0x10000000
  190. #define SICRH_UC1EOBI 0x00000004
  191. #define SICRH_UC2E1OBI 0x00000002
  192. #define SICRH_UC2E2OBI 0x00000001
  193. #elif defined(CONFIG_ARCH_MPC832X)
  194. /* SICRL bits - MPC832x specific */
  195. #define SICRL_LDP_LCS_A 0x80000000
  196. #define SICRL_IRQ_CKS 0x20000000
  197. #define SICRL_PCI_MSRC 0x10000000
  198. #define SICRL_URT_CTPR 0x06000000
  199. #define SICRL_IRQ_CTPR 0x00C00000
  200. #elif defined(CONFIG_ARCH_MPC8313)
  201. /* SICRL bits - MPC8313 specific */
  202. #define SICRL_LBC 0x30000000
  203. #define SICRL_UART 0x0C000000
  204. #define SICRL_SPI_A 0x03000000
  205. #define SICRL_SPI_B 0x00C00000
  206. #define SICRL_SPI_C 0x00300000
  207. #define SICRL_SPI_D 0x000C0000
  208. #define SICRL_USBDR_11 0x00000C00
  209. #define SICRL_USBDR_10 0x00000800
  210. #define SICRL_USBDR_01 0x00000400
  211. #define SICRL_USBDR_00 0x00000000
  212. #define SICRL_ETSEC1_A 0x0000000C
  213. #define SICRL_ETSEC2_A 0x00000003
  214. /* SICRH bits - MPC8313 specific */
  215. #define SICRH_INTR_A 0x02000000
  216. #define SICRH_INTR_B 0x00C00000
  217. #define SICRH_IIC 0x00300000
  218. #define SICRH_ETSEC2_B 0x000C0000
  219. #define SICRH_ETSEC2_C 0x00030000
  220. #define SICRH_ETSEC2_D 0x0000C000
  221. #define SICRH_ETSEC2_E 0x00003000
  222. #define SICRH_ETSEC2_F 0x00000C00
  223. #define SICRH_ETSEC2_G 0x00000300
  224. #define SICRH_ETSEC1_B 0x00000080
  225. #define SICRH_ETSEC1_C 0x00000060
  226. #define SICRH_GTX1_DLY 0x00000008
  227. #define SICRH_GTX2_DLY 0x00000004
  228. #define SICRH_TSOBI1 0x00000002
  229. #define SICRH_TSOBI2 0x00000001
  230. #elif defined(CONFIG_ARCH_MPC8315)
  231. /* SICRL bits - MPC8315 specific */
  232. #define SICRL_DMA_CH0 0xc0000000
  233. #define SICRL_DMA_SPI 0x30000000
  234. #define SICRL_UART 0x0c000000
  235. #define SICRL_IRQ4 0x02000000
  236. #define SICRL_IRQ5 0x01800000
  237. #define SICRL_IRQ6_7 0x00400000
  238. #define SICRL_IIC1 0x00300000
  239. #define SICRL_TDM 0x000c0000
  240. #define SICRL_TDM_SHARED 0x00030000
  241. #define SICRL_PCI_A 0x0000c000
  242. #define SICRL_ELBC_A 0x00003000
  243. #define SICRL_ETSEC1_A 0x000000c0
  244. #define SICRL_ETSEC1_B 0x00000030
  245. #define SICRL_ETSEC1_C 0x0000000c
  246. #define SICRL_TSEXPOBI 0x00000001
  247. /* SICRH bits - MPC8315 specific */
  248. #define SICRH_GPIO_0 0xc0000000
  249. #define SICRH_GPIO_1 0x30000000
  250. #define SICRH_GPIO_2 0x0c000000
  251. #define SICRH_GPIO_3 0x03000000
  252. #define SICRH_GPIO_4 0x00c00000
  253. #define SICRH_GPIO_5 0x00300000
  254. #define SICRH_GPIO_6 0x000c0000
  255. #define SICRH_GPIO_7 0x00030000
  256. #define SICRH_GPIO_8 0x0000c000
  257. #define SICRH_GPIO_9 0x00003000
  258. #define SICRH_GPIO_10 0x00000c00
  259. #define SICRH_GPIO_11 0x00000300
  260. #define SICRH_ETSEC2_A 0x000000c0
  261. #define SICRH_TSOBI1 0x00000002
  262. #define SICRH_TSOBI2 0x00000001
  263. #elif defined(CONFIG_ARCH_MPC837X)
  264. /* SICRL bits - MPC837X specific */
  265. #define SICRL_USB_A 0xC0000000
  266. #define SICRL_USB_B 0x30000000
  267. #define SICRL_USB_B_SD 0x20000000
  268. #define SICRL_UART 0x0C000000
  269. #define SICRL_GPIO_A 0x02000000
  270. #define SICRL_GPIO_B 0x01000000
  271. #define SICRL_GPIO_C 0x00800000
  272. #define SICRL_GPIO_D 0x00400000
  273. #define SICRL_GPIO_E 0x00200000
  274. #define SICRL_GPIO_F 0x00180000
  275. #define SICRL_GPIO_G 0x00040000
  276. #define SICRL_GPIO_H 0x00020000
  277. #define SICRL_GPIO_I 0x00010000
  278. #define SICRL_GPIO_J 0x00008000
  279. #define SICRL_GPIO_K 0x00004000
  280. #define SICRL_GPIO_L 0x00003000
  281. #define SICRL_DMA_A 0x00000800
  282. #define SICRL_DMA_B 0x00000400
  283. #define SICRL_DMA_C 0x00000200
  284. #define SICRL_DMA_D 0x00000100
  285. #define SICRL_DMA_E 0x00000080
  286. #define SICRL_DMA_F 0x00000040
  287. #define SICRL_DMA_G 0x00000020
  288. #define SICRL_DMA_H 0x00000010
  289. #define SICRL_DMA_I 0x00000008
  290. #define SICRL_DMA_J 0x00000004
  291. #define SICRL_LDP_A 0x00000002
  292. #define SICRL_LDP_B 0x00000001
  293. /* SICRH bits - MPC837X specific */
  294. #define SICRH_DDR 0x80000000
  295. #define SICRH_TSEC1_A 0x10000000
  296. #define SICRH_TSEC1_B 0x08000000
  297. #define SICRH_TSEC2_A 0x00400000
  298. #define SICRH_TSEC2_B 0x00200000
  299. #define SICRH_TSEC2_C 0x00100000
  300. #define SICRH_TSEC2_D 0x00080000
  301. #define SICRH_TSEC2_E 0x00040000
  302. #define SICRH_TMR 0x00010000
  303. #define SICRH_GPIO2_A 0x00008000
  304. #define SICRH_GPIO2_B 0x00004000
  305. #define SICRH_GPIO2_C 0x00002000
  306. #define SICRH_GPIO2_D 0x00001000
  307. #define SICRH_GPIO2_E 0x00000C00
  308. #define SICRH_GPIO2_E_SD 0x00000800
  309. #define SICRH_GPIO2_F 0x00000300
  310. #define SICRH_GPIO2_G 0x000000C0
  311. #define SICRH_GPIO2_H 0x00000030
  312. #define SICRH_SPI 0x00000003
  313. #define SICRH_SPI_SD 0x00000001
  314. #elif defined(CONFIG_ARCH_MPC8308)
  315. /* SICRL bits - MPC8308 specific */
  316. #define SICRL_SPI_PF0 (0 << 28)
  317. #define SICRL_SPI_PF1 (1 << 28)
  318. #define SICRL_SPI_PF3 (3 << 28)
  319. #define SICRL_UART_PF0 (0 << 26)
  320. #define SICRL_UART_PF1 (1 << 26)
  321. #define SICRL_UART_PF3 (3 << 26)
  322. #define SICRL_IRQ_PF0 (0 << 24)
  323. #define SICRL_IRQ_PF1 (1 << 24)
  324. #define SICRL_I2C2_PF0 (0 << 20)
  325. #define SICRL_I2C2_PF1 (1 << 20)
  326. #define SICRL_ETSEC1_TX_CLK (0 << 6)
  327. #define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
  328. /* SICRH bits - MPC8308 specific */
  329. #define SICRH_ESDHC_A_SD (0 << 30)
  330. #define SICRH_ESDHC_A_GTM (1 << 30)
  331. #define SICRH_ESDHC_A_GPIO (3 << 30)
  332. #define SICRH_ESDHC_B_SD (0 << 28)
  333. #define SICRH_ESDHC_B_GTM (1 << 28)
  334. #define SICRH_ESDHC_B_GPIO (3 << 28)
  335. #define SICRH_ESDHC_C_SD (0 << 26)
  336. #define SICRH_ESDHC_C_GTM (1 << 26)
  337. #define SICRH_ESDHC_C_GPIO (3 << 26)
  338. #define SICRH_GPIO_A_GPIO (0 << 24)
  339. #define SICRH_GPIO_A_TSEC2 (1 << 24)
  340. #define SICRH_GPIO_B_GPIO (0 << 22)
  341. #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
  342. #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
  343. #define SICRH_IEEE1588_A_TMR (1 << 20)
  344. #define SICRH_IEEE1588_A_GPIO (3 << 20)
  345. #define SICRH_USB (1 << 18)
  346. #define SICRH_GTM_GTM (1 << 16)
  347. #define SICRH_GTM_GPIO (3 << 16)
  348. #define SICRH_IEEE1588_B_TMR (1 << 14)
  349. #define SICRH_IEEE1588_B_GPIO (3 << 14)
  350. #define SICRH_ETSEC2_CRS (1 << 12)
  351. #define SICRH_ETSEC2_GPIO (3 << 12)
  352. #define SICRH_GPIOSEL_0 (0 << 8)
  353. #define SICRH_GPIOSEL_1 (1 << 8)
  354. #define SICRH_TMROBI_V3P3 (0 << 4)
  355. #define SICRH_TMROBI_V2P5 (1 << 4)
  356. #define SICRH_TSOBI1_V3P3 (0 << 1)
  357. #define SICRH_TSOBI1_V2P5 (1 << 1)
  358. #define SICRH_TSOBI2_V3P3 (0 << 0)
  359. #define SICRH_TSOBI2_V2P5 (1 << 0)
  360. #elif defined(CONFIG_ARCH_MPC8309)
  361. /* SICR_1 */
  362. #define SICR_1_UART1_UART1S (0 << (30-2))
  363. #define SICR_1_UART1_UART1RTS (1 << (30-2))
  364. #define SICR_1_I2C_I2C (0 << (30-4))
  365. #define SICR_1_I2C_CKSTOP (1 << (30-4))
  366. #define SICR_1_IRQ_A_IRQ (0 << (30-6))
  367. #define SICR_1_IRQ_A_MCP (1 << (30-6))
  368. #define SICR_1_IRQ_B_IRQ (0 << (30-8))
  369. #define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
  370. #define SICR_1_GPIO_A_GPIO (0 << (30-10))
  371. #define SICR_1_GPIO_A_SD (2 << (30-10))
  372. #define SICR_1_GPIO_A_DDR (3 << (30-10))
  373. #define SICR_1_GPIO_B_GPIO (0 << (30-12))
  374. #define SICR_1_GPIO_B_SD (2 << (30-12))
  375. #define SICR_1_GPIO_B_QE (3 << (30-12))
  376. #define SICR_1_GPIO_C_GPIO (0 << (30-14))
  377. #define SICR_1_GPIO_C_CAN (1 << (30-14))
  378. #define SICR_1_GPIO_C_DDR (2 << (30-14))
  379. #define SICR_1_GPIO_C_LCS (3 << (30-14))
  380. #define SICR_1_GPIO_D_GPIO (0 << (30-16))
  381. #define SICR_1_GPIO_D_CAN (1 << (30-16))
  382. #define SICR_1_GPIO_D_DDR (2 << (30-16))
  383. #define SICR_1_GPIO_D_LCS (3 << (30-16))
  384. #define SICR_1_GPIO_E_GPIO (0 << (30-18))
  385. #define SICR_1_GPIO_E_CAN (1 << (30-18))
  386. #define SICR_1_GPIO_E_DDR (2 << (30-18))
  387. #define SICR_1_GPIO_E_LCS (3 << (30-18))
  388. #define SICR_1_GPIO_F_GPIO (0 << (30-20))
  389. #define SICR_1_GPIO_F_CAN (1 << (30-20))
  390. #define SICR_1_GPIO_F_CK (2 << (30-20))
  391. #define SICR_1_USB_A_USBDR (0 << (30-22))
  392. #define SICR_1_USB_A_UART2S (1 << (30-22))
  393. #define SICR_1_USB_B_USBDR (0 << (30-24))
  394. #define SICR_1_USB_B_UART2S (1 << (30-24))
  395. #define SICR_1_USB_B_UART2RTS (2 << (30-24))
  396. #define SICR_1_USB_C_USBDR (0 << (30-26))
  397. #define SICR_1_USB_C_QE_EXT (3 << (30-26))
  398. #define SICR_1_FEC1_FEC1 (0 << (30-28))
  399. #define SICR_1_FEC1_GTM (1 << (30-28))
  400. #define SICR_1_FEC1_GPIO (2 << (30-28))
  401. #define SICR_1_FEC2_FEC2 (0 << (30-30))
  402. #define SICR_1_FEC2_GTM (1 << (30-30))
  403. #define SICR_1_FEC2_GPIO (2 << (30-30))
  404. /* SICR_2 */
  405. #define SICR_2_FEC3_FEC3 (0 << (30-0))
  406. #define SICR_2_FEC3_TMR (1 << (30-0))
  407. #define SICR_2_FEC3_GPIO (2 << (30-0))
  408. #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
  409. #define SICR_2_HDLC1_A_GPIO (1 << (30-2))
  410. #define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
  411. #define SICR_2_ELBC_A_LA (0 << (30-4))
  412. #define SICR_2_ELBC_B_LCLK (0 << (30-6))
  413. #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
  414. #define SICR_2_HDLC2_A_GPIO (0 << (30-8))
  415. #define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
  416. /* bits 10-11 unused */
  417. #define SICR_2_USB_D_USBDR (0 << (30-12))
  418. #define SICR_2_USB_D_GPIO (2 << (30-12))
  419. #define SICR_2_USB_D_QE_BRG (3 << (30-12))
  420. #define SICR_2_PCI_PCI (0 << (30-14))
  421. #define SICR_2_PCI_CPCI_HS (2 << (30-14))
  422. #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
  423. #define SICR_2_HDLC1_B_GPIO (1 << (30-16))
  424. #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
  425. #define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
  426. #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
  427. #define SICR_2_HDLC1_C_GPIO (1 << (30-18))
  428. #define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
  429. #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
  430. #define SICR_2_HDLC2_B_GPIO (1 << (30-20))
  431. #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
  432. #define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
  433. #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
  434. #define SICR_2_HDLC2_C_GPIO (1 << (30-22))
  435. #define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
  436. #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
  437. #define SICR_2_QUIESCE_B (0 << (30-24))
  438. #endif
  439. /*
  440. * SWCRR - System Watchdog Control Register
  441. */
  442. /* Register offset to immr */
  443. #define SWCRR 0x0204
  444. /* Software Watchdog Time Count */
  445. #define SWCRR_SWTC 0xFFFF0000
  446. /* Watchdog Enable bit */
  447. #define SWCRR_SWEN 0x00000004
  448. /* Software Watchdog Reset/Interrupt Select bit */
  449. #define SWCRR_SWRI 0x00000002
  450. /* Software Watchdog Counter Prescale bit */
  451. #define SWCRR_SWPR 0x00000001
  452. #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
  453. SWCRR_SWRI | SWCRR_SWPR))
  454. /*
  455. * SWCNR - System Watchdog Counter Register
  456. */
  457. /* Register offset to immr */
  458. #define SWCNR 0x0208
  459. /* Software Watchdog Count mask */
  460. #define SWCNR_SWCN 0x0000FFFF
  461. #define SWCNR_RES ~(SWCNR_SWCN)
  462. /*
  463. * SWSRR - System Watchdog Service Register
  464. */
  465. /* Register offset to immr */
  466. #define SWSRR 0x020E
  467. /*
  468. * ACR - Arbiter Configuration Register
  469. */
  470. #define ACR_COREDIS 0x10000000 /* Core disable */
  471. #define ACR_COREDIS_SHIFT (31-7)
  472. #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
  473. #define ACR_PIPE_DEP_SHIFT (31-15)
  474. #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
  475. #define ACR_PCI_RPTCNT_SHIFT (31-19)
  476. #define ACR_RPTCNT 0x00000700 /* Repeat count */
  477. #define ACR_RPTCNT_SHIFT (31-23)
  478. #define ACR_APARK 0x00000030 /* Address parking */
  479. #define ACR_APARK_SHIFT (31-27)
  480. #define ACR_PARKM 0x0000000F /* Parking master */
  481. #define ACR_PARKM_SHIFT (31-31)
  482. /*
  483. * ATR - Arbiter Timers Register
  484. */
  485. #define ATR_DTO 0x00FF0000 /* Data time out */
  486. #define ATR_DTO_SHIFT 16
  487. #define ATR_ATO 0x000000FF /* Address time out */
  488. #define ATR_ATO_SHIFT 0
  489. /*
  490. * AER - Arbiter Event Register
  491. */
  492. #define AER_ETEA 0x00000020 /* Transfer error */
  493. /* Reserved transfer type */
  494. #define AER_RES 0x00000010
  495. /* External control word transfer type */
  496. #define AER_ECW 0x00000008
  497. /* Address Only transfer type */
  498. #define AER_AO 0x00000004
  499. #define AER_DTO 0x00000002 /* Data time out */
  500. #define AER_ATO 0x00000001 /* Address time out */
  501. /*
  502. * AEATR - Arbiter Event Address Register
  503. */
  504. #define AEATR_EVENT 0x07000000 /* Event type */
  505. #define AEATR_EVENT_SHIFT 24
  506. #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
  507. #define AEATR_MSTR_ID_SHIFT 16
  508. #define AEATR_TBST 0x00000800 /* Transfer burst */
  509. #define AEATR_TBST_SHIFT 11
  510. #define AEATR_TSIZE 0x00000700 /* Transfer Size */
  511. #define AEATR_TSIZE_SHIFT 8
  512. #define AEATR_TTYPE 0x0000001F /* Transfer Type */
  513. #define AEATR_TTYPE_SHIFT 0
  514. /*
  515. * HRCWL - Hard Reset Configuration Word Low
  516. */
  517. #define HRCWL_LBIUCM 0x80000000
  518. #define HRCWL_LBIUCM_SHIFT 31
  519. #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
  520. #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
  521. #define HRCWL_DDRCM 0x40000000
  522. #define HRCWL_DDRCM_SHIFT 30
  523. #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
  524. #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
  525. #define HRCWL_SPMF 0x0f000000
  526. #define HRCWL_SPMF_SHIFT 24
  527. #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
  528. #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
  529. #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
  530. #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
  531. #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
  532. #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
  533. #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
  534. #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
  535. #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
  536. #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
  537. #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
  538. #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
  539. #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
  540. #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
  541. #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
  542. #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
  543. #define HRCWL_VCO_BYPASS 0x00000000
  544. #define HRCWL_VCO_1X2 0x00000000
  545. #define HRCWL_VCO_1X4 0x00200000
  546. #define HRCWL_VCO_1X8 0x00400000
  547. #define HRCWL_COREPLL 0x007F0000
  548. #define HRCWL_COREPLL_SHIFT 16
  549. #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
  550. #define HRCWL_CORE_TO_CSB_1X1 0x00020000
  551. #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
  552. #define HRCWL_CORE_TO_CSB_2X1 0x00040000
  553. #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
  554. #define HRCWL_CORE_TO_CSB_3X1 0x00060000
  555. #if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
  556. #define HRCWL_CEVCOD 0x000000C0
  557. #define HRCWL_CEVCOD_SHIFT 6
  558. #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
  559. #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
  560. #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
  561. #define HRCWL_CEPDF 0x00000020
  562. #define HRCWL_CEPDF_SHIFT 5
  563. #define HRCWL_CE_PLL_DIV_1X1 0x00000000
  564. #define HRCWL_CE_PLL_DIV_2X1 0x00000020
  565. #define HRCWL_CEPMF 0x0000001F
  566. #define HRCWL_CEPMF_SHIFT 0
  567. #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
  568. #define HRCWL_CE_TO_PLL_1X2 0x00000002
  569. #define HRCWL_CE_TO_PLL_1X3 0x00000003
  570. #define HRCWL_CE_TO_PLL_1X4 0x00000004
  571. #define HRCWL_CE_TO_PLL_1X5 0x00000005
  572. #define HRCWL_CE_TO_PLL_1X6 0x00000006
  573. #define HRCWL_CE_TO_PLL_1X7 0x00000007
  574. #define HRCWL_CE_TO_PLL_1X8 0x00000008
  575. #define HRCWL_CE_TO_PLL_1X9 0x00000009
  576. #define HRCWL_CE_TO_PLL_1X10 0x0000000A
  577. #define HRCWL_CE_TO_PLL_1X11 0x0000000B
  578. #define HRCWL_CE_TO_PLL_1X12 0x0000000C
  579. #define HRCWL_CE_TO_PLL_1X13 0x0000000D
  580. #define HRCWL_CE_TO_PLL_1X14 0x0000000E
  581. #define HRCWL_CE_TO_PLL_1X15 0x0000000F
  582. #define HRCWL_CE_TO_PLL_1X16 0x00000010
  583. #define HRCWL_CE_TO_PLL_1X17 0x00000011
  584. #define HRCWL_CE_TO_PLL_1X18 0x00000012
  585. #define HRCWL_CE_TO_PLL_1X19 0x00000013
  586. #define HRCWL_CE_TO_PLL_1X20 0x00000014
  587. #define HRCWL_CE_TO_PLL_1X21 0x00000015
  588. #define HRCWL_CE_TO_PLL_1X22 0x00000016
  589. #define HRCWL_CE_TO_PLL_1X23 0x00000017
  590. #define HRCWL_CE_TO_PLL_1X24 0x00000018
  591. #define HRCWL_CE_TO_PLL_1X25 0x00000019
  592. #define HRCWL_CE_TO_PLL_1X26 0x0000001A
  593. #define HRCWL_CE_TO_PLL_1X27 0x0000001B
  594. #define HRCWL_CE_TO_PLL_1X28 0x0000001C
  595. #define HRCWL_CE_TO_PLL_1X29 0x0000001D
  596. #define HRCWL_CE_TO_PLL_1X30 0x0000001E
  597. #define HRCWL_CE_TO_PLL_1X31 0x0000001F
  598. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
  599. #define HRCWL_SVCOD 0x30000000
  600. #define HRCWL_SVCOD_SHIFT 28
  601. #define HRCWL_SVCOD_DIV_2 0x00000000
  602. #define HRCWL_SVCOD_DIV_4 0x10000000
  603. #define HRCWL_SVCOD_DIV_8 0x20000000
  604. #define HRCWL_SVCOD_DIV_1 0x30000000
  605. #elif defined(CONFIG_ARCH_MPC837X)
  606. #define HRCWL_SVCOD 0x30000000
  607. #define HRCWL_SVCOD_SHIFT 28
  608. #define HRCWL_SVCOD_DIV_4 0x00000000
  609. #define HRCWL_SVCOD_DIV_8 0x10000000
  610. #define HRCWL_SVCOD_DIV_2 0x20000000
  611. #define HRCWL_SVCOD_DIV_1 0x30000000
  612. #elif defined(CONFIG_ARCH_MPC8309)
  613. #define HRCWL_CEVCOD 0x000000C0
  614. #define HRCWL_CEVCOD_SHIFT 6
  615. /*
  616. * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
  617. * these are different than with 8360, 832x
  618. */
  619. #define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
  620. #define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
  621. #define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
  622. #define HRCWL_CEPDF 0x00000020
  623. #define HRCWL_CEPDF_SHIFT 5
  624. #define HRCWL_CE_PLL_DIV_1X1 0x00000000
  625. #define HRCWL_CE_PLL_DIV_2X1 0x00000020
  626. #define HRCWL_CEPMF 0x0000001F
  627. #define HRCWL_CEPMF_SHIFT 0
  628. #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
  629. #define HRCWL_CE_TO_PLL_1X2 0x00000002
  630. #define HRCWL_CE_TO_PLL_1X3 0x00000003
  631. #define HRCWL_CE_TO_PLL_1X4 0x00000004
  632. #define HRCWL_CE_TO_PLL_1X5 0x00000005
  633. #define HRCWL_CE_TO_PLL_1X6 0x00000006
  634. #define HRCWL_CE_TO_PLL_1X7 0x00000007
  635. #define HRCWL_CE_TO_PLL_1X8 0x00000008
  636. #define HRCWL_CE_TO_PLL_1X9 0x00000009
  637. #define HRCWL_CE_TO_PLL_1X10 0x0000000A
  638. #define HRCWL_CE_TO_PLL_1X11 0x0000000B
  639. #define HRCWL_CE_TO_PLL_1X12 0x0000000C
  640. #define HRCWL_CE_TO_PLL_1X13 0x0000000D
  641. #define HRCWL_CE_TO_PLL_1X14 0x0000000E
  642. #define HRCWL_CE_TO_PLL_1X15 0x0000000F
  643. #define HRCWL_CE_TO_PLL_1X16 0x00000010
  644. #define HRCWL_CE_TO_PLL_1X17 0x00000011
  645. #define HRCWL_CE_TO_PLL_1X18 0x00000012
  646. #define HRCWL_CE_TO_PLL_1X19 0x00000013
  647. #define HRCWL_CE_TO_PLL_1X20 0x00000014
  648. #define HRCWL_CE_TO_PLL_1X21 0x00000015
  649. #define HRCWL_CE_TO_PLL_1X22 0x00000016
  650. #define HRCWL_CE_TO_PLL_1X23 0x00000017
  651. #define HRCWL_CE_TO_PLL_1X24 0x00000018
  652. #define HRCWL_CE_TO_PLL_1X25 0x00000019
  653. #define HRCWL_CE_TO_PLL_1X26 0x0000001A
  654. #define HRCWL_CE_TO_PLL_1X27 0x0000001B
  655. #define HRCWL_CE_TO_PLL_1X28 0x0000001C
  656. #define HRCWL_CE_TO_PLL_1X29 0x0000001D
  657. #define HRCWL_CE_TO_PLL_1X30 0x0000001E
  658. #define HRCWL_CE_TO_PLL_1X31 0x0000001F
  659. #define HRCWL_SVCOD 0x30000000
  660. #define HRCWL_SVCOD_SHIFT 28
  661. #define HRCWL_SVCOD_DIV_2 0x00000000
  662. #define HRCWL_SVCOD_DIV_4 0x10000000
  663. #define HRCWL_SVCOD_DIV_8 0x20000000
  664. #define HRCWL_SVCOD_DIV_1 0x30000000
  665. #endif
  666. /*
  667. * HRCWH - Hardware Reset Configuration Word High
  668. */
  669. #define HRCWH_PCI_HOST 0x80000000
  670. #define HRCWH_PCI_HOST_SHIFT 31
  671. #define HRCWH_PCI_AGENT 0x00000000
  672. #if defined(CONFIG_ARCH_MPC834X)
  673. #define HRCWH_32_BIT_PCI 0x00000000
  674. #define HRCWH_64_BIT_PCI 0x40000000
  675. #endif
  676. #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
  677. #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
  678. #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
  679. #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
  680. #if defined(CONFIG_ARCH_MPC834X)
  681. #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
  682. #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
  683. #elif defined(CONFIG_ARCH_MPC8360)
  684. #define HRCWH_PCICKDRV_DISABLE 0x00000000
  685. #define HRCWH_PCICKDRV_ENABLE 0x10000000
  686. #endif
  687. #define HRCWH_CORE_DISABLE 0x08000000
  688. #define HRCWH_CORE_ENABLE 0x00000000
  689. #define HRCWH_FROM_0X00000100 0x00000000
  690. #define HRCWH_FROM_0XFFF00100 0x04000000
  691. #define HRCWH_BOOTSEQ_DISABLE 0x00000000
  692. #define HRCWH_BOOTSEQ_NORMAL 0x01000000
  693. #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
  694. #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
  695. #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
  696. #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
  697. #define HRCWH_ROM_LOC_PCI1 0x00100000
  698. #if defined(CONFIG_ARCH_MPC834X)
  699. #define HRCWH_ROM_LOC_PCI2 0x00200000
  700. #endif
  701. #if defined(CONFIG_ARCH_MPC837X)
  702. #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
  703. #endif
  704. #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
  705. #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
  706. #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
  707. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  708. defined(CONFIG_ARCH_MPC837X)
  709. #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
  710. #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
  711. #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
  712. #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
  713. #define HRCWH_RL_EXT_LEGACY 0x00000000
  714. #define HRCWH_RL_EXT_NAND 0x00040000
  715. #define HRCWH_TSEC1M_MASK 0x0000E000
  716. #define HRCWH_TSEC1M_IN_MII 0x00000000
  717. #define HRCWH_TSEC1M_IN_RMII 0x00002000
  718. #define HRCWH_TSEC1M_IN_RGMII 0x00006000
  719. #define HRCWH_TSEC1M_IN_RTBI 0x0000A000
  720. #define HRCWH_TSEC1M_IN_SGMII 0x0000C000
  721. #define HRCWH_TSEC2M_MASK 0x00001C00
  722. #define HRCWH_TSEC2M_IN_MII 0x00000000
  723. #define HRCWH_TSEC2M_IN_RMII 0x00000400
  724. #define HRCWH_TSEC2M_IN_RGMII 0x00000C00
  725. #define HRCWH_TSEC2M_IN_RTBI 0x00001400
  726. #define HRCWH_TSEC2M_IN_SGMII 0x00001800
  727. #endif
  728. #if defined(CONFIG_ARCH_MPC834X)
  729. #define HRCWH_TSEC1M_IN_RGMII 0x00000000
  730. #define HRCWH_TSEC1M_IN_RTBI 0x00004000
  731. #define HRCWH_TSEC1M_IN_GMII 0x00008000
  732. #define HRCWH_TSEC1M_IN_TBI 0x0000C000
  733. #define HRCWH_TSEC2M_IN_RGMII 0x00000000
  734. #define HRCWH_TSEC2M_IN_RTBI 0x00001000
  735. #define HRCWH_TSEC2M_IN_GMII 0x00002000
  736. #define HRCWH_TSEC2M_IN_TBI 0x00003000
  737. #endif
  738. #if defined(CONFIG_ARCH_MPC8360)
  739. #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
  740. #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
  741. #endif
  742. #define HRCWH_BIG_ENDIAN 0x00000000
  743. #define HRCWH_LITTLE_ENDIAN 0x00000008
  744. #define HRCWH_LALE_NORMAL 0x00000000
  745. #define HRCWH_LALE_EARLY 0x00000004
  746. #define HRCWH_LDP_SET 0x00000000
  747. #define HRCWH_LDP_CLEAR 0x00000002
  748. /*
  749. * RSR - Reset Status Register
  750. */
  751. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  752. defined(CONFIG_ARCH_MPC837X)
  753. #define RSR_RSTSRC 0xF0000000 /* Reset source */
  754. #define RSR_RSTSRC_SHIFT 28
  755. #else
  756. #define RSR_RSTSRC 0xE0000000 /* Reset source */
  757. #define RSR_RSTSRC_SHIFT 29
  758. #endif
  759. #define RSR_BSF 0x00010000 /* Boot seq. fail */
  760. #define RSR_BSF_SHIFT 16
  761. /* software soft reset */
  762. #define RSR_SWSR 0x00002000
  763. #define RSR_SWSR_SHIFT 13
  764. /* software hard reset */
  765. #define RSR_SWHR 0x00001000
  766. #define RSR_SWHR_SHIFT 12
  767. #define RSR_JHRS 0x00000200 /* jtag hreset */
  768. #define RSR_JHRS_SHIFT 9
  769. /* jtag sreset status */
  770. #define RSR_JSRS 0x00000100
  771. #define RSR_JSRS_SHIFT 8
  772. /* checkstop reset status */
  773. #define RSR_CSHR 0x00000010
  774. #define RSR_CSHR_SHIFT 4
  775. /* software watchdog reset status */
  776. #define RSR_SWRS 0x00000008
  777. #define RSR_SWRS_SHIFT 3
  778. /* bus monitop reset status */
  779. #define RSR_BMRS 0x00000004
  780. #define RSR_BMRS_SHIFT 2
  781. #define RSR_SRS 0x00000002 /* soft reset status */
  782. #define RSR_SRS_SHIFT 1
  783. #define RSR_HRS 0x00000001 /* hard reset status */
  784. #define RSR_HRS_SHIFT 0
  785. #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
  786. RSR_SWHR | RSR_JHRS | \
  787. RSR_JSRS | RSR_CSHR | \
  788. RSR_SWRS | RSR_BMRS | \
  789. RSR_SRS | RSR_HRS))
  790. /*
  791. * RMR - Reset Mode Register
  792. */
  793. /* checkstop reset enable */
  794. #define RMR_CSRE 0x00000001
  795. #define RMR_CSRE_SHIFT 0
  796. #define RMR_RES ~(RMR_CSRE)
  797. /*
  798. * RCR - Reset Control Register
  799. */
  800. /* software hard reset */
  801. #define RCR_SWHR 0x00000002
  802. /* software soft reset */
  803. #define RCR_SWSR 0x00000001
  804. #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
  805. /*
  806. * RCER - Reset Control Enable Register
  807. */
  808. /* software hard reset */
  809. #define RCER_CRE 0x00000001
  810. #define RCER_RES ~(RCER_CRE)
  811. /*
  812. * SPMR - System PLL Mode Register
  813. */
  814. #define SPMR_LBIUCM 0x80000000
  815. #define SPMR_LBIUCM_SHIFT 31
  816. #define SPMR_DDRCM 0x40000000
  817. #define SPMR_DDRCM_SHIFT 30
  818. #define SPMR_SPMF 0x0F000000
  819. #define SPMR_SPMF_SHIFT 24
  820. #define SPMR_CKID 0x00800000
  821. #define SPMR_CKID_SHIFT 23
  822. #define SPMR_COREPLL 0x007F0000
  823. #define SPMR_COREPLL_SHIFT 16
  824. #define SPMR_CEVCOD 0x000000C0
  825. #define SPMR_CEVCOD_SHIFT 6
  826. #define SPMR_CEPDF 0x00000020
  827. #define SPMR_CEPDF_SHIFT 5
  828. #define SPMR_CEPMF 0x0000001F
  829. #define SPMR_CEPMF_SHIFT 0
  830. /*
  831. * OCCR - Output Clock Control Register
  832. */
  833. #define OCCR_PCICOE0 0x80000000
  834. #define OCCR_PCICOE1 0x40000000
  835. #define OCCR_PCICOE2 0x20000000
  836. #define OCCR_PCICOE3 0x10000000
  837. #define OCCR_PCICOE4 0x08000000
  838. #define OCCR_PCICOE5 0x04000000
  839. #define OCCR_PCICOE6 0x02000000
  840. #define OCCR_PCICOE7 0x01000000
  841. #define OCCR_PCICD0 0x00800000
  842. #define OCCR_PCICD1 0x00400000
  843. #define OCCR_PCICD2 0x00200000
  844. #define OCCR_PCICD3 0x00100000
  845. #define OCCR_PCICD4 0x00080000
  846. #define OCCR_PCICD5 0x00040000
  847. #define OCCR_PCICD6 0x00020000
  848. #define OCCR_PCICD7 0x00010000
  849. #define OCCR_PCI1CR 0x00000002
  850. #define OCCR_PCI2CR 0x00000001
  851. #define OCCR_PCICR OCCR_PCI1CR
  852. /*
  853. * SCCR - System Clock Control Register
  854. */
  855. #define SCCR_ENCCM 0x03000000
  856. #define SCCR_ENCCM_SHIFT 24
  857. #define SCCR_ENCCM_0 0x00000000
  858. #define SCCR_ENCCM_1 0x01000000
  859. #define SCCR_ENCCM_2 0x02000000
  860. #define SCCR_ENCCM_3 0x03000000
  861. #define SCCR_PCICM 0x00010000
  862. #define SCCR_PCICM_SHIFT 16
  863. #if defined(CONFIG_ARCH_MPC834X)
  864. /* SCCR bits - MPC834X specific */
  865. #define SCCR_TSEC1CM 0xc0000000
  866. #define SCCR_TSEC1CM_SHIFT 30
  867. #define SCCR_TSEC1CM_0 0x00000000
  868. #define SCCR_TSEC1CM_1 0x40000000
  869. #define SCCR_TSEC1CM_2 0x80000000
  870. #define SCCR_TSEC1CM_3 0xC0000000
  871. #define SCCR_TSEC2CM 0x30000000
  872. #define SCCR_TSEC2CM_SHIFT 28
  873. #define SCCR_TSEC2CM_0 0x00000000
  874. #define SCCR_TSEC2CM_1 0x10000000
  875. #define SCCR_TSEC2CM_2 0x20000000
  876. #define SCCR_TSEC2CM_3 0x30000000
  877. /* The MPH must have the same clock ratio as DR, unless its clock disabled */
  878. #define SCCR_USBMPHCM 0x00c00000
  879. #define SCCR_USBMPHCM_SHIFT 22
  880. #define SCCR_USBDRCM 0x00300000
  881. #define SCCR_USBDRCM_SHIFT 20
  882. #define SCCR_USBCM 0x00f00000
  883. #define SCCR_USBCM_SHIFT 20
  884. #define SCCR_USBCM_0 0x00000000
  885. #define SCCR_USBCM_1 0x00500000
  886. #define SCCR_USBCM_2 0x00A00000
  887. #define SCCR_USBCM_3 0x00F00000
  888. #elif defined(CONFIG_ARCH_MPC8313)
  889. /* TSEC1 bits are for TSEC2 as well */
  890. #define SCCR_TSEC1CM 0xc0000000
  891. #define SCCR_TSEC1CM_SHIFT 30
  892. #define SCCR_TSEC1CM_0 0x00000000
  893. #define SCCR_TSEC1CM_1 0x40000000
  894. #define SCCR_TSEC1CM_2 0x80000000
  895. #define SCCR_TSEC1CM_3 0xC0000000
  896. #define SCCR_TSEC1ON 0x20000000
  897. #define SCCR_TSEC1ON_SHIFT 29
  898. #define SCCR_TSEC2ON 0x10000000
  899. #define SCCR_TSEC2ON_SHIFT 28
  900. #define SCCR_USBDRCM 0x00300000
  901. #define SCCR_USBDRCM_SHIFT 20
  902. #define SCCR_USBDRCM_0 0x00000000
  903. #define SCCR_USBDRCM_1 0x00100000
  904. #define SCCR_USBDRCM_2 0x00200000
  905. #define SCCR_USBDRCM_3 0x00300000
  906. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
  907. /* SCCR bits - MPC8315/MPC8308 specific */
  908. #define SCCR_TSEC1CM 0xc0000000
  909. #define SCCR_TSEC1CM_SHIFT 30
  910. #define SCCR_TSEC1CM_0 0x00000000
  911. #define SCCR_TSEC1CM_1 0x40000000
  912. #define SCCR_TSEC1CM_2 0x80000000
  913. #define SCCR_TSEC1CM_3 0xC0000000
  914. #define SCCR_TSEC2CM 0x30000000
  915. #define SCCR_TSEC2CM_SHIFT 28
  916. #define SCCR_TSEC2CM_0 0x00000000
  917. #define SCCR_TSEC2CM_1 0x10000000
  918. #define SCCR_TSEC2CM_2 0x20000000
  919. #define SCCR_TSEC2CM_3 0x30000000
  920. #define SCCR_SDHCCM 0x0c000000
  921. #define SCCR_SDHCCM_SHIFT 26
  922. #define SCCR_SDHCCM_0 0x00000000
  923. #define SCCR_SDHCCM_1 0x04000000
  924. #define SCCR_SDHCCM_2 0x08000000
  925. #define SCCR_SDHCCM_3 0x0c000000
  926. #define SCCR_USBDRCM 0x00c00000
  927. #define SCCR_USBDRCM_SHIFT 22
  928. #define SCCR_USBDRCM_0 0x00000000
  929. #define SCCR_USBDRCM_1 0x00400000
  930. #define SCCR_USBDRCM_2 0x00800000
  931. #define SCCR_USBDRCM_3 0x00c00000
  932. #define SCCR_SATA1CM 0x00003000
  933. #define SCCR_SATA1CM_SHIFT 12
  934. #define SCCR_SATACM 0x00003c00
  935. #define SCCR_SATACM_SHIFT 10
  936. #define SCCR_SATACM_0 0x00000000
  937. #define SCCR_SATACM_1 0x00001400
  938. #define SCCR_SATACM_2 0x00002800
  939. #define SCCR_SATACM_3 0x00003c00
  940. #define SCCR_TDMCM 0x00000030
  941. #define SCCR_TDMCM_SHIFT 4
  942. #define SCCR_TDMCM_0 0x00000000
  943. #define SCCR_TDMCM_1 0x00000010
  944. #define SCCR_TDMCM_2 0x00000020
  945. #define SCCR_TDMCM_3 0x00000030
  946. #elif defined(CONFIG_ARCH_MPC837X)
  947. /* SCCR bits - MPC837X specific */
  948. #define SCCR_TSEC1CM 0xc0000000
  949. #define SCCR_TSEC1CM_SHIFT 30
  950. #define SCCR_TSEC1CM_0 0x00000000
  951. #define SCCR_TSEC1CM_1 0x40000000
  952. #define SCCR_TSEC1CM_2 0x80000000
  953. #define SCCR_TSEC1CM_3 0xC0000000
  954. #define SCCR_TSEC2CM 0x30000000
  955. #define SCCR_TSEC2CM_SHIFT 28
  956. #define SCCR_TSEC2CM_0 0x00000000
  957. #define SCCR_TSEC2CM_1 0x10000000
  958. #define SCCR_TSEC2CM_2 0x20000000
  959. #define SCCR_TSEC2CM_3 0x30000000
  960. #define SCCR_SDHCCM 0x0c000000
  961. #define SCCR_SDHCCM_SHIFT 26
  962. #define SCCR_SDHCCM_0 0x00000000
  963. #define SCCR_SDHCCM_1 0x04000000
  964. #define SCCR_SDHCCM_2 0x08000000
  965. #define SCCR_SDHCCM_3 0x0c000000
  966. #define SCCR_USBDRCM 0x00c00000
  967. #define SCCR_USBDRCM_SHIFT 22
  968. #define SCCR_USBDRCM_0 0x00000000
  969. #define SCCR_USBDRCM_1 0x00400000
  970. #define SCCR_USBDRCM_2 0x00800000
  971. #define SCCR_USBDRCM_3 0x00c00000
  972. /* All of the four SATA controllers must have the same clock ratio */
  973. #define SCCR_SATA1CM 0x000000c0
  974. #define SCCR_SATA1CM_SHIFT 6
  975. #define SCCR_SATACM 0x000000ff
  976. #define SCCR_SATACM_SHIFT 0
  977. #define SCCR_SATACM_0 0x00000000
  978. #define SCCR_SATACM_1 0x00000055
  979. #define SCCR_SATACM_2 0x000000aa
  980. #define SCCR_SATACM_3 0x000000ff
  981. #elif defined(CONFIG_ARCH_MPC8309)
  982. /* SCCR bits - MPC8309 specific */
  983. #define SCCR_SDHCCM 0x0c000000
  984. #define SCCR_SDHCCM_SHIFT 26
  985. #define SCCR_SDHCCM_0 0x00000000
  986. #define SCCR_SDHCCM_1 0x04000000
  987. #define SCCR_SDHCCM_2 0x08000000
  988. #define SCCR_SDHCCM_3 0x0c000000
  989. #define SCCR_USBDRCM 0x00c00000
  990. #define SCCR_USBDRCM_SHIFT 22
  991. #define SCCR_USBDRCM_0 0x00000000
  992. #define SCCR_USBDRCM_1 0x00400000
  993. #define SCCR_USBDRCM_2 0x00800000
  994. #define SCCR_USBDRCM_3 0x00c00000
  995. #endif
  996. #define SCCR_PCIEXP1CM 0x00300000
  997. #define SCCR_PCIEXP1CM_SHIFT 20
  998. #define SCCR_PCIEXP1CM_0 0x00000000
  999. #define SCCR_PCIEXP1CM_1 0x00100000
  1000. #define SCCR_PCIEXP1CM_2 0x00200000
  1001. #define SCCR_PCIEXP1CM_3 0x00300000
  1002. #define SCCR_PCIEXP2CM 0x000c0000
  1003. #define SCCR_PCIEXP2CM_SHIFT 18
  1004. #define SCCR_PCIEXP2CM_0 0x00000000
  1005. #define SCCR_PCIEXP2CM_1 0x00040000
  1006. #define SCCR_PCIEXP2CM_2 0x00080000
  1007. #define SCCR_PCIEXP2CM_3 0x000c0000
  1008. /*
  1009. * CSn_BDNS - Chip Select memory Bounds Register
  1010. */
  1011. #define CSBNDS_SA 0x00FF0000
  1012. #define CSBNDS_SA_SHIFT 8
  1013. #define CSBNDS_EA 0x000000FF
  1014. #define CSBNDS_EA_SHIFT 24
  1015. #ifndef CONFIG_MPC83XX_SDRAM
  1016. /*
  1017. * CSn_CONFIG - Chip Select Configuration Register
  1018. */
  1019. #define CSCONFIG_EN 0x80000000
  1020. #define CSCONFIG_AP 0x00800000
  1021. #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
  1022. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  1023. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  1024. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  1025. #define CSCONFIG_ODT_RD_ALL 0x00400000
  1026. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  1027. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  1028. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  1029. #define CSCONFIG_ODT_WR_ALL 0x00040000
  1030. #elif defined(CONFIG_ARCH_MPC832X)
  1031. #define CSCONFIG_ODT_RD_CFG 0x00400000
  1032. #define CSCONFIG_ODT_WR_CFG 0x00040000
  1033. #elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
  1034. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  1035. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  1036. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  1037. #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
  1038. #define CSCONFIG_ODT_RD_ALL 0x00400000
  1039. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  1040. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  1041. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  1042. #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
  1043. #define CSCONFIG_ODT_WR_ALL 0x00040000
  1044. #endif
  1045. #define CSCONFIG_BANK_BIT_3 0x00004000
  1046. #define CSCONFIG_ROW_BIT 0x00000700
  1047. #define CSCONFIG_ROW_BIT_12 0x00000000
  1048. #define CSCONFIG_ROW_BIT_13 0x00000100
  1049. #define CSCONFIG_ROW_BIT_14 0x00000200
  1050. #define CSCONFIG_COL_BIT 0x00000007
  1051. #define CSCONFIG_COL_BIT_8 0x00000000
  1052. #define CSCONFIG_COL_BIT_9 0x00000001
  1053. #define CSCONFIG_COL_BIT_10 0x00000002
  1054. #define CSCONFIG_COL_BIT_11 0x00000003
  1055. /*
  1056. * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
  1057. */
  1058. #define TIMING_CFG0_RWT 0xC0000000
  1059. #define TIMING_CFG0_RWT_SHIFT 30
  1060. #define TIMING_CFG0_WRT 0x30000000
  1061. #define TIMING_CFG0_WRT_SHIFT 28
  1062. #define TIMING_CFG0_RRT 0x0C000000
  1063. #define TIMING_CFG0_RRT_SHIFT 26
  1064. #define TIMING_CFG0_WWT 0x03000000
  1065. #define TIMING_CFG0_WWT_SHIFT 24
  1066. #define TIMING_CFG0_ACT_PD_EXIT 0x00700000
  1067. #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
  1068. #define TIMING_CFG0_PRE_PD_EXIT 0x00070000
  1069. #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
  1070. #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
  1071. #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
  1072. #define TIMING_CFG0_MRS_CYC 0x0000000F
  1073. #define TIMING_CFG0_MRS_CYC_SHIFT 0
  1074. /*
  1075. * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
  1076. */
  1077. #define TIMING_CFG1_PRETOACT 0x70000000
  1078. #define TIMING_CFG1_PRETOACT_SHIFT 28
  1079. #define TIMING_CFG1_ACTTOPRE 0x0F000000
  1080. #define TIMING_CFG1_ACTTOPRE_SHIFT 24
  1081. #define TIMING_CFG1_ACTTORW 0x00700000
  1082. #define TIMING_CFG1_ACTTORW_SHIFT 20
  1083. #define TIMING_CFG1_CASLAT 0x00070000
  1084. #define TIMING_CFG1_CASLAT_SHIFT 16
  1085. #define TIMING_CFG1_REFREC 0x0000F000
  1086. #define TIMING_CFG1_REFREC_SHIFT 12
  1087. #define TIMING_CFG1_WRREC 0x00000700
  1088. #define TIMING_CFG1_WRREC_SHIFT 8
  1089. #define TIMING_CFG1_ACTTOACT 0x00000070
  1090. #define TIMING_CFG1_ACTTOACT_SHIFT 4
  1091. #define TIMING_CFG1_WRTORD 0x00000007
  1092. #define TIMING_CFG1_WRTORD_SHIFT 0
  1093. #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
  1094. #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
  1095. #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
  1096. #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
  1097. #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
  1098. #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
  1099. #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
  1100. /*
  1101. * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  1102. */
  1103. #define TIMING_CFG2_CPO 0x0F800000
  1104. #define TIMING_CFG2_CPO_SHIFT 23
  1105. #define TIMING_CFG2_ACSM 0x00080000
  1106. #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
  1107. #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
  1108. /* default (= CASLAT + 1) */
  1109. #define TIMING_CFG2_CPO_DEF 0x00000000
  1110. #define TIMING_CFG2_ADD_LAT 0x70000000
  1111. #define TIMING_CFG2_ADD_LAT_SHIFT 28
  1112. #define TIMING_CFG2_WR_LAT_DELAY 0x00380000
  1113. #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
  1114. #define TIMING_CFG2_RD_TO_PRE 0x0000E000
  1115. #define TIMING_CFG2_RD_TO_PRE_SHIFT 13
  1116. #define TIMING_CFG2_CKE_PLS 0x000001C0
  1117. #define TIMING_CFG2_CKE_PLS_SHIFT 6
  1118. #define TIMING_CFG2_FOUR_ACT 0x0000003F
  1119. #define TIMING_CFG2_FOUR_ACT_SHIFT 0
  1120. /*
  1121. * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
  1122. */
  1123. #define TIMING_CFG3_EXT_REFREC 0x00070000
  1124. #define TIMING_CFG3_EXT_REFREC_SHIFT 16
  1125. /*
  1126. * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  1127. */
  1128. #define SDRAM_CFG_MEM_EN 0x80000000
  1129. #define SDRAM_CFG_SREN 0x40000000
  1130. #define SDRAM_CFG_ECC_EN 0x20000000
  1131. #define SDRAM_CFG_RD_EN 0x10000000
  1132. #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
  1133. #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
  1134. #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
  1135. #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
  1136. #define SDRAM_CFG_DYN_PWR 0x00200000
  1137. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  1138. #define SDRAM_CFG_DBW_MASK 0x00180000
  1139. #define SDRAM_CFG_DBW_16 0x00100000
  1140. #define SDRAM_CFG_DBW_32 0x00080000
  1141. #else
  1142. #define SDRAM_CFG_32_BE 0x00080000
  1143. #endif
  1144. #if !defined(CONFIG_ARCH_MPC8308)
  1145. #define SDRAM_CFG_8_BE 0x00040000
  1146. #endif
  1147. #define SDRAM_CFG_NCAP 0x00020000
  1148. #define SDRAM_CFG_2T_EN 0x00008000
  1149. #define SDRAM_CFG_HSE 0x00000008
  1150. #define SDRAM_CFG_BI 0x00000001
  1151. /*
  1152. * DDR_SDRAM_MODE - DDR SDRAM Mode Register
  1153. */
  1154. #define SDRAM_MODE_ESD 0xFFFF0000
  1155. #define SDRAM_MODE_ESD_SHIFT 16
  1156. #define SDRAM_MODE_SD 0x0000FFFF
  1157. #define SDRAM_MODE_SD_SHIFT 0
  1158. /* select extended mode reg */
  1159. #define DDR_MODE_EXT_MODEREG 0x4000
  1160. /* operating mode, mask */
  1161. #define DDR_MODE_EXT_OPMODE 0x3FF8
  1162. #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
  1163. /* QFC / compatibility, mask */
  1164. #define DDR_MODE_QFC 0x0004
  1165. /* compatible to older SDRAMs */
  1166. #define DDR_MODE_QFC_COMP 0x0000
  1167. /* weak drivers */
  1168. #define DDR_MODE_WEAK 0x0002
  1169. /* disable DLL */
  1170. #define DDR_MODE_DLL_DIS 0x0001
  1171. /* CAS latency, mask */
  1172. #define DDR_MODE_CASLAT 0x0070
  1173. #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
  1174. #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
  1175. #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
  1176. #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
  1177. /* sequential burst */
  1178. #define DDR_MODE_BTYPE_SEQ 0x0000
  1179. /* interleaved burst */
  1180. #define DDR_MODE_BTYPE_ILVD 0x0008
  1181. #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
  1182. #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
  1183. /* exact value for 7.8125us */
  1184. #define DDR_REFINT_166MHZ_7US 1302
  1185. /* use 256 cycles as a starting point */
  1186. #define DDR_BSTOPRE 256
  1187. /* select mode register */
  1188. #define DDR_MODE_MODEREG 0x0000
  1189. /*
  1190. * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
  1191. */
  1192. #define SDRAM_INTERVAL_REFINT 0x3FFF0000
  1193. #define SDRAM_INTERVAL_REFINT_SHIFT 16
  1194. #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
  1195. /*
  1196. * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
  1197. */
  1198. #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
  1199. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
  1200. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
  1201. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
  1202. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
  1203. /*
  1204. * ECC_ERR_INJECT - Memory data path error injection mask ECC
  1205. */
  1206. /* ECC Mirror Byte */
  1207. #define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
  1208. /* Error Injection Enable */
  1209. #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
  1210. /* ECC Erroe Injection Enable */
  1211. #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
  1212. #define ECC_ERR_INJECT_EEIM_SHIFT 0
  1213. /*
  1214. * CAPTURE_ECC - Memory data path read capture ECC
  1215. */
  1216. #define CAPTURE_ECC_ECE (0xff000000 >> 24)
  1217. #define CAPTURE_ECC_ECE_SHIFT 0
  1218. /*
  1219. * ERR_DETECT - Memory error detect
  1220. */
  1221. /* Multiple Memory Errors */
  1222. #define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
  1223. /* Multiple-Bit Error */
  1224. #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
  1225. /* Single-Bit ECC Error Pickup */
  1226. #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
  1227. /* Memory Select Error */
  1228. #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
  1229. /*
  1230. * ERR_DISABLE - Memory error disable
  1231. */
  1232. /* Multiple-Bit ECC Error Disable */
  1233. #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
  1234. /* Sinle-Bit ECC Error disable */
  1235. #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
  1236. /* Memory Select Error Disable */
  1237. #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
  1238. #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
  1239. ECC_ERROR_DISABLE_SBED | \
  1240. ECC_ERROR_DISABLE_MBED))
  1241. /*
  1242. * ERR_INT_EN - Memory error interrupt enable
  1243. */
  1244. /* Multiple-Bit ECC Error Interrupt Enable */
  1245. #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
  1246. /* Single-Bit ECC Error Interrupt Enable */
  1247. #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
  1248. /* Memory Select Error Interrupt Enable */
  1249. #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
  1250. #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
  1251. ECC_ERR_INT_EN_SBEE | \
  1252. ECC_ERR_INT_EN_MSEE))
  1253. /*
  1254. * CAPTURE_ATTRIBUTES - Memory error attributes capture
  1255. */
  1256. /* Data Beat Num */
  1257. #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
  1258. #define ECC_CAPT_ATTR_BNUM_SHIFT 28
  1259. /* Transaction Size */
  1260. #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
  1261. #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
  1262. #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
  1263. #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
  1264. #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
  1265. #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
  1266. /* Transaction Source */
  1267. #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
  1268. #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
  1269. #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
  1270. #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
  1271. #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
  1272. #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
  1273. #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
  1274. #define ECC_CAPT_ATTR_TSRC_I2C 0x9
  1275. #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
  1276. #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
  1277. #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
  1278. #define ECC_CAPT_ATTR_TSRC_DMA 0xF
  1279. #define ECC_CAPT_ATTR_TSRC_SHIFT 16
  1280. /* Transaction Type */
  1281. #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
  1282. #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
  1283. #define ECC_CAPT_ATTR_TTYP_READ 0x2
  1284. #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
  1285. #define ECC_CAPT_ATTR_TTYP_SHIFT 12
  1286. #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
  1287. /*
  1288. * ERR_SBE - Single bit ECC memory error management
  1289. */
  1290. /* Single-Bit Error Threshold 0..255 */
  1291. #define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
  1292. #define ECC_ERROR_MAN_SBET_SHIFT 16
  1293. /* Single Bit Error Counter 0..255 */
  1294. #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
  1295. #define ECC_ERROR_MAN_SBEC_SHIFT 0
  1296. #endif /* !CONFIG_MPC83XX_SDRAM */
  1297. /*
  1298. * CONFIG_ADDRESS - PCI Config Address Register
  1299. */
  1300. #define PCI_CONFIG_ADDRESS_EN 0x80000000
  1301. #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
  1302. #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
  1303. #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
  1304. #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
  1305. #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
  1306. #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
  1307. #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
  1308. #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
  1309. /*
  1310. * POTAR - PCI Outbound Translation Address Register
  1311. */
  1312. #define POTAR_TA_MASK 0x000fffff
  1313. /*
  1314. * POBAR - PCI Outbound Base Address Register
  1315. */
  1316. #define POBAR_BA_MASK 0x000fffff
  1317. /*
  1318. * POCMR - PCI Outbound Comparision Mask Register
  1319. */
  1320. #define POCMR_EN 0x80000000
  1321. /* 0-memory space 1-I/O space */
  1322. #define POCMR_IO 0x40000000
  1323. #define POCMR_SE 0x20000000 /* streaming enable */
  1324. #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
  1325. #define POCMR_CM_MASK 0x000fffff
  1326. #define POCMR_CM_4G 0x00000000
  1327. #define POCMR_CM_2G 0x00080000
  1328. #define POCMR_CM_1G 0x000C0000
  1329. #define POCMR_CM_512M 0x000E0000
  1330. #define POCMR_CM_256M 0x000F0000
  1331. #define POCMR_CM_128M 0x000F8000
  1332. #define POCMR_CM_64M 0x000FC000
  1333. #define POCMR_CM_32M 0x000FE000
  1334. #define POCMR_CM_16M 0x000FF000
  1335. #define POCMR_CM_8M 0x000FF800
  1336. #define POCMR_CM_4M 0x000FFC00
  1337. #define POCMR_CM_2M 0x000FFE00
  1338. #define POCMR_CM_1M 0x000FFF00
  1339. #define POCMR_CM_512K 0x000FFF80
  1340. #define POCMR_CM_256K 0x000FFFC0
  1341. #define POCMR_CM_128K 0x000FFFE0
  1342. #define POCMR_CM_64K 0x000FFFF0
  1343. #define POCMR_CM_32K 0x000FFFF8
  1344. #define POCMR_CM_16K 0x000FFFFC
  1345. #define POCMR_CM_8K 0x000FFFFE
  1346. #define POCMR_CM_4K 0x000FFFFF
  1347. /*
  1348. * PITAR - PCI Inbound Translation Address Register
  1349. */
  1350. #define PITAR_TA_MASK 0x000fffff
  1351. /*
  1352. * PIBAR - PCI Inbound Base/Extended Address Register
  1353. */
  1354. #define PIBAR_MASK 0xffffffff
  1355. #define PIEBAR_EBA_MASK 0x000fffff
  1356. /*
  1357. * PIWAR - PCI Inbound Windows Attributes Register
  1358. */
  1359. #define PIWAR_EN 0x80000000
  1360. #define PIWAR_PF 0x20000000
  1361. #define PIWAR_RTT_MASK 0x000f0000
  1362. #define PIWAR_RTT_NO_SNOOP 0x00040000
  1363. #define PIWAR_RTT_SNOOP 0x00050000
  1364. #define PIWAR_WTT_MASK 0x0000f000
  1365. #define PIWAR_WTT_NO_SNOOP 0x00004000
  1366. #define PIWAR_WTT_SNOOP 0x00005000
  1367. #define PIWAR_IWS_MASK 0x0000003F
  1368. #define PIWAR_IWS_4K 0x0000000B
  1369. #define PIWAR_IWS_8K 0x0000000C
  1370. #define PIWAR_IWS_16K 0x0000000D
  1371. #define PIWAR_IWS_32K 0x0000000E
  1372. #define PIWAR_IWS_64K 0x0000000F
  1373. #define PIWAR_IWS_128K 0x00000010
  1374. #define PIWAR_IWS_256K 0x00000011
  1375. #define PIWAR_IWS_512K 0x00000012
  1376. #define PIWAR_IWS_1M 0x00000013
  1377. #define PIWAR_IWS_2M 0x00000014
  1378. #define PIWAR_IWS_4M 0x00000015
  1379. #define PIWAR_IWS_8M 0x00000016
  1380. #define PIWAR_IWS_16M 0x00000017
  1381. #define PIWAR_IWS_32M 0x00000018
  1382. #define PIWAR_IWS_64M 0x00000019
  1383. #define PIWAR_IWS_128M 0x0000001A
  1384. #define PIWAR_IWS_256M 0x0000001B
  1385. #define PIWAR_IWS_512M 0x0000001C
  1386. #define PIWAR_IWS_1G 0x0000001D
  1387. #define PIWAR_IWS_2G 0x0000001E
  1388. /*
  1389. * PMCCR1 - PCI Configuration Register 1
  1390. */
  1391. #define PMCCR1_POWER_OFF 0x00000020
  1392. #ifndef CONFIG_RAM
  1393. /*
  1394. * DDRCDR - DDR Control Driver Register
  1395. */
  1396. #define DDRCDR_DHC_EN 0x80000000
  1397. #define DDRCDR_EN 0x40000000
  1398. #define DDRCDR_PZ 0x3C000000
  1399. #define DDRCDR_PZ_MAXZ 0x00000000
  1400. #define DDRCDR_PZ_HIZ 0x20000000
  1401. #define DDRCDR_PZ_NOMZ 0x30000000
  1402. #define DDRCDR_PZ_LOZ 0x38000000
  1403. #define DDRCDR_PZ_MINZ 0x3C000000
  1404. #define DDRCDR_NZ 0x3C000000
  1405. #define DDRCDR_NZ_MAXZ 0x00000000
  1406. #define DDRCDR_NZ_HIZ 0x02000000
  1407. #define DDRCDR_NZ_NOMZ 0x03000000
  1408. #define DDRCDR_NZ_LOZ 0x03800000
  1409. #define DDRCDR_NZ_MINZ 0x03C00000
  1410. #define DDRCDR_ODT 0x00080000
  1411. #define DDRCDR_DDR_CFG 0x00040000
  1412. #define DDRCDR_M_ODR 0x00000002
  1413. #define DDRCDR_Q_DRN 0x00000001
  1414. #endif /* !CONFIG_RAM */
  1415. /*
  1416. * PCIE Bridge Register
  1417. */
  1418. #define PEX_CSB_CTRL_OBPIOE 0x00000001
  1419. #define PEX_CSB_CTRL_IBPIOE 0x00000002
  1420. #define PEX_CSB_CTRL_WDMAE 0x00000004
  1421. #define PEX_CSB_CTRL_RDMAE 0x00000008
  1422. #define PEX_CSB_OBCTRL_PIOE 0x00000001
  1423. #define PEX_CSB_OBCTRL_MEMWE 0x00000002
  1424. #define PEX_CSB_OBCTRL_IOWE 0x00000004
  1425. #define PEX_CSB_OBCTRL_CFGWE 0x00000008
  1426. #define PEX_CSB_IBCTRL_PIOE 0x00000001
  1427. #define PEX_OWAR_EN 0x00000001
  1428. #define PEX_OWAR_TYPE_CFG 0x00000000
  1429. #define PEX_OWAR_TYPE_IO 0x00000002
  1430. #define PEX_OWAR_TYPE_MEM 0x00000004
  1431. #define PEX_OWAR_RLXO 0x00000008
  1432. #define PEX_OWAR_NANP 0x00000010
  1433. #define PEX_OWAR_SIZE 0xFFFFF000
  1434. #define PEX_IWAR_EN 0x00000001
  1435. #define PEX_IWAR_TYPE_INT 0x00000000
  1436. #define PEX_IWAR_TYPE_PF 0x00000004
  1437. #define PEX_IWAR_TYPE_NO_PF 0x00000006
  1438. #define PEX_IWAR_NSOV 0x00000008
  1439. #define PEX_IWAR_NSNP 0x00000010
  1440. #define PEX_IWAR_SIZE 0xFFFFF000
  1441. #define PEX_IWAR_SIZE_1M 0x000FF000
  1442. #define PEX_IWAR_SIZE_2M 0x001FF000
  1443. #define PEX_IWAR_SIZE_4M 0x003FF000
  1444. #define PEX_IWAR_SIZE_8M 0x007FF000
  1445. #define PEX_IWAR_SIZE_16M 0x00FFF000
  1446. #define PEX_IWAR_SIZE_32M 0x01FFF000
  1447. #define PEX_IWAR_SIZE_64M 0x03FFF000
  1448. #define PEX_IWAR_SIZE_128M 0x07FFF000
  1449. #define PEX_IWAR_SIZE_256M 0x0FFFF000
  1450. #define PEX_GCLK_RATIO 0x440
  1451. #ifndef __ASSEMBLY__
  1452. struct pci_region;
  1453. void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
  1454. void mpc83xx_pcislave_unlock(int bus);
  1455. void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
  1456. #endif
  1457. #endif /* __MPC83XX_H__ */