mmc.h 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/list.h>
  11. #include <linux/sizes.h>
  12. #include <linux/compiler.h>
  13. #include <part.h>
  14. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  15. #define MMC_SUPPORTS_TUNING
  16. #endif
  17. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  18. #define MMC_SUPPORTS_TUNING
  19. #endif
  20. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  21. #define SD_VERSION_SD (1U << 31)
  22. #define MMC_VERSION_MMC (1U << 30)
  23. #define MAKE_SDMMC_VERSION(a, b, c) \
  24. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  25. #define MAKE_SD_VERSION(a, b, c) \
  26. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  27. #define MAKE_MMC_VERSION(a, b, c) \
  28. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  29. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  30. (((u32)(x) >> 16) & 0xff)
  31. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  32. (((u32)(x) >> 8) & 0xff)
  33. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  34. ((u32)(x) & 0xff)
  35. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  36. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  37. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  38. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  39. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  40. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  41. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  42. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  43. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  44. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  45. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  46. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  47. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  48. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  49. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  50. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  51. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  52. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  53. #define MMC_CAP(mode) (1 << mode)
  54. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  55. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  56. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  57. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  58. #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
  59. #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
  60. #define MMC_CAP_NONREMOVABLE BIT(14)
  61. #define MMC_CAP_NEEDS_POLL BIT(15)
  62. #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
  63. #define MMC_MODE_8BIT BIT(30)
  64. #define MMC_MODE_4BIT BIT(29)
  65. #define MMC_MODE_1BIT BIT(28)
  66. #define MMC_MODE_SPI BIT(27)
  67. #define SD_DATA_4BIT 0x00040000
  68. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  69. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  70. #define MMC_DATA_READ 1
  71. #define MMC_DATA_WRITE 2
  72. #define MMC_CMD_GO_IDLE_STATE 0
  73. #define MMC_CMD_SEND_OP_COND 1
  74. #define MMC_CMD_ALL_SEND_CID 2
  75. #define MMC_CMD_SET_RELATIVE_ADDR 3
  76. #define MMC_CMD_SET_DSR 4
  77. #define MMC_CMD_SWITCH 6
  78. #define MMC_CMD_SELECT_CARD 7
  79. #define MMC_CMD_SEND_EXT_CSD 8
  80. #define MMC_CMD_SEND_CSD 9
  81. #define MMC_CMD_SEND_CID 10
  82. #define MMC_CMD_STOP_TRANSMISSION 12
  83. #define MMC_CMD_SEND_STATUS 13
  84. #define MMC_CMD_SET_BLOCKLEN 16
  85. #define MMC_CMD_READ_SINGLE_BLOCK 17
  86. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  87. #define MMC_CMD_SEND_TUNING_BLOCK 19
  88. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  89. #define MMC_CMD_SET_BLOCK_COUNT 23
  90. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  91. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  92. #define MMC_CMD_ERASE_GROUP_START 35
  93. #define MMC_CMD_ERASE_GROUP_END 36
  94. #define MMC_CMD_ERASE 38
  95. #define MMC_CMD_APP_CMD 55
  96. #define MMC_CMD_SPI_READ_OCR 58
  97. #define MMC_CMD_SPI_CRC_ON_OFF 59
  98. #define MMC_CMD_RES_MAN 62
  99. #define MMC_CMD62_ARG1 0xefac62ec
  100. #define MMC_CMD62_ARG2 0xcbaea7
  101. #define SD_CMD_SEND_RELATIVE_ADDR 3
  102. #define SD_CMD_SWITCH_FUNC 6
  103. #define SD_CMD_SEND_IF_COND 8
  104. #define SD_CMD_SWITCH_UHS18V 11
  105. #define SD_CMD_APP_SET_BUS_WIDTH 6
  106. #define SD_CMD_APP_SD_STATUS 13
  107. #define SD_CMD_ERASE_WR_BLK_START 32
  108. #define SD_CMD_ERASE_WR_BLK_END 33
  109. #define SD_CMD_APP_SEND_OP_COND 41
  110. #define SD_CMD_APP_SEND_SCR 51
  111. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  112. {
  113. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  114. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  115. return true;
  116. return false;
  117. }
  118. /* SCR definitions in different words */
  119. #define SD_HIGHSPEED_BUSY 0x00020000
  120. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  121. #define UHS_SDR12_BUS_SPEED 0
  122. #define HIGH_SPEED_BUS_SPEED 1
  123. #define UHS_SDR25_BUS_SPEED 1
  124. #define UHS_SDR50_BUS_SPEED 2
  125. #define UHS_SDR104_BUS_SPEED 3
  126. #define UHS_DDR50_BUS_SPEED 4
  127. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  128. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  129. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  130. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  131. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  132. #define OCR_BUSY 0x80000000
  133. #define OCR_HCS 0x40000000
  134. #define OCR_S18R 0x1000000
  135. #define OCR_VOLTAGE_MASK 0x007FFF80
  136. #define OCR_ACCESS_MODE 0x60000000
  137. #define MMC_ERASE_ARG 0x00000000
  138. #define MMC_SECURE_ERASE_ARG 0x80000000
  139. #define MMC_TRIM_ARG 0x00000001
  140. #define MMC_DISCARD_ARG 0x00000003
  141. #define MMC_SECURE_TRIM1_ARG 0x80000001
  142. #define MMC_SECURE_TRIM2_ARG 0x80008000
  143. #define MMC_STATUS_MASK (~0x0206BF7F)
  144. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  145. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  146. #define MMC_STATUS_CURR_STATE (0xf << 9)
  147. #define MMC_STATUS_ERROR (1 << 19)
  148. #define MMC_STATE_PRG (7 << 9)
  149. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  150. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  151. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  152. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  153. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  154. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  155. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  156. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  157. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  158. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  159. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  160. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  161. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  162. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  163. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  164. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  165. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  166. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  167. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  168. addressed by index which are
  169. 1 in value field */
  170. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  171. addressed by index, which are
  172. 1 in value field */
  173. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  174. #define SD_SWITCH_CHECK 0
  175. #define SD_SWITCH_SWITCH 1
  176. /*
  177. * EXT_CSD fields
  178. */
  179. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  180. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  181. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  182. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  183. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  184. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  185. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  186. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  187. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  188. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  189. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  190. #define EXT_CSD_RPMB_MULT 168 /* RO */
  191. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  192. #define EXT_CSD_BOOT_BUS_WIDTH 177
  193. #define EXT_CSD_PART_CONF 179 /* R/W */
  194. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  195. #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
  196. #define EXT_CSD_HS_TIMING 185 /* R/W */
  197. #define EXT_CSD_REV 192 /* RO */
  198. #define EXT_CSD_CARD_TYPE 196 /* RO */
  199. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  200. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  201. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  202. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  203. #define EXT_CSD_BOOT_MULT 226 /* RO */
  204. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  205. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  206. /*
  207. * EXT_CSD field definitions
  208. */
  209. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  210. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  211. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  212. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  213. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  214. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  215. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  216. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  217. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  218. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  219. /* SDR mode @1.8V I/O */
  220. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  221. /* SDR mode @1.2V I/O */
  222. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  223. EXT_CSD_CARD_TYPE_HS200_1_2V)
  224. #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
  225. #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
  226. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  227. EXT_CSD_CARD_TYPE_HS400_1_2V)
  228. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  229. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  230. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  231. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  232. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  233. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  234. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  235. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  236. #define EXT_CSD_TIMING_HS 1 /* HS */
  237. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  238. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  239. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  240. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  241. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  242. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  243. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  244. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  245. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  246. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  247. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  248. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  249. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  250. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  251. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  252. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  253. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  254. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  255. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  256. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  257. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  258. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  259. #define R1_ILLEGAL_COMMAND (1 << 22)
  260. #define R1_APP_CMD (1 << 5)
  261. #define MMC_RSP_PRESENT (1 << 0)
  262. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  263. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  264. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  265. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  266. #define MMC_RSP_NONE (0)
  267. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  268. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  269. MMC_RSP_BUSY)
  270. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  271. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  272. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  273. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  274. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  275. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  276. #define MMCPART_NOAVAILABLE (0xff)
  277. #define PART_ACCESS_MASK (0x7)
  278. #define PART_SUPPORT (0x1)
  279. #define ENHNCD_SUPPORT (0x2)
  280. #define PART_ENH_ATTRIB (0x1f)
  281. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  282. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  283. enum mmc_voltage {
  284. MMC_SIGNAL_VOLTAGE_000 = 0,
  285. MMC_SIGNAL_VOLTAGE_120 = 1,
  286. MMC_SIGNAL_VOLTAGE_180 = 2,
  287. MMC_SIGNAL_VOLTAGE_330 = 4,
  288. };
  289. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  290. MMC_SIGNAL_VOLTAGE_180 |\
  291. MMC_SIGNAL_VOLTAGE_330)
  292. /* Maximum block size for MMC */
  293. #define MMC_MAX_BLOCK_LEN 512
  294. /* The number of MMC physical partitions. These consist of:
  295. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  296. */
  297. #define MMC_NUM_BOOT_PARTITION 2
  298. #define MMC_PART_RPMB 3 /* RPMB partition number */
  299. /* Driver model support */
  300. /**
  301. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  302. */
  303. struct mmc_uclass_priv {
  304. struct mmc *mmc;
  305. };
  306. /**
  307. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  308. *
  309. * Provided that the device is already probed and ready for use, this value
  310. * will be available.
  311. *
  312. * @dev: Device
  313. * @return associated mmc struct pointer if available, else NULL
  314. */
  315. struct mmc *mmc_get_mmc_dev(struct udevice *dev);
  316. /* End of driver model support */
  317. struct mmc_cid {
  318. unsigned long psn;
  319. unsigned short oid;
  320. unsigned char mid;
  321. unsigned char prv;
  322. unsigned char mdt;
  323. char pnm[7];
  324. };
  325. struct mmc_cmd {
  326. ushort cmdidx;
  327. uint resp_type;
  328. uint cmdarg;
  329. uint response[4];
  330. };
  331. struct mmc_data {
  332. union {
  333. char *dest;
  334. const char *src; /* src buffers don't get written to */
  335. };
  336. uint flags;
  337. uint blocks;
  338. uint blocksize;
  339. };
  340. /* forward decl. */
  341. struct mmc;
  342. #if CONFIG_IS_ENABLED(DM_MMC)
  343. struct dm_mmc_ops {
  344. /**
  345. * send_cmd() - Send a command to the MMC device
  346. *
  347. * @dev: Device to receive the command
  348. * @cmd: Command to send
  349. * @data: Additional data to send/receive
  350. * @return 0 if OK, -ve on error
  351. */
  352. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  353. struct mmc_data *data);
  354. /**
  355. * set_ios() - Set the I/O speed/width for an MMC device
  356. *
  357. * @dev: Device to update
  358. * @return 0 if OK, -ve on error
  359. */
  360. int (*set_ios)(struct udevice *dev);
  361. /**
  362. * get_cd() - See whether a card is present
  363. *
  364. * @dev: Device to check
  365. * @return 0 if not present, 1 if present, -ve on error
  366. */
  367. int (*get_cd)(struct udevice *dev);
  368. /**
  369. * get_wp() - See whether a card has write-protect enabled
  370. *
  371. * @dev: Device to check
  372. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  373. */
  374. int (*get_wp)(struct udevice *dev);
  375. #ifdef MMC_SUPPORTS_TUNING
  376. /**
  377. * execute_tuning() - Start the tuning process
  378. *
  379. * @dev: Device to start the tuning
  380. * @opcode: Command opcode to send
  381. * @return 0 if OK, -ve on error
  382. */
  383. int (*execute_tuning)(struct udevice *dev, uint opcode);
  384. #endif
  385. /**
  386. * wait_dat0() - wait until dat0 is in the target state
  387. * (CLK must be running during the wait)
  388. *
  389. * @dev: Device to check
  390. * @state: target state
  391. * @timeout_us: timeout in us
  392. * @return 0 if dat0 is in the target state, -ve on error
  393. */
  394. int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
  395. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  396. /* set_enhanced_strobe() - set HS400 enhanced strobe */
  397. int (*set_enhanced_strobe)(struct udevice *dev);
  398. #endif
  399. /**
  400. * host_power_cycle - host specific tasks in power cycle sequence
  401. * Called between mmc_power_off() and
  402. * mmc_power_on()
  403. *
  404. * @dev: Device to check
  405. * @return 0 if not present, 1 if present, -ve on error
  406. */
  407. int (*host_power_cycle)(struct udevice *dev);
  408. };
  409. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  410. int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  411. struct mmc_data *data);
  412. int dm_mmc_set_ios(struct udevice *dev);
  413. int dm_mmc_get_cd(struct udevice *dev);
  414. int dm_mmc_get_wp(struct udevice *dev);
  415. int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
  416. int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
  417. int dm_mmc_host_power_cycle(struct udevice *dev);
  418. /* Transition functions for compatibility */
  419. int mmc_set_ios(struct mmc *mmc);
  420. int mmc_getcd(struct mmc *mmc);
  421. int mmc_getwp(struct mmc *mmc);
  422. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  423. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
  424. int mmc_set_enhanced_strobe(struct mmc *mmc);
  425. int mmc_host_power_cycle(struct mmc *mmc);
  426. #else
  427. struct mmc_ops {
  428. int (*send_cmd)(struct mmc *mmc,
  429. struct mmc_cmd *cmd, struct mmc_data *data);
  430. int (*set_ios)(struct mmc *mmc);
  431. int (*init)(struct mmc *mmc);
  432. int (*getcd)(struct mmc *mmc);
  433. int (*getwp)(struct mmc *mmc);
  434. int (*host_power_cycle)(struct mmc *mmc);
  435. };
  436. #endif
  437. struct mmc_config {
  438. const char *name;
  439. #if !CONFIG_IS_ENABLED(DM_MMC)
  440. const struct mmc_ops *ops;
  441. #endif
  442. uint host_caps;
  443. uint voltages;
  444. uint f_min;
  445. uint f_max;
  446. uint b_max;
  447. unsigned char part_type;
  448. };
  449. struct sd_ssr {
  450. unsigned int au; /* In sectors */
  451. unsigned int erase_timeout; /* In milliseconds */
  452. unsigned int erase_offset; /* In milliseconds */
  453. };
  454. enum bus_mode {
  455. MMC_LEGACY,
  456. SD_LEGACY,
  457. MMC_HS,
  458. SD_HS,
  459. MMC_HS_52,
  460. MMC_DDR_52,
  461. UHS_SDR12,
  462. UHS_SDR25,
  463. UHS_SDR50,
  464. UHS_DDR50,
  465. UHS_SDR104,
  466. MMC_HS_200,
  467. MMC_HS_400,
  468. MMC_HS_400_ES,
  469. MMC_MODES_END
  470. };
  471. const char *mmc_mode_name(enum bus_mode mode);
  472. void mmc_dump_capabilities(const char *text, uint caps);
  473. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  474. {
  475. if (mode == MMC_DDR_52)
  476. return true;
  477. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  478. else if (mode == UHS_DDR50)
  479. return true;
  480. #endif
  481. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  482. else if (mode == MMC_HS_400)
  483. return true;
  484. #endif
  485. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  486. else if (mode == MMC_HS_400_ES)
  487. return true;
  488. #endif
  489. else
  490. return false;
  491. }
  492. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  493. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  494. MMC_CAP(UHS_DDR50))
  495. static inline bool supports_uhs(uint caps)
  496. {
  497. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  498. return (caps & UHS_CAPS) ? true : false;
  499. #else
  500. return false;
  501. #endif
  502. }
  503. /*
  504. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  505. * with mmc_get_mmc_dev().
  506. *
  507. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  508. */
  509. struct mmc {
  510. #if !CONFIG_IS_ENABLED(BLK)
  511. struct list_head link;
  512. #endif
  513. const struct mmc_config *cfg; /* provided configuration */
  514. uint version;
  515. void *priv;
  516. uint has_init;
  517. int high_capacity;
  518. bool clk_disable; /* true if the clock can be turned off */
  519. uint bus_width;
  520. uint clock;
  521. enum mmc_voltage signal_voltage;
  522. uint card_caps;
  523. uint host_caps;
  524. uint ocr;
  525. uint dsr;
  526. uint dsr_imp;
  527. uint scr[2];
  528. uint csd[4];
  529. uint cid[4];
  530. ushort rca;
  531. u8 part_support;
  532. u8 part_attr;
  533. u8 wr_rel_set;
  534. u8 part_config;
  535. u8 gen_cmd6_time; /* units: 10 ms */
  536. u8 part_switch_time; /* units: 10 ms */
  537. uint tran_speed;
  538. uint legacy_speed; /* speed for the legacy mode provided by the card */
  539. uint read_bl_len;
  540. #if CONFIG_IS_ENABLED(MMC_WRITE)
  541. uint write_bl_len;
  542. uint erase_grp_size; /* in 512-byte sectors */
  543. #endif
  544. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  545. uint hc_wp_grp_size; /* in 512-byte sectors */
  546. #endif
  547. #if CONFIG_IS_ENABLED(MMC_WRITE)
  548. struct sd_ssr ssr; /* SD status register */
  549. #endif
  550. u64 capacity;
  551. u64 capacity_user;
  552. u64 capacity_boot;
  553. u64 capacity_rpmb;
  554. u64 capacity_gp[4];
  555. #ifndef CONFIG_SPL_BUILD
  556. u64 enh_user_start;
  557. u64 enh_user_size;
  558. #endif
  559. #if !CONFIG_IS_ENABLED(BLK)
  560. struct blk_desc block_dev;
  561. #endif
  562. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  563. char init_in_progress; /* 1 if we have done mmc_start_init() */
  564. char preinit; /* start init as early as possible */
  565. int ddr_mode;
  566. #if CONFIG_IS_ENABLED(DM_MMC)
  567. struct udevice *dev; /* Device for this MMC controller */
  568. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  569. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  570. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  571. #endif
  572. #endif
  573. u8 *ext_csd;
  574. u32 cardtype; /* cardtype read from the MMC */
  575. enum mmc_voltage current_voltage;
  576. enum bus_mode selected_mode; /* mode currently used */
  577. enum bus_mode best_mode; /* best mode is the supported mode with the
  578. * highest bandwidth. It may not always be the
  579. * operating mode due to limitations when
  580. * accessing the boot partitions
  581. */
  582. u32 quirks;
  583. };
  584. struct mmc_hwpart_conf {
  585. struct {
  586. uint enh_start; /* in 512-byte sectors */
  587. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  588. unsigned wr_rel_change : 1;
  589. unsigned wr_rel_set : 1;
  590. } user;
  591. struct {
  592. uint size; /* in 512-byte sectors */
  593. unsigned enhanced : 1;
  594. unsigned wr_rel_change : 1;
  595. unsigned wr_rel_set : 1;
  596. } gp_part[4];
  597. };
  598. enum mmc_hwpart_conf_mode {
  599. MMC_HWPART_CONF_CHECK,
  600. MMC_HWPART_CONF_SET,
  601. MMC_HWPART_CONF_COMPLETE,
  602. };
  603. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  604. /**
  605. * mmc_bind() - Set up a new MMC device ready for probing
  606. *
  607. * A child block device is bound with the IF_TYPE_MMC interface type. This
  608. * allows the device to be used with CONFIG_BLK
  609. *
  610. * @dev: MMC device to set up
  611. * @mmc: MMC struct
  612. * @cfg: MMC configuration
  613. * @return 0 if OK, -ve on error
  614. */
  615. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  616. const struct mmc_config *cfg);
  617. void mmc_destroy(struct mmc *mmc);
  618. /**
  619. * mmc_unbind() - Unbind a MMC device's child block device
  620. *
  621. * @dev: MMC device
  622. * @return 0 if OK, -ve on error
  623. */
  624. int mmc_unbind(struct udevice *dev);
  625. int mmc_initialize(bd_t *bis);
  626. int mmc_init_device(int num);
  627. int snps_mmc_init(struct mmc *mmc);
  628. int mmc_init(struct mmc *mmc);
  629. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  630. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  631. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  632. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  633. int mmc_deinit(struct mmc *mmc);
  634. #endif
  635. /**
  636. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  637. *
  638. * @dev: MMC device
  639. * @cfg: MMC configuration
  640. * @return 0 if OK, -ve on error
  641. */
  642. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  643. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  644. /**
  645. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  646. *
  647. * @voltage: The mmc_voltage to convert
  648. * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  649. */
  650. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  651. /**
  652. * mmc_set_clock() - change the bus clock
  653. * @mmc: MMC struct
  654. * @clock: bus frequency in Hz
  655. * @disable: flag indicating if the clock must on or off
  656. * @return 0 if OK, -ve on error
  657. */
  658. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  659. #define MMC_CLK_ENABLE false
  660. #define MMC_CLK_DISABLE true
  661. struct mmc *find_mmc_device(int dev_num);
  662. int mmc_set_dev(int dev_num);
  663. void print_mmc_devices(char separator);
  664. /**
  665. * get_mmc_num() - get the total MMC device number
  666. *
  667. * @return 0 if there is no MMC device, else the number of devices
  668. */
  669. int get_mmc_num(void);
  670. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  671. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  672. enum mmc_hwpart_conf_mode mode);
  673. #if !CONFIG_IS_ENABLED(DM_MMC)
  674. int mmc_getcd(struct mmc *mmc);
  675. int board_mmc_getcd(struct mmc *mmc);
  676. int mmc_getwp(struct mmc *mmc);
  677. int board_mmc_getwp(struct mmc *mmc);
  678. #endif
  679. int mmc_set_dsr(struct mmc *mmc, u16 val);
  680. /* Function to change the size of boot partition and rpmb partitions */
  681. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  682. unsigned long rpmbsize);
  683. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  684. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  685. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  686. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  687. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  688. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  689. /* Functions to read / write the RPMB partition */
  690. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  691. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  692. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  693. unsigned short cnt, unsigned char *key);
  694. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  695. unsigned short cnt, unsigned char *key);
  696. /**
  697. * mmc_rpmb_route_frames() - route RPMB data frames
  698. * @mmc Pointer to a MMC device struct
  699. * @req Request data frames
  700. * @reqlen Length of data frames in bytes
  701. * @rsp Supplied buffer for response data frames
  702. * @rsplen Length of supplied buffer for response data frames
  703. *
  704. * The RPMB data frames are routed to/from some external entity, for
  705. * example a Trusted Exectuion Environment in an arm TrustZone protected
  706. * secure world. It's expected that it's the external entity who is in
  707. * control of the RPMB key.
  708. *
  709. * Returns 0 on success, < 0 on error.
  710. */
  711. int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
  712. void *rsp, unsigned long rsplen);
  713. #ifdef CONFIG_CMD_BKOPS_ENABLE
  714. int mmc_set_bkops_enable(struct mmc *mmc);
  715. #endif
  716. /**
  717. * Start device initialization and return immediately; it does not block on
  718. * polling OCR (operation condition register) status. Useful for checking
  719. * the presence of SD/eMMC when no card detect logic is available.
  720. *
  721. * @param mmc Pointer to a MMC device struct
  722. * @return 0 on success, <0 on error.
  723. */
  724. int mmc_get_op_cond(struct mmc *mmc);
  725. /**
  726. * Start device initialization and return immediately; it does not block on
  727. * polling OCR (operation condition register) status. Then you should call
  728. * mmc_init, which would block on polling OCR status and complete the device
  729. * initializatin.
  730. *
  731. * @param mmc Pointer to a MMC device struct
  732. * @return 0 on success, <0 on error.
  733. */
  734. int mmc_start_init(struct mmc *mmc);
  735. /**
  736. * Set preinit flag of mmc device.
  737. *
  738. * This will cause the device to be pre-inited during mmc_initialize(),
  739. * which may save boot time if the device is not accessed until later.
  740. * Some eMMC devices take 200-300ms to init, but unfortunately they
  741. * must be sent a series of commands to even get them to start preparing
  742. * for operation.
  743. *
  744. * @param mmc Pointer to a MMC device struct
  745. * @param preinit preinit flag value
  746. */
  747. void mmc_set_preinit(struct mmc *mmc, int preinit);
  748. #ifdef CONFIG_MMC_SPI
  749. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  750. #else
  751. #define mmc_host_is_spi(mmc) 0
  752. #endif
  753. void board_mmc_power_init(void);
  754. int board_mmc_init(bd_t *bis);
  755. int cpu_mmc_init(bd_t *bis);
  756. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  757. # ifdef CONFIG_SYS_MMC_ENV_PART
  758. extern uint mmc_get_env_part(struct mmc *mmc);
  759. # endif
  760. int mmc_get_env_dev(void);
  761. int mmc_select_speed_mode(struct mmc *mmc, enum bus_mode mode);
  762. int sd_select_speed_mode(struct mmc *mmc, enum bus_mode mode);
  763. int mmc_resetore_mmc_modes_by_pref(void);
  764. int sd_resetore_sd_modes_by_pref(void);
  765. /* Minimum partition switch timeout in units of 10-milliseconds */
  766. #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
  767. /* Set block count limit because of 16 bit register limit on some hardware*/
  768. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  769. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
  770. #endif
  771. /**
  772. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  773. *
  774. * @mmc: MMC device
  775. * @return block device if found, else NULL
  776. */
  777. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  778. #endif /* _MMC_H_ */