xhci-omap.h 3.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Inc, <www.ti.com>
  5. *
  6. * Author: Dan Murphy <dmurphy@ti.com>
  7. */
  8. #ifndef _ASM_ARCH_XHCI_OMAP_H_
  9. #define _ASM_ARCH_XHCI_OMAP_H_
  10. #ifdef CONFIG_DRA7XX
  11. #if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
  12. #define OMAP_XHCI_BASE 0x488d0000
  13. #define OMAP_OCP1_SCP_BASE 0x4A081000
  14. #define OMAP_OTG_WRAPPER_BASE 0x488c0000
  15. #elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
  16. #define OMAP_XHCI_BASE 0x48890000
  17. #define OMAP_OCP1_SCP_BASE 0x4A084c00
  18. #define OMAP_OTG_WRAPPER_BASE 0x48880000
  19. #endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
  20. #elif defined CONFIG_AM43XX
  21. #define OMAP_XHCI_BASE 0x483d0000
  22. #define OMAP_OCP1_SCP_BASE 0x483E8000
  23. #define OMAP_OTG_WRAPPER_BASE 0x483dc100
  24. #else
  25. /* Default to the OMAP5 XHCI defines */
  26. #define OMAP_XHCI_BASE 0x4a030000
  27. #define OMAP_OCP1_SCP_BASE 0x4a084c00
  28. #define OMAP_OTG_WRAPPER_BASE 0x4A020000
  29. #endif
  30. /* Phy register MACRO definitions */
  31. #define PLL_REGM_MASK 0x001FFE00
  32. #define PLL_REGM_SHIFT 0x9
  33. #define PLL_REGM_F_MASK 0x0003FFFF
  34. #define PLL_REGM_F_SHIFT 0x0
  35. #define PLL_REGN_MASK 0x000001FE
  36. #define PLL_REGN_SHIFT 0x1
  37. #define PLL_SELFREQDCO_MASK 0x0000000E
  38. #define PLL_SELFREQDCO_SHIFT 0x1
  39. #define PLL_SD_MASK 0x0003FC00
  40. #define PLL_SD_SHIFT 0x9
  41. #define SET_PLL_GO 0x1
  42. #define PLL_TICOPWDN 0x10000
  43. #define PLL_LOCK 0x2
  44. #define PLL_IDLE 0x1
  45. #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
  46. #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
  47. #define USB3_PHY_PARTIAL_RX_POWERON (1 << 6)
  48. #define USB3_PHY_RX_POWERON (1 << 14)
  49. #define USB3_PHY_TX_POWERON (1 << 15)
  50. #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
  51. #define USB3_PWRCTL_CLK_CMD_SHIFT 14
  52. #define USB3_PWRCTL_CLK_FREQ_SHIFT 22
  53. /* USBOTGSS_WRAPPER definitions */
  54. #define USBOTGSS_WRAPRESET (1 << 17)
  55. #define USBOTGSS_DMADISABLE (1 << 16)
  56. #define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
  57. #define USBOTGSS_STANDBYMODE_SMRT (1 << 5)
  58. #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
  59. #define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
  60. #define USBOTGSS_IDLEMODE_SMRT (1 << 3)
  61. #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
  62. /* USBOTGSS_IRQENABLE_SET_0 bit */
  63. #define USBOTGSS_COREIRQ_EN (1 << 0)
  64. /* USBOTGSS_IRQENABLE_SET_1 bits */
  65. #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0)
  66. #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3)
  67. #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4)
  68. #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5)
  69. #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8)
  70. #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11)
  71. #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12)
  72. #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13)
  73. #define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16)
  74. #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17)
  75. /*
  76. * USBOTGSS_WRAPPER registers
  77. */
  78. struct omap_dwc_wrapper {
  79. u32 revision;
  80. u32 reserve_1[3];
  81. u32 sysconfig; /* offset of 0x10 */
  82. u32 reserve_2[3];
  83. u16 reserve_3;
  84. u32 irqstatus_raw_0; /* offset of 0x24 */
  85. u32 irqstatus_0;
  86. u32 irqenable_set_0;
  87. u32 irqenable_clr_0;
  88. u32 irqstatus_raw_1; /* offset of 0x34 */
  89. u32 irqstatus_1;
  90. u32 irqenable_set_1;
  91. u32 irqenable_clr_1;
  92. u32 reserve_4[15];
  93. u32 utmi_otg_ctrl; /* offset of 0x80 */
  94. u32 utmi_otg_status;
  95. u32 reserve_5[30];
  96. u32 mram_offset; /* offset of 0x100 */
  97. u32 fladj;
  98. u32 dbg_config;
  99. u32 dbg_data;
  100. u32 dev_ebc_en;
  101. };
  102. /* XHCI PHY register structure */
  103. struct omap_usb3_phy {
  104. u32 reserve1;
  105. u32 pll_status;
  106. u32 pll_go;
  107. u32 pll_config_1;
  108. u32 pll_config_2;
  109. u32 pll_config_3;
  110. u32 pll_ssc_config_1;
  111. u32 pll_ssc_config_2;
  112. u32 pll_config_4;
  113. };
  114. struct omap_xhci {
  115. struct omap_dwc_wrapper *otg_wrapper;
  116. struct omap_usb3_phy *usb3_phy;
  117. struct xhci_hccr *hcd;
  118. struct dwc3 *dwc3_reg;
  119. };
  120. /* USB PHY functions */
  121. void omap_enable_phy(struct omap_xhci *omap);
  122. void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
  123. void usb_phy_power(int on);
  124. #endif /* _ASM_ARCH_XHCI_OMAP_H_ */