dwc3.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* include/linux/usb/dwc3.h
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co. Ltd
  5. *
  6. * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
  7. */
  8. #ifndef __DWC3_H_
  9. #define __DWC3_H_
  10. /* Global constants */
  11. #define DWC3_ENDPOINTS_NUM 32
  12. #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
  13. #define DWC3_EVENT_TYPE_MASK 0xfe
  14. #define DWC3_EVENT_TYPE_DEV 0
  15. #define DWC3_EVENT_TYPE_CARKIT 3
  16. #define DWC3_EVENT_TYPE_I2C 4
  17. #define DWC3_DEVICE_EVENT_DISCONNECT 0
  18. #define DWC3_DEVICE_EVENT_RESET 1
  19. #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
  20. #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
  21. #define DWC3_DEVICE_EVENT_WAKEUP 4
  22. #define DWC3_DEVICE_EVENT_EOPF 6
  23. #define DWC3_DEVICE_EVENT_SOF 7
  24. #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
  25. #define DWC3_DEVICE_EVENT_CMD_CMPL 10
  26. #define DWC3_DEVICE_EVENT_OVERFLOW 11
  27. #define DWC3_GEVNTCOUNT_MASK 0xfffc
  28. #define DWC3_GSNPSID_MASK 0xffff0000
  29. #define DWC3_GSNPSID_SHIFT 16
  30. #define DWC3_GSNPSREV_MASK 0xffff
  31. #define DWC3_REVISION_MASK 0xffff
  32. #define DWC3_REG_OFFSET 0xC100
  33. struct g_event_buffer {
  34. u32 g_evntadrlo;
  35. u32 g_evntadrhi;
  36. u32 g_evntsiz;
  37. u32 g_evntcount;
  38. };
  39. struct d_physical_endpoint {
  40. u32 d_depcmdpar2;
  41. u32 d_depcmdpar1;
  42. u32 d_depcmdpar0;
  43. u32 d_depcmd;
  44. };
  45. struct dwc3 { /* offset: 0xC100 */
  46. u32 g_sbuscfg0;
  47. u32 g_sbuscfg1;
  48. u32 g_txthrcfg;
  49. u32 g_rxthrcfg;
  50. u32 g_ctl;
  51. u32 reserved1;
  52. u32 g_sts;
  53. u32 reserved2;
  54. u32 g_snpsid;
  55. u32 g_gpio;
  56. u32 g_uid;
  57. u32 g_uctl;
  58. u64 g_buserraddr;
  59. u64 g_prtbimap;
  60. u32 g_hwparams0;
  61. u32 g_hwparams1;
  62. u32 g_hwparams2;
  63. u32 g_hwparams3;
  64. u32 g_hwparams4;
  65. u32 g_hwparams5;
  66. u32 g_hwparams6;
  67. u32 g_hwparams7;
  68. u32 g_dbgfifospace;
  69. u32 g_dbgltssm;
  70. u32 g_dbglnmcc;
  71. u32 g_dbgbmu;
  72. u32 g_dbglspmux;
  73. u32 g_dbglsp;
  74. u32 g_dbgepinfo0;
  75. u32 g_dbgepinfo1;
  76. u64 g_prtbimap_hs;
  77. u64 g_prtbimap_fs;
  78. u32 reserved3[28];
  79. u32 g_usb2phycfg[16];
  80. u32 g_usb2i2cctl[16];
  81. u32 g_usb2phyacc[16];
  82. u32 g_usb3pipectl[16];
  83. u32 g_txfifosiz[32];
  84. u32 g_rxfifosiz[32];
  85. struct g_event_buffer g_evnt_buf[32];
  86. u32 g_hwparams8;
  87. u32 reserved4[11];
  88. u32 g_fladj;
  89. u32 reserved5[51];
  90. u32 d_cfg;
  91. u32 d_ctl;
  92. u32 d_evten;
  93. u32 d_sts;
  94. u32 d_gcmdpar;
  95. u32 d_gcmd;
  96. u32 reserved6[2];
  97. u32 d_alepena;
  98. u32 reserved7[55];
  99. struct d_physical_endpoint d_phy_ep_cmd[32];
  100. u32 reserved8[128];
  101. u32 o_cfg;
  102. u32 o_ctl;
  103. u32 o_evt;
  104. u32 o_evten;
  105. u32 o_sts;
  106. u32 reserved9[3];
  107. u32 adp_cfg;
  108. u32 adp_ctl;
  109. u32 adp_evt;
  110. u32 adp_evten;
  111. u32 bc_cfg;
  112. u32 reserved10;
  113. u32 bc_evt;
  114. u32 bc_evten;
  115. };
  116. /* Global Configuration Register */
  117. #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
  118. #define DWC3_GCTL_U2RSTECN (1 << 16)
  119. #define DWC3_GCTL_RAMCLKSEL(x) \
  120. (((x) & DWC3_GCTL_CLK_MASK) << 6)
  121. #define DWC3_GCTL_CLK_BUS (0)
  122. #define DWC3_GCTL_CLK_PIPE (1)
  123. #define DWC3_GCTL_CLK_PIPEHALF (2)
  124. #define DWC3_GCTL_CLK_MASK (3)
  125. #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
  126. #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
  127. #define DWC3_GCTL_PRTCAP_HOST 1
  128. #define DWC3_GCTL_PRTCAP_DEVICE 2
  129. #define DWC3_GCTL_PRTCAP_OTG 3
  130. #define DWC3_GCTL_CORESOFTRESET (1 << 11)
  131. #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
  132. #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
  133. #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
  134. #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
  135. /* Global HWPARAMS1 Register */
  136. #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
  137. #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
  138. #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
  139. /* Global USB2 PHY Configuration Register */
  140. #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
  141. #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
  142. #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
  143. #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
  144. #define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
  145. /* Global USB2 PHY Configuration Mask */
  146. #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
  147. /* Global USB2 PHY Configuration Offset */
  148. #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
  149. #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
  150. DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
  151. #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
  152. DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
  153. /* Global USB3 PIPE Control Register */
  154. #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
  155. #define DWC3_GUSB3PIPECTL_DISRXDETP3 (1 << 28)
  156. #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
  157. /* Global TX Fifo Size Register */
  158. #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
  159. #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
  160. /* Device Control Register */
  161. #define DWC3_DCTL_RUN_STOP (1 << 31)
  162. #define DWC3_DCTL_CSFTRST (1 << 30)
  163. #define DWC3_DCTL_LSFTRST (1 << 29)
  164. /* Global Frame Length Adjustment Register */
  165. #define GFLADJ_30MHZ_REG_SEL (1 << 7)
  166. #define GFLADJ_30MHZ(n) ((n) & 0x3f)
  167. #define GFLADJ_30MHZ_DEFAULT 0x20
  168. #ifdef CONFIG_USB_XHCI_DWC3
  169. void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
  170. void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
  171. int dwc3_core_init(struct dwc3 *dwc3_reg);
  172. void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
  173. #endif
  174. #endif /* __DWC3_H_ */