serial_reg.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * include/linux/serial_reg.h
  4. *
  5. * Copyright (C) 1992, 1994 by Theodore Ts'o.
  6. *
  7. * These are the UART port assignments, expressed as offsets from the base
  8. * register. These assignments should hold for any serial port based on
  9. * a 8250, 16450, or 16550(A).
  10. */
  11. #ifndef _LINUX_SERIAL_REG_H
  12. #define _LINUX_SERIAL_REG_H
  13. /*
  14. * DLAB=0
  15. */
  16. #define UART_RX 0 /* In: Receive buffer */
  17. #define UART_TX 0 /* Out: Transmit buffer */
  18. #define UART_IER 1 /* Out: Interrupt Enable Register */
  19. #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
  20. #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
  21. #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
  22. #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
  23. /*
  24. * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
  25. */
  26. #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
  27. #define UART_IIR 2 /* In: Interrupt ID Register */
  28. #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
  29. #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
  30. #define UART_IIR_MSI 0x00 /* Modem status interrupt */
  31. #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
  32. #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
  33. #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
  34. #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
  35. #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
  36. #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */
  37. #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */
  38. #define UART_FCR 2 /* Out: FIFO Control Register */
  39. #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
  40. #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
  41. #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
  42. #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
  43. /*
  44. * Note: The FIFO trigger levels are chip specific:
  45. * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
  46. * PC16550D: 1 4 8 14 xx xx xx xx
  47. * TI16C550A: 1 4 8 14 xx xx xx xx
  48. * TI16C550C: 1 4 8 14 xx xx xx xx
  49. * ST16C550: 1 4 8 14 xx xx xx xx
  50. * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
  51. * NS16C552: 1 4 8 14 xx xx xx xx
  52. * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
  53. * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
  54. * TI16C752: 8 16 56 60 8 16 32 56
  55. * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
  56. */
  57. #define UART_FCR_R_TRIG_00 0x00
  58. #define UART_FCR_R_TRIG_01 0x40
  59. #define UART_FCR_R_TRIG_10 0x80
  60. #define UART_FCR_R_TRIG_11 0xc0
  61. #define UART_FCR_T_TRIG_00 0x00
  62. #define UART_FCR_T_TRIG_01 0x10
  63. #define UART_FCR_T_TRIG_10 0x20
  64. #define UART_FCR_T_TRIG_11 0x30
  65. #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
  66. #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
  67. #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
  68. #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
  69. #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
  70. /* 16650 definitions */
  71. #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
  72. #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
  73. #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
  74. #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
  75. #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
  76. #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
  77. #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
  78. #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
  79. #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
  80. #define UART_LCR 3 /* Out: Line Control Register */
  81. /*
  82. * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  83. * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  84. */
  85. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  86. #define UART_LCR_SBC 0x40 /* Set break control */
  87. #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
  88. #define UART_LCR_EPAR 0x10 /* Even parity select */
  89. #define UART_LCR_PARITY 0x08 /* Parity Enable */
  90. #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
  91. #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
  92. #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
  93. #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
  94. #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
  95. /*
  96. * Access to some registers depends on register access / configuration
  97. * mode.
  98. */
  99. #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
  100. #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
  101. #define UART_MCR 4 /* Out: Modem Control Register */
  102. #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
  103. #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
  104. #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
  105. #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
  106. #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
  107. #define UART_MCR_OUT2 0x08 /* Out2 complement */
  108. #define UART_MCR_OUT1 0x04 /* Out1 complement */
  109. #define UART_MCR_RTS 0x02 /* RTS complement */
  110. #define UART_MCR_DTR 0x01 /* DTR complement */
  111. #define UART_LSR 5 /* In: Line Status Register */
  112. #define UART_LSR_FIFOE 0x80 /* Fifo error */
  113. #define UART_LSR_TEMT 0x40 /* Transmitter empty */
  114. #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
  115. #define UART_LSR_BI 0x10 /* Break interrupt indicator */
  116. #define UART_LSR_FE 0x08 /* Frame error indicator */
  117. #define UART_LSR_PE 0x04 /* Parity error indicator */
  118. #define UART_LSR_OE 0x02 /* Overrun error indicator */
  119. #define UART_LSR_DR 0x01 /* Receiver data ready */
  120. #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
  121. #define UART_MSR 6 /* In: Modem Status Register */
  122. #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
  123. #define UART_MSR_RI 0x40 /* Ring Indicator */
  124. #define UART_MSR_DSR 0x20 /* Data Set Ready */
  125. #define UART_MSR_CTS 0x10 /* Clear to Send */
  126. #define UART_MSR_DDCD 0x08 /* Delta DCD */
  127. #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
  128. #define UART_MSR_DDSR 0x02 /* Delta DSR */
  129. #define UART_MSR_DCTS 0x01 /* Delta CTS */
  130. #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  131. #define UART_SCR 7 /* I/O: Scratch Register */
  132. /*
  133. * DLAB=1
  134. */
  135. #define UART_DLL 0 /* Out: Divisor Latch Low */
  136. #define UART_DLM 1 /* Out: Divisor Latch High */
  137. /*
  138. * LCR=0xBF (or DLAB=1 for 16C660)
  139. */
  140. #define UART_EFR 2 /* I/O: Extended Features Register */
  141. #define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */
  142. #define UART_EFR_CTS 0x80 /* CTS flow control */
  143. #define UART_EFR_RTS 0x40 /* RTS flow control */
  144. #define UART_EFR_SCD 0x20 /* Special character detect */
  145. #define UART_EFR_ECB 0x10 /* Enhanced control bit */
  146. /*
  147. * the low four bits control software flow control
  148. */
  149. /*
  150. * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
  151. */
  152. #define UART_XON1 4 /* I/O: Xon character 1 */
  153. #define UART_XON2 5 /* I/O: Xon character 2 */
  154. #define UART_XOFF1 6 /* I/O: Xoff character 1 */
  155. #define UART_XOFF2 7 /* I/O: Xoff character 2 */
  156. /*
  157. * EFR[4]=1 MCR[6]=1, TI16C752
  158. */
  159. #define UART_TI752_TCR 6 /* I/O: transmission control register */
  160. #define UART_TI752_TLR 7 /* I/O: trigger level register */
  161. /*
  162. * LCR=0xBF, XR16C85x
  163. */
  164. #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
  165. * In: Fifo count
  166. * Out: Fifo custom trigger levels */
  167. /*
  168. * These are the definitions for the Programmable Trigger Register
  169. */
  170. #define UART_TRG_1 0x01
  171. #define UART_TRG_4 0x04
  172. #define UART_TRG_8 0x08
  173. #define UART_TRG_16 0x10
  174. #define UART_TRG_32 0x20
  175. #define UART_TRG_64 0x40
  176. #define UART_TRG_96 0x60
  177. #define UART_TRG_120 0x78
  178. #define UART_TRG_128 0x80
  179. #define UART_FCTR 1 /* Feature Control Register */
  180. #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
  181. #define UART_FCTR_RTS_4DELAY 0x01
  182. #define UART_FCTR_RTS_6DELAY 0x02
  183. #define UART_FCTR_RTS_8DELAY 0x03
  184. #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
  185. #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
  186. #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
  187. #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
  188. #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
  189. #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
  190. #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
  191. #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
  192. #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
  193. /*
  194. * LCR=0xBF, FCTR[6]=1
  195. */
  196. #define UART_EMSR 7 /* Extended Mode Select Register */
  197. #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
  198. #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
  199. /*
  200. * The Intel XScale on-chip UARTs define these bits
  201. */
  202. #define UART_IER_DMAE 0x80 /* DMA Requests Enable */
  203. #define UART_IER_UUE 0x40 /* UART Unit Enable */
  204. #define UART_IER_NRZE 0x20 /* NRZ coding Enable */
  205. #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
  206. #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
  207. #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
  208. #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
  209. #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
  210. #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
  211. /*
  212. * Intel MID on-chip HSU (High Speed UART) defined bits
  213. */
  214. #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */
  215. #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */
  216. #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */
  217. #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */
  218. #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */
  219. #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */
  220. #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */
  221. #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */
  222. #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */
  223. #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */
  224. #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
  225. #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */
  226. /*
  227. * These register definitions are for the 16C950
  228. */
  229. #define UART_ASR 0x01 /* Additional Status Register */
  230. #define UART_RFL 0x03 /* Receiver FIFO level */
  231. #define UART_TFL 0x04 /* Transmitter FIFO level */
  232. #define UART_ICR 0x05 /* Index Control Register */
  233. /* The 16950 ICR registers */
  234. #define UART_ACR 0x00 /* Additional Control Register */
  235. #define UART_CPR 0x01 /* Clock Prescalar Register */
  236. #define UART_TCR 0x02 /* Times Clock Register */
  237. #define UART_CKS 0x03 /* Clock Select Register */
  238. #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
  239. #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
  240. #define UART_FCL 0x06 /* Flow Control Level Lower */
  241. #define UART_FCH 0x07 /* Flow Control Level Higher */
  242. #define UART_ID1 0x08 /* ID #1 */
  243. #define UART_ID2 0x09 /* ID #2 */
  244. #define UART_ID3 0x0A /* ID #3 */
  245. #define UART_REV 0x0B /* Revision */
  246. #define UART_CSR 0x0C /* Channel Software Reset */
  247. #define UART_NMR 0x0D /* Nine-bit Mode Register */
  248. #define UART_CTR 0xFF
  249. /*
  250. * The 16C950 Additional Control Register
  251. */
  252. #define UART_ACR_RXDIS 0x01 /* Receiver disable */
  253. #define UART_ACR_TXDIS 0x02 /* Transmitter disable */
  254. #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
  255. #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
  256. #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
  257. #define UART_ACR_ASREN 0x80 /* Additional status enable */
  258. /*
  259. * These definitions are for the RSA-DV II/S card, from
  260. *
  261. * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
  262. */
  263. #define UART_RSA_BASE (-8)
  264. #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
  265. #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
  266. #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
  267. #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
  268. #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
  269. #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
  270. #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
  271. #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
  272. #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
  273. #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
  274. #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
  275. #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
  276. #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
  277. #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
  278. #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
  279. #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
  280. #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
  281. #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
  282. #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
  283. #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
  284. #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
  285. #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
  286. #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
  287. #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
  288. /*
  289. * The RSA DSV/II board has two fixed clock frequencies. One is the
  290. * standard rate, and the other is 8 times faster.
  291. */
  292. #define SERIAL_RSA_BAUD_BASE (921600)
  293. #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
  294. /*
  295. * Extra serial register definitions for the internal UARTs
  296. * in TI OMAP processors.
  297. */
  298. #define UART_OMAP_MDR1 0x08 /* Mode definition register */
  299. #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
  300. #define UART_OMAP_SCR 0x10 /* Supplementary control register */
  301. #define UART_OMAP_SSR 0x11 /* Supplementary status register */
  302. #define UART_OMAP_EBLR 0x12 /* BOF length register */
  303. #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
  304. #define UART_OMAP_MVER 0x14 /* Module version register */
  305. #define UART_OMAP_SYSC 0x15 /* System configuration register */
  306. #define UART_OMAP_SYSS 0x16 /* System status register */
  307. #define UART_OMAP_WER 0x17 /* Wake-up enable register */
  308. /*
  309. * These are the definitions for the MDR1 register
  310. */
  311. #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
  312. #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
  313. #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
  314. #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
  315. #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
  316. #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
  317. #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
  318. #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
  319. /*
  320. * These are definitions for the Exar XR17V35X and XR17(C|D)15X
  321. */
  322. #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
  323. #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
  324. #define UART_EXAR_DVID 0x8d /* Device identification */
  325. #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
  326. #define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */
  327. #define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */
  328. #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
  329. #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
  330. #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
  331. #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
  332. #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
  333. #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
  334. #endif /* _LINUX_SERIAL_REG_H */