spi-nor.h 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. * Synced from Linux v4.19
  5. */
  6. #ifndef __LINUX_MTD_SPI_NOR_H
  7. #define __LINUX_MTD_SPI_NOR_H
  8. #include <linux/bitops.h>
  9. #include <linux/mtd/cfi.h>
  10. #include <linux/mtd/mtd.h>
  11. /*
  12. * Manufacturer IDs
  13. *
  14. * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  15. * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  16. */
  17. #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
  18. #define SNOR_MFR_GIGADEVICE 0xc8
  19. #define SNOR_MFR_INTEL CFI_MFR_INTEL
  20. #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
  21. #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
  22. #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
  23. #define SNOR_MFR_SPANSION CFI_MFR_AMD
  24. #define SNOR_MFR_SST CFI_MFR_SST
  25. #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
  26. /*
  27. * Note on opcode nomenclature: some opcodes have a format like
  28. * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  29. * of I/O lines used for the opcode, address, and data (respectively). The
  30. * FUNCTION has an optional suffix of '4', to represent an opcode which
  31. * requires a 4-byte (32-bit) address.
  32. */
  33. /* Flash opcodes. */
  34. #define SPINOR_OP_WREN 0x06 /* Write enable */
  35. #define SPINOR_OP_RDSR 0x05 /* Read status register */
  36. #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
  37. #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
  38. #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
  39. #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
  40. #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
  41. #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
  42. #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
  43. #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
  44. #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
  45. #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
  46. #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
  47. #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
  48. #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
  49. #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
  50. #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
  51. #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  52. #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
  53. #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
  54. #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
  55. #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
  56. #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
  57. #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
  58. #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
  59. #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
  60. /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  61. #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
  62. #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
  63. #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
  64. #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
  65. #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
  66. #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
  67. #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
  68. #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
  69. #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
  70. #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
  71. #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
  72. #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  73. /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  74. #define SPINOR_OP_READ_1_1_1_DTR 0x0d
  75. #define SPINOR_OP_READ_1_2_2_DTR 0xbd
  76. #define SPINOR_OP_READ_1_4_4_DTR 0xed
  77. #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
  78. #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
  79. #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
  80. /* Used for SST flashes only. */
  81. #define SPINOR_OP_BP 0x02 /* Byte program */
  82. #define SPINOR_OP_WRDI 0x04 /* Write disable */
  83. #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
  84. /* Used for SST26* flashes only. */
  85. #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
  86. #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
  87. /* Used for S3AN flashes only */
  88. #define SPINOR_OP_XSE 0x50 /* Sector erase */
  89. #define SPINOR_OP_XPP 0x82 /* Page program */
  90. #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
  91. #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
  92. #define XSR_RDY BIT(7) /* Ready */
  93. /* Used for Macronix and Winbond flashes. */
  94. #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
  95. #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
  96. /* Used for Spansion flashes only. */
  97. #define SPINOR_OP_BRWR 0x17 /* Bank register write */
  98. #define SPINOR_OP_BRRD 0x16 /* Bank register read */
  99. #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
  100. /* Used for Micron flashes only. */
  101. #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
  102. #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
  103. /* Status Register bits. */
  104. #define SR_WIP BIT(0) /* Write in progress */
  105. #define SR_WEL BIT(1) /* Write enable latch */
  106. /* meaning of other SR_* bits may differ between vendors */
  107. #define SR_BP0 BIT(2) /* Block protect 0 */
  108. #define SR_BP1 BIT(3) /* Block protect 1 */
  109. #define SR_BP2 BIT(4) /* Block protect 2 */
  110. #define SR_TB BIT(5) /* Top/Bottom protect */
  111. #define SR_SRWD BIT(7) /* SR write protect */
  112. /* Spansion/Cypress specific status bits */
  113. #define SR_E_ERR BIT(5)
  114. #define SR_P_ERR BIT(6)
  115. #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
  116. /* Enhanced Volatile Configuration Register bits */
  117. #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
  118. /* Flag Status Register bits */
  119. #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
  120. #define FSR_E_ERR BIT(5) /* Erase operation status */
  121. #define FSR_P_ERR BIT(4) /* Program operation status */
  122. #define FSR_PT_ERR BIT(1) /* Protection error bit */
  123. /* Configuration Register bits. */
  124. #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
  125. /* Status Register 2 bits. */
  126. #define SR2_QUAD_EN_BIT7 BIT(7)
  127. /* Supported SPI protocols */
  128. #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
  129. #define SNOR_PROTO_INST_SHIFT 16
  130. #define SNOR_PROTO_INST(_nbits) \
  131. ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
  132. SNOR_PROTO_INST_MASK)
  133. #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
  134. #define SNOR_PROTO_ADDR_SHIFT 8
  135. #define SNOR_PROTO_ADDR(_nbits) \
  136. ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
  137. SNOR_PROTO_ADDR_MASK)
  138. #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
  139. #define SNOR_PROTO_DATA_SHIFT 0
  140. #define SNOR_PROTO_DATA(_nbits) \
  141. ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
  142. SNOR_PROTO_DATA_MASK)
  143. #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
  144. #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
  145. (SNOR_PROTO_INST(_inst_nbits) | \
  146. SNOR_PROTO_ADDR(_addr_nbits) | \
  147. SNOR_PROTO_DATA(_data_nbits))
  148. #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
  149. (SNOR_PROTO_IS_DTR | \
  150. SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
  151. enum spi_nor_protocol {
  152. SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
  153. SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
  154. SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
  155. SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
  156. SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
  157. SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
  158. SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
  159. SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
  160. SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
  161. SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
  162. SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
  163. SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
  164. SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
  165. SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
  166. };
  167. static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
  168. {
  169. return !!(proto & SNOR_PROTO_IS_DTR);
  170. }
  171. static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
  172. {
  173. return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
  174. SNOR_PROTO_INST_SHIFT;
  175. }
  176. static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
  177. {
  178. return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
  179. SNOR_PROTO_ADDR_SHIFT;
  180. }
  181. static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
  182. {
  183. return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
  184. SNOR_PROTO_DATA_SHIFT;
  185. }
  186. static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
  187. {
  188. return spi_nor_get_protocol_data_nbits(proto);
  189. }
  190. #define SPI_NOR_MAX_CMD_SIZE 8
  191. enum spi_nor_ops {
  192. SPI_NOR_OPS_READ = 0,
  193. SPI_NOR_OPS_WRITE,
  194. SPI_NOR_OPS_ERASE,
  195. SPI_NOR_OPS_LOCK,
  196. SPI_NOR_OPS_UNLOCK,
  197. };
  198. enum spi_nor_option_flags {
  199. SNOR_F_USE_FSR = BIT(0),
  200. SNOR_F_HAS_SR_TB = BIT(1),
  201. SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
  202. SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
  203. SNOR_F_READY_XSR_RDY = BIT(4),
  204. SNOR_F_USE_CLSR = BIT(5),
  205. SNOR_F_BROKEN_RESET = BIT(6),
  206. };
  207. /**
  208. * struct flash_info - Forward declaration of a structure used internally by
  209. * spi_nor_scan()
  210. */
  211. struct flash_info;
  212. /*
  213. * TODO: Remove, once all users of spi_flash interface are moved to MTD
  214. *
  215. * struct spi_flash {
  216. * Defined below (keep this text to enable searching for spi_flash decl)
  217. * }
  218. */
  219. #define spi_flash spi_nor
  220. /**
  221. * struct spi_nor - Structure for defining a the SPI NOR layer
  222. * @mtd: point to a mtd_info structure
  223. * @lock: the lock for the read/write/erase/lock/unlock operations
  224. * @dev: point to a spi device, or a spi nor controller device.
  225. * @info: spi-nor part JDEC MFR id and other info
  226. * @page_size: the page size of the SPI NOR
  227. * @addr_width: number of address bytes
  228. * @erase_opcode: the opcode for erasing a sector
  229. * @read_opcode: the read opcode
  230. * @read_dummy: the dummy needed by the read operation
  231. * @program_opcode: the program opcode
  232. * @bank_read_cmd: Bank read cmd
  233. * @bank_write_cmd: Bank write cmd
  234. * @bank_curr: Current flash bank
  235. * @sst_write_second: used by the SST write operation
  236. * @flags: flag options for the current SPI-NOR (SNOR_F_*)
  237. * @read_proto: the SPI protocol for read operations
  238. * @write_proto: the SPI protocol for write operations
  239. * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
  240. * @cmd_buf: used by the write_reg
  241. * @prepare: [OPTIONAL] do some preparations for the
  242. * read/write/erase/lock/unlock operations
  243. * @unprepare: [OPTIONAL] do some post work after the
  244. * read/write/erase/lock/unlock operations
  245. * @read_reg: [DRIVER-SPECIFIC] read out the register
  246. * @write_reg: [DRIVER-SPECIFIC] write data to the register
  247. * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
  248. * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
  249. * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
  250. * at the offset @offs; if not provided by the driver,
  251. * spi-nor will send the erase opcode via write_reg()
  252. * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
  253. * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
  254. * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
  255. * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
  256. * completely locked
  257. * @priv: the private data
  258. */
  259. struct spi_nor {
  260. struct mtd_info mtd;
  261. struct udevice *dev;
  262. struct spi_slave *spi;
  263. const struct flash_info *info;
  264. u32 page_size;
  265. u8 addr_width;
  266. u8 erase_opcode;
  267. u8 read_opcode;
  268. u8 read_dummy;
  269. u8 program_opcode;
  270. #ifdef CONFIG_SPI_FLASH_BAR
  271. u8 bank_read_cmd;
  272. u8 bank_write_cmd;
  273. u8 bank_curr;
  274. #endif
  275. enum spi_nor_protocol read_proto;
  276. enum spi_nor_protocol write_proto;
  277. enum spi_nor_protocol reg_proto;
  278. bool sst_write_second;
  279. u32 flags;
  280. u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
  281. int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  282. void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  283. int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  284. int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  285. ssize_t (*read)(struct spi_nor *nor, loff_t from,
  286. size_t len, u_char *read_buf);
  287. ssize_t (*write)(struct spi_nor *nor, loff_t to,
  288. size_t len, const u_char *write_buf);
  289. int (*erase)(struct spi_nor *nor, loff_t offs);
  290. int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  291. int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  292. int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  293. int (*quad_enable)(struct spi_nor *nor);
  294. void *priv;
  295. /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
  296. const char *name;
  297. u32 size;
  298. u32 sector_size;
  299. u32 erase_size;
  300. };
  301. static inline void spi_nor_set_flash_node(struct spi_nor *nor,
  302. const struct device_node *np)
  303. {
  304. mtd_set_of_node(&nor->mtd, np);
  305. }
  306. static inline const struct
  307. device_node *spi_nor_get_flash_node(struct spi_nor *nor)
  308. {
  309. return mtd_get_of_node(&nor->mtd);
  310. }
  311. /**
  312. * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
  313. * supported by the SPI controller (bus master).
  314. * @mask: the bitmask listing all the supported hw capabilies
  315. */
  316. struct spi_nor_hwcaps {
  317. u32 mask;
  318. };
  319. /*
  320. *(Fast) Read capabilities.
  321. * MUST be ordered by priority: the higher bit position, the higher priority.
  322. * As a matter of performances, it is relevant to use Octo SPI protocols first,
  323. * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
  324. * (Slow) Read.
  325. */
  326. #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
  327. #define SNOR_HWCAPS_READ BIT(0)
  328. #define SNOR_HWCAPS_READ_FAST BIT(1)
  329. #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
  330. #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
  331. #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
  332. #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
  333. #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
  334. #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
  335. #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
  336. #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
  337. #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
  338. #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
  339. #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
  340. #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
  341. #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
  342. #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
  343. #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
  344. #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
  345. /*
  346. * Page Program capabilities.
  347. * MUST be ordered by priority: the higher bit position, the higher priority.
  348. * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
  349. * legacy SPI 1-1-1 protocol.
  350. * Note that Dual Page Programs are not supported because there is no existing
  351. * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
  352. * implements such commands.
  353. */
  354. #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
  355. #define SNOR_HWCAPS_PP BIT(16)
  356. #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
  357. #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
  358. #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
  359. #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
  360. #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
  361. #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
  362. #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
  363. #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
  364. /**
  365. * spi_nor_scan() - scan the SPI NOR
  366. * @nor: the spi_nor structure
  367. *
  368. * The drivers can use this function to scan the SPI NOR.
  369. * In the scanning, it will try to get all the necessary information to
  370. * fill the mtd_info{} and the spi_nor{}.
  371. *
  372. * Return: 0 for success, others for failure.
  373. */
  374. int spi_nor_scan(struct spi_nor *nor);
  375. #endif