samsung_onenand.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2005-2009 Samsung Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Kyungmin Park <kyungmin.park@samsung.com>
  6. */
  7. #ifndef __SAMSUNG_ONENAND_H__
  8. #define __SAMSUNG_ONENAND_H__
  9. /*
  10. * OneNAND Controller
  11. */
  12. #ifndef __ASSEMBLY__
  13. struct samsung_onenand {
  14. unsigned int mem_cfg; /* 0x0000 */
  15. unsigned char res1[0xc];
  16. unsigned int burst_len; /* 0x0010 */
  17. unsigned char res2[0xc];
  18. unsigned int mem_reset; /* 0x0020 */
  19. unsigned char res3[0xc];
  20. unsigned int int_err_stat; /* 0x0030 */
  21. unsigned char res4[0xc];
  22. unsigned int int_err_mask; /* 0x0040 */
  23. unsigned char res5[0xc];
  24. unsigned int int_err_ack; /* 0x0050 */
  25. unsigned char res6[0xc];
  26. unsigned int ecc_err_stat; /* 0x0060 */
  27. unsigned char res7[0xc];
  28. unsigned int manufact_id; /* 0x0070 */
  29. unsigned char res8[0xc];
  30. unsigned int device_id; /* 0x0080 */
  31. unsigned char res9[0xc];
  32. unsigned int data_buf_size; /* 0x0090 */
  33. unsigned char res10[0xc];
  34. unsigned int boot_buf_size; /* 0x00A0 */
  35. unsigned char res11[0xc];
  36. unsigned int buf_amount; /* 0x00B0 */
  37. unsigned char res12[0xc];
  38. unsigned int tech; /* 0x00C0 */
  39. unsigned char res13[0xc];
  40. unsigned int fba; /* 0x00D0 */
  41. unsigned char res14[0xc];
  42. unsigned int fpa; /* 0x00E0 */
  43. unsigned char res15[0xc];
  44. unsigned int fsa; /* 0x00F0 */
  45. unsigned char res16[0x3c];
  46. unsigned int sync_mode; /* 0x0130 */
  47. unsigned char res17[0xc];
  48. unsigned int trans_spare; /* 0x0140 */
  49. unsigned char res18[0x3c];
  50. unsigned int err_page_addr; /* 0x0180 */
  51. unsigned char res19[0x1c];
  52. unsigned int int_pin_en; /* 0x01A0 */
  53. unsigned char res20[0x1c];
  54. unsigned int acc_clock; /* 0x01C0 */
  55. unsigned char res21[0x1c];
  56. unsigned int err_blk_addr; /* 0x01E0 */
  57. unsigned char res22[0xc];
  58. unsigned int flash_ver_id; /* 0x01F0 */
  59. unsigned char res23[0x6c];
  60. unsigned int watchdog_cnt_low; /* 0x0260 */
  61. unsigned char res24[0xc];
  62. unsigned int watchdog_cnt_hi; /* 0x0270 */
  63. unsigned char res25[0xc];
  64. unsigned int sync_write; /* 0x0280 */
  65. unsigned char res26[0x1c];
  66. unsigned int cold_reset; /* 0x02A0 */
  67. unsigned char res27[0xc];
  68. unsigned int ddp_device; /* 0x02B0 */
  69. unsigned char res28[0xc];
  70. unsigned int multi_plane; /* 0x02C0 */
  71. unsigned char res29[0x1c];
  72. unsigned int trans_mode; /* 0x02E0 */
  73. unsigned char res30[0x1c];
  74. unsigned int ecc_err_stat2; /* 0x0300 */
  75. unsigned char res31[0xc];
  76. unsigned int ecc_err_stat3; /* 0x0310 */
  77. unsigned char res32[0xc];
  78. unsigned int ecc_err_stat4; /* 0x0320 */
  79. unsigned char res33[0x1c];
  80. unsigned int dev_page_size; /* 0x0340 */
  81. unsigned char res34[0x4c];
  82. unsigned int int_mon_status; /* 0x0390 */
  83. };
  84. #endif
  85. #define ONENAND_MEM_RESET_HOT 0x3
  86. #define ONENAND_MEM_RESET_COLD 0x2
  87. #define ONENAND_MEM_RESET_WARM 0x1
  88. #define INT_ERR_ALL 0x3fff
  89. #define CACHE_OP_ERR (1 << 13)
  90. #define RST_CMP (1 << 12)
  91. #define RDY_ACT (1 << 11)
  92. #define INT_ACT (1 << 10)
  93. #define UNSUP_CMD (1 << 9)
  94. #define LOCKED_BLK (1 << 8)
  95. #define BLK_RW_CMP (1 << 7)
  96. #define ERS_CMP (1 << 6)
  97. #define PGM_CMP (1 << 5)
  98. #define LOAD_CMP (1 << 4)
  99. #define ERS_FAIL (1 << 3)
  100. #define PGM_FAIL (1 << 2)
  101. #define INT_TO (1 << 1)
  102. #define LD_FAIL_ECC_ERR (1 << 0)
  103. #define TSRF (1 << 0)
  104. /* common initialize function */
  105. extern void s3c_onenand_init(struct mtd_info *);
  106. extern int s5pc110_chip_probe(struct mtd_info *);
  107. extern int s5pc210_chip_probe(struct mtd_info *);
  108. #endif