onenand_regs.h 6.7 KB

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  1. /*
  2. * linux/include/linux/mtd/onenand_regs.h
  3. *
  4. * OneNAND Register header file
  5. *
  6. * Copyright (C) 2005-2007 Samsung Electronics
  7. * Kyungmin Park <kyungmin.park@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #ifndef __ONENAND_REG_H
  14. #define __ONENAND_REG_H
  15. /* Memory Address Map Translation (Word order) */
  16. #define ONENAND_MEMORY_MAP(x) ((x) << 1)
  17. /*
  18. * External BufferRAM area
  19. */
  20. #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
  21. #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
  22. #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
  23. /*
  24. * OneNAND Registers
  25. */
  26. #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
  27. #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
  28. #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
  29. #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
  30. #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
  31. #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
  32. #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
  33. #define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
  34. #define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
  35. #define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
  36. #define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
  37. #define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
  38. #define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
  39. #define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
  40. #define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
  41. #define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
  42. #define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
  43. #define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
  44. #define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
  45. #define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
  46. #define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
  47. #define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
  48. #define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
  49. #define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
  50. #define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
  51. #define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
  52. #define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
  53. #define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
  54. #define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
  55. #define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
  56. #define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
  57. #define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
  58. #define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
  59. /*
  60. * Device ID Register F001h (R)
  61. */
  62. #define DEVICE_IS_FLEXONENAND (1 << 9)
  63. #define FLEXONENAND_PI_MASK (0x3ff)
  64. #define FLEXONENAND_PI_UNLOCK_SHIFT (14)
  65. #define ONENAND_DEVICE_DENSITY_MASK (0xf)
  66. #define ONENAND_DEVICE_DENSITY_SHIFT (4)
  67. #define ONENAND_DEVICE_IS_DDP (1 << 3)
  68. #define ONENAND_DEVICE_IS_DEMUX (1 << 2)
  69. #define ONENAND_DEVICE_VCC_MASK (0x3)
  70. #define ONENAND_DEVICE_DENSITY_512Mb (0x002)
  71. #define ONENAND_DEVICE_DENSITY_1Gb (0x003)
  72. #define ONENAND_DEVICE_DENSITY_2Gb (0x004)
  73. #define ONENAND_DEVICE_DENSITY_4Gb (0x005)
  74. /*
  75. * Version ID Register F002h (R)
  76. */
  77. #define ONENAND_VERSION_PROCESS_SHIFT (8)
  78. /*
  79. * Technology Register F006h (R)
  80. */
  81. #define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
  82. /*
  83. * Start Address 1 F100h (R/W)
  84. */
  85. #define ONENAND_DDP_SHIFT (15)
  86. #define ONENAND_DDP_CHIP0 (0)
  87. #define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
  88. /*
  89. * Start Address 8 F107h (R/W)
  90. */
  91. #define ONENAND_FPA_MASK (0x7f)
  92. #define ONENAND_FPA_SHIFT (2)
  93. #define ONENAND_FSA_MASK (0x03)
  94. /*
  95. * Start Buffer Register F200h (R/W)
  96. */
  97. #define ONENAND_BSA_MASK (0x03)
  98. #define ONENAND_BSA_SHIFT (8)
  99. #define ONENAND_BSA_BOOTRAM (0 << 2)
  100. #define ONENAND_BSA_DATARAM0 (2 << 2)
  101. #define ONENAND_BSA_DATARAM1 (3 << 2)
  102. #define ONENAND_BSC_MASK (0x07)
  103. /*
  104. * Command Register F220h (R/W)
  105. */
  106. #define ONENAND_CMD_READ (0x00)
  107. #define ONENAND_CMD_READOOB (0x13)
  108. #define ONENAND_CMD_PROG (0x80)
  109. #define ONENAND_CMD_PROGOOB (0x1A)
  110. #define ONENAND_CMD_2X_PROG (0x7D)
  111. #define ONENAND_CMD_2X_CACHE_PROG (0x7F)
  112. #define ONENAND_CMD_UNLOCK (0x23)
  113. #define ONENAND_CMD_LOCK (0x2A)
  114. #define ONENAND_CMD_LOCK_TIGHT (0x2C)
  115. #define ONENAND_CMD_UNLOCK_ALL (0x27)
  116. #define ONENAND_CMD_ERASE (0x94)
  117. #define ONENAND_CMD_MULTIBLOCK_ERASE (0x95)
  118. #define ONENAND_CMD_ERASE_VERIFY (0x71)
  119. #define ONENAND_CMD_RESET (0xF0)
  120. #define ONENAND_CMD_READID (0x90)
  121. #define FLEXONENAND_CMD_RESET (0xF3)
  122. #define FLEXONENAND_CMD_PI_UPDATE (0x05)
  123. #define FLEXONENAND_CMD_PI_ACCESS (0x66)
  124. #define FLEXONENAND_CMD_RECOVER_LSB (0x05)
  125. /* NOTE: Those are not *REAL* commands */
  126. #define ONENAND_CMD_BUFFERRAM (0x1978)
  127. #define FLEXONENAND_CMD_READ_PI (0x1985)
  128. /*
  129. * System Configuration 1 Register F221h (R, R/W)
  130. */
  131. #define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
  132. #define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
  133. #define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
  134. #define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
  135. #define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
  136. #define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
  137. #define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
  138. #define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
  139. #define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
  140. #define ONENAND_SYS_CFG1_BRL_SHIFT (12)
  141. #define ONENAND_SYS_CFG1_BL_32 (4 << 9)
  142. #define ONENAND_SYS_CFG1_BL_16 (3 << 9)
  143. #define ONENAND_SYS_CFG1_BL_8 (2 << 9)
  144. #define ONENAND_SYS_CFG1_BL_4 (1 << 9)
  145. #define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
  146. #define ONENAND_SYS_CFG1_BL_SHIFT (9)
  147. #define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
  148. #define ONENAND_SYS_CFG1_RDY (1 << 7)
  149. #define ONENAND_SYS_CFG1_INT (1 << 6)
  150. #define ONENAND_SYS_CFG1_IOBE (1 << 5)
  151. #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
  152. /*
  153. * Controller Status Register F240h (R)
  154. */
  155. #define ONENAND_CTRL_ONGO (1 << 15)
  156. #define ONENAND_CTRL_LOCK (1 << 14)
  157. #define ONENAND_CTRL_LOAD (1 << 13)
  158. #define ONENAND_CTRL_PROGRAM (1 << 12)
  159. #define ONENAND_CTRL_ERASE (1 << 11)
  160. #define ONENAND_CTRL_ERROR (1 << 10)
  161. #define ONENAND_CTRL_RSTB (1 << 7)
  162. /*
  163. * Interrupt Status Register F241h (R)
  164. */
  165. #define ONENAND_INT_MASTER (1 << 15)
  166. #define ONENAND_INT_READ (1 << 7)
  167. #define ONENAND_INT_WRITE (1 << 6)
  168. #define ONENAND_INT_ERASE (1 << 5)
  169. #define ONENAND_INT_RESET (1 << 4)
  170. #define ONENAND_INT_CLEAR (0 << 0)
  171. /*
  172. * NAND Flash Write Protection Status Register F24Eh (R)
  173. */
  174. #define ONENAND_WP_US (1 << 2)
  175. #define ONENAND_WP_LS (1 << 1)
  176. #define ONENAND_WP_LTS (1 << 0)
  177. /*
  178. * ECC Status Reigser FF00h (R)
  179. */
  180. #define ONENAND_ECC_1BIT (1 << 0)
  181. #define ONENAND_ECC_1BIT_ALL (0x5555)
  182. #define ONENAND_ECC_2BIT (1 << 1)
  183. #define ONENAND_ECC_2BIT_ALL (0xAAAA)
  184. #define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
  185. #define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
  186. #endif /* __ONENAND_REG_H */