fsmc_nand.h 2.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #ifndef __FSMC_NAND_H__
  7. #define __FSMC_NAND_H__
  8. #include <linux/mtd/rawnand.h>
  9. struct fsmc_regs {
  10. u32 ctrl; /* 0x00 */
  11. u8 reserved_1[0x40 - 0x04];
  12. u32 pc; /* 0x40 */
  13. u32 sts; /* 0x44 */
  14. u32 comm; /* 0x48 */
  15. u32 attrib; /* 0x4c */
  16. u32 ioata; /* 0x50 */
  17. u32 ecc1; /* 0x54 */
  18. u32 ecc2; /* 0x58 */
  19. u32 ecc3; /* 0x5c */
  20. u8 reserved_2[0xfe0 - 0x60];
  21. u32 peripid0; /* 0xfe0 */
  22. u32 peripid1; /* 0xfe4 */
  23. u32 peripid2; /* 0xfe8 */
  24. u32 peripid3; /* 0xfec */
  25. u32 pcellid0; /* 0xff0 */
  26. u32 pcellid1; /* 0xff4 */
  27. u32 pcellid2; /* 0xff8 */
  28. u32 pcellid3; /* 0xffc */
  29. };
  30. /* ctrl register definitions */
  31. #define FSMC_WP (1 << 7)
  32. /* pc register definitions */
  33. #define FSMC_RESET (1 << 0)
  34. #define FSMC_WAITON (1 << 1)
  35. #define FSMC_ENABLE (1 << 2)
  36. #define FSMC_DEVTYPE_NAND (1 << 3)
  37. #define FSMC_DEVWID_8 (0 << 4)
  38. #define FSMC_DEVWID_16 (1 << 4)
  39. #define FSMC_ECCEN (1 << 6)
  40. #define FSMC_ECCPLEN_512 (0 << 7)
  41. #define FSMC_ECCPLEN_256 (1 << 7)
  42. #define FSMC_TCLR_1 (1 << 9)
  43. #define FSMC_TAR_1 (1 << 13)
  44. /* sts register definitions */
  45. #define FSMC_CODE_RDY (1 << 15)
  46. /* comm register definitions */
  47. #define FSMC_TSET_0 (0 << 0)
  48. #define FSMC_TWAIT_6 (6 << 8)
  49. #define FSMC_THOLD_4 (4 << 16)
  50. #define FSMC_THIZ_1 (1 << 24)
  51. /* peripid2 register definitions */
  52. #define FSMC_REVISION_MSK (0xf)
  53. #define FSMC_REVISION_SHFT (0x4)
  54. #define FSMC_VER8 0x8
  55. /*
  56. * There are 13 bytes of ecc for every 512 byte block and it has to be read
  57. * consecutively and immediately after the 512 byte data block for hardware to
  58. * generate the error bit offsets
  59. * Managing the ecc bytes in the following way is easier. This way is similar to
  60. * oobfree structure maintained already in u-boot nand driver
  61. */
  62. #define FSMC_MAX_ECCPLACE_ENTRIES 32
  63. struct fsmc_nand_eccplace {
  64. u32 offset;
  65. u32 length;
  66. };
  67. struct fsmc_eccplace {
  68. struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
  69. };
  70. extern int fsmc_nand_init(struct nand_chip *nand);
  71. #endif