immap_qe.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * QUICC Engine (QE) Internal Memory Map.
  4. * The Internal Memory Map for devices with QE on them. This
  5. * is the superset of all QE devices (8360, etc.).
  6. *
  7. * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
  8. * Author: Shlomi Gridih <gridish@freescale.com>
  9. */
  10. #ifndef __IMMAP_QE_H__
  11. #define __IMMAP_QE_H__
  12. #ifdef CONFIG_MPC83xx
  13. #if defined(CONFIG_ARCH_MPC8360)
  14. #define QE_MURAM_SIZE 0xc000UL
  15. #define MAX_QE_RISC 2
  16. #define QE_NUM_OF_SNUM 28
  17. #elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
  18. #define QE_MURAM_SIZE 0x4000UL
  19. #define MAX_QE_RISC 1
  20. #define QE_NUM_OF_SNUM 28
  21. #endif
  22. #endif
  23. #ifdef CONFIG_ARCH_LS1021A
  24. #define QE_MURAM_SIZE 0x6000UL
  25. #define MAX_QE_RISC 1
  26. #define QE_NUM_OF_SNUM 28
  27. #endif
  28. #ifdef CONFIG_PPC
  29. #define QE_IMMR_OFFSET 0x00140000
  30. #else
  31. #define QE_IMMR_OFFSET 0x01400000
  32. #endif
  33. /* QE I-RAM */
  34. typedef struct qe_iram {
  35. u32 iadd; /* I-RAM Address Register */
  36. u32 idata; /* I-RAM Data Register */
  37. u8 res0[0x4];
  38. u32 iready;
  39. u8 res1[0x70];
  40. } __attribute__ ((packed)) qe_iram_t;
  41. /* QE Interrupt Controller */
  42. typedef struct qe_ic {
  43. u32 qicr;
  44. u32 qivec;
  45. u32 qripnr;
  46. u32 qipnr;
  47. u32 qipxcc;
  48. u32 qipycc;
  49. u32 qipwcc;
  50. u32 qipzcc;
  51. u32 qimr;
  52. u32 qrimr;
  53. u32 qicnr;
  54. u8 res0[0x4];
  55. u32 qiprta;
  56. u32 qiprtb;
  57. u8 res1[0x4];
  58. u32 qricr;
  59. u8 res2[0x20];
  60. u32 qhivec;
  61. u8 res3[0x1C];
  62. } __attribute__ ((packed)) qe_ic_t;
  63. /* Communications Processor */
  64. typedef struct cp_qe {
  65. u32 cecr; /* QE command register */
  66. u32 ceccr; /* QE controller configuration register */
  67. u32 cecdr; /* QE command data register */
  68. u8 res0[0xA];
  69. u16 ceter; /* QE timer event register */
  70. u8 res1[0x2];
  71. u16 cetmr; /* QE timers mask register */
  72. u32 cetscr; /* QE time-stamp timer control register */
  73. u32 cetsr1; /* QE time-stamp register 1 */
  74. u32 cetsr2; /* QE time-stamp register 2 */
  75. u8 res2[0x8];
  76. u32 cevter; /* QE virtual tasks event register */
  77. u32 cevtmr; /* QE virtual tasks mask register */
  78. u16 cercr; /* QE RAM control register */
  79. u8 res3[0x2];
  80. u8 res4[0x24];
  81. u16 ceexe1; /* QE external request 1 event register */
  82. u8 res5[0x2];
  83. u16 ceexm1; /* QE external request 1 mask register */
  84. u8 res6[0x2];
  85. u16 ceexe2; /* QE external request 2 event register */
  86. u8 res7[0x2];
  87. u16 ceexm2; /* QE external request 2 mask register */
  88. u8 res8[0x2];
  89. u16 ceexe3; /* QE external request 3 event register */
  90. u8 res9[0x2];
  91. u16 ceexm3; /* QE external request 3 mask register */
  92. u8 res10[0x2];
  93. u16 ceexe4; /* QE external request 4 event register */
  94. u8 res11[0x2];
  95. u16 ceexm4; /* QE external request 4 mask register */
  96. u8 res12[0x2];
  97. u8 res13[0x280];
  98. } __attribute__ ((packed)) cp_qe_t;
  99. /* QE Multiplexer */
  100. typedef struct qe_mux {
  101. u32 cmxgcr; /* CMX general clock route register */
  102. u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
  103. u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
  104. u32 cmxsi1syr; /* CMX SI1 SYNC route register */
  105. u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
  106. u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
  107. u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
  108. u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
  109. u32 cmxupcr; /* CMX UPC clock route register */
  110. u8 res0[0x1C];
  111. } __attribute__ ((packed)) qe_mux_t;
  112. /* QE Timers */
  113. typedef struct qe_timers {
  114. u8 gtcfr1; /* Timer 1 2 global configuration register */
  115. u8 res0[0x3];
  116. u8 gtcfr2; /* Timer 3 4 global configuration register */
  117. u8 res1[0xB];
  118. u16 gtmdr1; /* Timer 1 mode register */
  119. u16 gtmdr2; /* Timer 2 mode register */
  120. u16 gtrfr1; /* Timer 1 reference register */
  121. u16 gtrfr2; /* Timer 2 reference register */
  122. u16 gtcpr1; /* Timer 1 capture register */
  123. u16 gtcpr2; /* Timer 2 capture register */
  124. u16 gtcnr1; /* Timer 1 counter */
  125. u16 gtcnr2; /* Timer 2 counter */
  126. u16 gtmdr3; /* Timer 3 mode register */
  127. u16 gtmdr4; /* Timer 4 mode register */
  128. u16 gtrfr3; /* Timer 3 reference register */
  129. u16 gtrfr4; /* Timer 4 reference register */
  130. u16 gtcpr3; /* Timer 3 capture register */
  131. u16 gtcpr4; /* Timer 4 capture register */
  132. u16 gtcnr3; /* Timer 3 counter */
  133. u16 gtcnr4; /* Timer 4 counter */
  134. u16 gtevr1; /* Timer 1 event register */
  135. u16 gtevr2; /* Timer 2 event register */
  136. u16 gtevr3; /* Timer 3 event register */
  137. u16 gtevr4; /* Timer 4 event register */
  138. u16 gtps; /* Timer 1 prescale register */
  139. u8 res2[0x46];
  140. } __attribute__ ((packed)) qe_timers_t;
  141. /* BRG */
  142. typedef struct qe_brg {
  143. u32 brgc1; /* BRG1 configuration register */
  144. u32 brgc2; /* BRG2 configuration register */
  145. u32 brgc3; /* BRG3 configuration register */
  146. u32 brgc4; /* BRG4 configuration register */
  147. u32 brgc5; /* BRG5 configuration register */
  148. u32 brgc6; /* BRG6 configuration register */
  149. u32 brgc7; /* BRG7 configuration register */
  150. u32 brgc8; /* BRG8 configuration register */
  151. u32 brgc9; /* BRG9 configuration register */
  152. u32 brgc10; /* BRG10 configuration register */
  153. u32 brgc11; /* BRG11 configuration register */
  154. u32 brgc12; /* BRG12 configuration register */
  155. u32 brgc13; /* BRG13 configuration register */
  156. u32 brgc14; /* BRG14 configuration register */
  157. u32 brgc15; /* BRG15 configuration register */
  158. u32 brgc16; /* BRG16 configuration register */
  159. u8 res0[0x40];
  160. } __attribute__ ((packed)) qe_brg_t;
  161. /* SPI */
  162. typedef struct spi {
  163. u8 res0[0x20];
  164. u32 spmode; /* SPI mode register */
  165. u8 res1[0x2];
  166. u8 spie; /* SPI event register */
  167. u8 res2[0x1];
  168. u8 res3[0x2];
  169. u8 spim; /* SPI mask register */
  170. u8 res4[0x1];
  171. u8 res5[0x1];
  172. u8 spcom; /* SPI command register */
  173. u8 res6[0x2];
  174. u32 spitd; /* SPI transmit data register (cpu mode) */
  175. u32 spird; /* SPI receive data register (cpu mode) */
  176. u8 res7[0x8];
  177. } __attribute__ ((packed)) spi_t;
  178. /* SI */
  179. typedef struct si1 {
  180. u16 siamr1; /* SI1 TDMA mode register */
  181. u16 sibmr1; /* SI1 TDMB mode register */
  182. u16 sicmr1; /* SI1 TDMC mode register */
  183. u16 sidmr1; /* SI1 TDMD mode register */
  184. u8 siglmr1_h; /* SI1 global mode register high */
  185. u8 res0[0x1];
  186. u8 sicmdr1_h; /* SI1 command register high */
  187. u8 res2[0x1];
  188. u8 sistr1_h; /* SI1 status register high */
  189. u8 res3[0x1];
  190. u16 sirsr1_h; /* SI1 RAM shadow address register high */
  191. u8 sitarc1; /* SI1 RAM counter Tx TDMA */
  192. u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
  193. u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
  194. u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
  195. u8 sirarc1; /* SI1 RAM counter Rx TDMA */
  196. u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
  197. u8 sircrc1; /* SI1 RAM counter Rx TDMC */
  198. u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
  199. u8 res4[0x8];
  200. u16 siemr1; /* SI1 TDME mode register 16 bits */
  201. u16 sifmr1; /* SI1 TDMF mode register 16 bits */
  202. u16 sigmr1; /* SI1 TDMG mode register 16 bits */
  203. u16 sihmr1; /* SI1 TDMH mode register 16 bits */
  204. u8 siglmg1_l; /* SI1 global mode register low 8 bits */
  205. u8 res5[0x1];
  206. u8 sicmdr1_l; /* SI1 command register low 8 bits */
  207. u8 res6[0x1];
  208. u8 sistr1_l; /* SI1 status register low 8 bits */
  209. u8 res7[0x1];
  210. u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
  211. u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
  212. u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
  213. u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
  214. u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
  215. u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
  216. u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
  217. u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
  218. u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
  219. u8 res8[0x8];
  220. u32 siml1; /* SI1 multiframe limit register */
  221. u8 siedm1; /* SI1 extended diagnostic mode register */
  222. u8 res9[0xBB];
  223. } __attribute__ ((packed)) si1_t;
  224. /* SI Routing Tables */
  225. typedef struct sir {
  226. u8 tx[0x400];
  227. u8 rx[0x400];
  228. u8 res0[0x800];
  229. } __attribute__ ((packed)) sir_t;
  230. /* USB Controller. */
  231. typedef struct usb_ctlr {
  232. u8 usb_usmod;
  233. u8 usb_usadr;
  234. u8 usb_uscom;
  235. u8 res1[1];
  236. u16 usb_usep1;
  237. u16 usb_usep2;
  238. u16 usb_usep3;
  239. u16 usb_usep4;
  240. u8 res2[4];
  241. u16 usb_usber;
  242. u8 res3[2];
  243. u16 usb_usbmr;
  244. u8 res4[1];
  245. u8 usb_usbs;
  246. u16 usb_ussft;
  247. u8 res5[2];
  248. u16 usb_usfrn;
  249. u8 res6[0x22];
  250. } __attribute__ ((packed)) usb_t;
  251. /* MCC */
  252. typedef struct mcc {
  253. u32 mcce; /* MCC event register */
  254. u32 mccm; /* MCC mask register */
  255. u32 mccf; /* MCC configuration register */
  256. u32 merl; /* MCC emergency request level register */
  257. u8 res0[0xF0];
  258. } __attribute__ ((packed)) mcc_t;
  259. /* QE UCC Slow */
  260. typedef struct ucc_slow {
  261. u32 gumr_l; /* UCCx general mode register (low) */
  262. u32 gumr_h; /* UCCx general mode register (high) */
  263. u16 upsmr; /* UCCx protocol-specific mode register */
  264. u8 res0[0x2];
  265. u16 utodr; /* UCCx transmit on demand register */
  266. u16 udsr; /* UCCx data synchronization register */
  267. u16 ucce; /* UCCx event register */
  268. u8 res1[0x2];
  269. u16 uccm; /* UCCx mask register */
  270. u8 res2[0x1];
  271. u8 uccs; /* UCCx status register */
  272. u8 res3[0x24];
  273. u16 utpt;
  274. u8 guemr; /* UCC general extended mode register */
  275. u8 res4[0x200 - 0x091];
  276. } __attribute__ ((packed)) ucc_slow_t;
  277. typedef struct ucc_mii_mng {
  278. u32 miimcfg; /* MII management configuration reg */
  279. u32 miimcom; /* MII management command reg */
  280. u32 miimadd; /* MII management address reg */
  281. u32 miimcon; /* MII management control reg */
  282. u32 miimstat; /* MII management status reg */
  283. u32 miimind; /* MII management indication reg */
  284. u32 ifctl; /* interface control reg */
  285. u32 ifstat; /* interface statux reg */
  286. } __attribute__ ((packed))uec_mii_t;
  287. typedef struct ucc_ethernet {
  288. u32 maccfg1; /* mac configuration reg. 1 */
  289. u32 maccfg2; /* mac configuration reg. 2 */
  290. u32 ipgifg; /* interframe gap reg. */
  291. u32 hafdup; /* half-duplex reg. */
  292. u8 res1[0x10];
  293. u32 miimcfg; /* MII management configuration reg */
  294. u32 miimcom; /* MII management command reg */
  295. u32 miimadd; /* MII management address reg */
  296. u32 miimcon; /* MII management control reg */
  297. u32 miimstat; /* MII management status reg */
  298. u32 miimind; /* MII management indication reg */
  299. u32 ifctl; /* interface control reg */
  300. u32 ifstat; /* interface statux reg */
  301. u32 macstnaddr1; /* mac station address part 1 reg */
  302. u32 macstnaddr2; /* mac station address part 2 reg */
  303. u8 res2[0x8];
  304. u32 uempr; /* UCC Ethernet Mac parameter reg */
  305. u32 utbipar; /* UCC tbi address reg */
  306. u16 uescr; /* UCC Ethernet statistics control reg */
  307. u8 res3[0x180 - 0x15A];
  308. u32 tx64; /* Total number of frames (including bad
  309. * frames) transmitted that were exactly
  310. * of the minimal length (64 for un tagged,
  311. * 68 for tagged, or with length exactly
  312. * equal to the parameter MINLength */
  313. u32 tx127; /* Total number of frames (including bad
  314. * frames) transmitted that were between
  315. * MINLength (Including FCS length==4)
  316. * and 127 octets */
  317. u32 tx255; /* Total number of frames (including bad
  318. * frames) transmitted that were between
  319. * 128 (Including FCS length==4) and 255
  320. * octets */
  321. u32 rx64; /* Total number of frames received including
  322. * bad frames that were exactly of the
  323. * mninimal length (64 bytes) */
  324. u32 rx127; /* Total number of frames (including bad
  325. * frames) received that were between
  326. * MINLength (Including FCS length==4)
  327. * and 127 octets */
  328. u32 rx255; /* Total number of frames (including
  329. * bad frames) received that were between
  330. * 128 (Including FCS length==4) and 255
  331. * octets */
  332. u32 txok; /* Total number of octets residing in frames
  333. * that where involved in succesfull
  334. * transmission */
  335. u16 txcf; /* Total number of PAUSE control frames
  336. * transmitted by this MAC */
  337. u8 res4[0x2];
  338. u32 tmca; /* Total number of frames that were transmitted
  339. * succesfully with the group address bit set
  340. * that are not broadcast frames */
  341. u32 tbca; /* Total number of frames transmitted
  342. * succesfully that had destination address
  343. * field equal to the broadcast address */
  344. u32 rxfok; /* Total number of frames received OK */
  345. u32 rxbok; /* Total number of octets received OK */
  346. u32 rbyt; /* Total number of octets received including
  347. * octets in bad frames. Must be implemented
  348. * in HW because it includes octets in frames
  349. * that never even reach the UCC */
  350. u32 rmca; /* Total number of frames that were received
  351. * succesfully with the group address bit set
  352. * that are not broadcast frames */
  353. u32 rbca; /* Total number of frames received succesfully
  354. * that had destination address equal to the
  355. * broadcast address */
  356. u32 scar; /* Statistics carry register */
  357. u32 scam; /* Statistics caryy mask register */
  358. u8 res5[0x200 - 0x1c4];
  359. } __attribute__ ((packed)) uec_t;
  360. /* QE UCC Fast */
  361. typedef struct ucc_fast {
  362. u32 gumr; /* UCCx general mode register */
  363. u32 upsmr; /* UCCx protocol-specific mode register */
  364. u16 utodr; /* UCCx transmit on demand register */
  365. u8 res0[0x2];
  366. u16 udsr; /* UCCx data synchronization register */
  367. u8 res1[0x2];
  368. u32 ucce; /* UCCx event register */
  369. u32 uccm; /* UCCx mask register. */
  370. u8 uccs; /* UCCx status register */
  371. u8 res2[0x7];
  372. u32 urfb; /* UCC receive FIFO base */
  373. u16 urfs; /* UCC receive FIFO size */
  374. u8 res3[0x2];
  375. u16 urfet; /* UCC receive FIFO emergency threshold */
  376. u16 urfset; /* UCC receive FIFO special emergency
  377. * threshold */
  378. u32 utfb; /* UCC transmit FIFO base */
  379. u16 utfs; /* UCC transmit FIFO size */
  380. u8 res4[0x2];
  381. u16 utfet; /* UCC transmit FIFO emergency threshold */
  382. u8 res5[0x2];
  383. u16 utftt; /* UCC transmit FIFO transmit threshold */
  384. u8 res6[0x2];
  385. u16 utpt; /* UCC transmit polling timer */
  386. u8 res7[0x2];
  387. u32 urtry; /* UCC retry counter register */
  388. u8 res8[0x4C];
  389. u8 guemr; /* UCC general extended mode register */
  390. u8 res9[0x100 - 0x091];
  391. uec_t ucc_eth;
  392. } __attribute__ ((packed)) ucc_fast_t;
  393. /* QE UCC */
  394. typedef struct ucc_common {
  395. u8 res1[0x90];
  396. u8 guemr;
  397. u8 res2[0x200 - 0x091];
  398. } __attribute__ ((packed)) ucc_common_t;
  399. typedef struct ucc {
  400. union {
  401. ucc_slow_t slow;
  402. ucc_fast_t fast;
  403. ucc_common_t common;
  404. };
  405. } __attribute__ ((packed)) ucc_t;
  406. /* MultiPHY UTOPIA POS Controllers (UPC) */
  407. typedef struct upc {
  408. u32 upgcr; /* UTOPIA/POS general configuration register */
  409. u32 uplpa; /* UTOPIA/POS last PHY address */
  410. u32 uphec; /* ATM HEC register */
  411. u32 upuc; /* UTOPIA/POS UCC configuration */
  412. u32 updc1; /* UTOPIA/POS device 1 configuration */
  413. u32 updc2; /* UTOPIA/POS device 2 configuration */
  414. u32 updc3; /* UTOPIA/POS device 3 configuration */
  415. u32 updc4; /* UTOPIA/POS device 4 configuration */
  416. u32 upstpa; /* UTOPIA/POS STPA threshold */
  417. u8 res0[0xC];
  418. u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
  419. u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
  420. u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
  421. u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
  422. u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
  423. u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
  424. u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
  425. u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
  426. u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
  427. u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
  428. u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
  429. u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
  430. u32 upde1; /* UTOPIA/POS device 1 event */
  431. u32 upde2; /* UTOPIA/POS device 2 event */
  432. u32 upde3; /* UTOPIA/POS device 3 event */
  433. u32 upde4; /* UTOPIA/POS device 4 event */
  434. u16 uprp1;
  435. u16 uprp2;
  436. u16 uprp3;
  437. u16 uprp4;
  438. u8 res1[0x8];
  439. u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
  440. u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
  441. u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
  442. u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
  443. u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
  444. u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
  445. u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
  446. u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
  447. u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
  448. u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
  449. u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
  450. u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
  451. u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
  452. u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
  453. u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
  454. u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
  455. u32 uper1; /* Device 1 port enable register */
  456. u32 uper2; /* Device 2 port enable register */
  457. u32 uper3; /* Device 3 port enable register */
  458. u32 uper4; /* Device 4 port enable register */
  459. u8 res2[0x150];
  460. } __attribute__ ((packed)) upc_t;
  461. /* SDMA */
  462. typedef struct sdma {
  463. u32 sdsr; /* Serial DMA status register */
  464. u32 sdmr; /* Serial DMA mode register */
  465. u32 sdtr1; /* SDMA system bus threshold register */
  466. u32 sdtr2; /* SDMA secondary bus threshold register */
  467. u32 sdhy1; /* SDMA system bus hysteresis register */
  468. u32 sdhy2; /* SDMA secondary bus hysteresis register */
  469. u32 sdta1; /* SDMA system bus address register */
  470. u32 sdta2; /* SDMA secondary bus address register */
  471. u32 sdtm1; /* SDMA system bus MSNUM register */
  472. u32 sdtm2; /* SDMA secondary bus MSNUM register */
  473. u8 res0[0x10];
  474. u32 sdaqr; /* SDMA address bus qualify register */
  475. u32 sdaqmr; /* SDMA address bus qualify mask register */
  476. u8 res1[0x4];
  477. u32 sdwbcr; /* SDMA CAM entries base register */
  478. u8 res2[0x38];
  479. } __attribute__ ((packed)) sdma_t;
  480. /* Debug Space */
  481. typedef struct dbg {
  482. u32 bpdcr; /* Breakpoint debug command register */
  483. u32 bpdsr; /* Breakpoint debug status register */
  484. u32 bpdmr; /* Breakpoint debug mask register */
  485. u32 bprmrr0; /* Breakpoint request mode risc register 0 */
  486. u32 bprmrr1; /* Breakpoint request mode risc register 1 */
  487. u8 res0[0x8];
  488. u32 bprmtr0; /* Breakpoint request mode trb register 0 */
  489. u32 bprmtr1; /* Breakpoint request mode trb register 1 */
  490. u8 res1[0x8];
  491. u32 bprmir; /* Breakpoint request mode immediate register */
  492. u32 bprmsr; /* Breakpoint request mode serial register */
  493. u32 bpemr; /* Breakpoint exit mode register */
  494. u8 res2[0x48];
  495. } __attribute__ ((packed)) dbg_t;
  496. /*
  497. * RISC Special Registers (Trap and Breakpoint). These are described in
  498. * the QE Developer's Handbook.
  499. */
  500. typedef struct rsp {
  501. u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
  502. u8 res0[64];
  503. u32 ibcr0;
  504. u32 ibs0;
  505. u32 ibcnr0;
  506. u8 res1[4];
  507. u32 ibcr1;
  508. u32 ibs1;
  509. u32 ibcnr1;
  510. u32 npcr;
  511. u32 dbcr;
  512. u32 dbar;
  513. u32 dbamr;
  514. u32 dbsr;
  515. u32 dbcnr;
  516. u8 res2[12];
  517. u32 dbdr_h;
  518. u32 dbdr_l;
  519. u32 dbdmr_h;
  520. u32 dbdmr_l;
  521. u32 bsr;
  522. u32 bor;
  523. u32 bior;
  524. u8 res3[4];
  525. u32 iatr[4];
  526. u32 eccr; /* Exception control configuration register */
  527. u32 eicr;
  528. u8 res4[0x100-0xf8];
  529. } __attribute__ ((packed)) rsp_t;
  530. typedef struct qe_immap {
  531. qe_iram_t iram; /* I-RAM */
  532. qe_ic_t ic; /* Interrupt Controller */
  533. cp_qe_t cp; /* Communications Processor */
  534. qe_mux_t qmx; /* QE Multiplexer */
  535. qe_timers_t qet; /* QE Timers */
  536. spi_t spi[0x2]; /* spi */
  537. mcc_t mcc; /* mcc */
  538. qe_brg_t brg; /* brg */
  539. usb_t usb; /* USB */
  540. si1_t si1; /* SI */
  541. u8 res11[0x800];
  542. sir_t sir; /* SI Routing Tables */
  543. ucc_t ucc1; /* ucc1 */
  544. ucc_t ucc3; /* ucc3 */
  545. ucc_t ucc5; /* ucc5 */
  546. ucc_t ucc7; /* ucc7 */
  547. u8 res12[0x600];
  548. upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
  549. ucc_t ucc2; /* ucc2 */
  550. ucc_t ucc4; /* ucc4 */
  551. ucc_t ucc6; /* ucc6 */
  552. ucc_t ucc8; /* ucc8 */
  553. u8 res13[0x600];
  554. upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
  555. sdma_t sdma; /* SDMA */
  556. dbg_t dbg; /* Debug Space */
  557. rsp_t rsp[0x2]; /* RISC Special Registers
  558. * (Trap and Breakpoint) */
  559. u8 res14[0x300];
  560. u8 res15[0x3A00];
  561. u8 res16[0x8000]; /* 0x108000 - 0x110000 */
  562. u8 muram[QE_MURAM_SIZE];
  563. } __attribute__ ((packed)) qe_map_t;
  564. extern qe_map_t *qe_immr;
  565. #endif /* __IMMAP_QE_H__ */