clk-provider.h 5.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
  7. * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
  8. */
  9. #ifndef __LINUX_CLK_PROVIDER_H
  10. #define __LINUX_CLK_PROVIDER_H
  11. #include <clk-uclass.h>
  12. static inline void clk_dm(ulong id, struct clk *clk)
  13. {
  14. if (!IS_ERR(clk))
  15. clk->id = id;
  16. }
  17. /*
  18. * flags used across common struct clk. these flags should only affect the
  19. * top-level framework. custom flags for dealing with hardware specifics
  20. * belong in struct clk_foo
  21. *
  22. * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
  23. */
  24. #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
  25. #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
  26. #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
  27. #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
  28. /* unused */
  29. #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
  30. #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
  31. #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  32. #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
  33. #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
  34. #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
  35. #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
  36. /* parents need enable during gate/ungate, set rate and re-parent */
  37. #define CLK_OPS_PARENT_ENABLE BIT(12)
  38. /* duty cycle call may be forwarded to the parent clock */
  39. #define CLK_DUTY_CYCLE_PARENT BIT(13)
  40. #define CLK_MUX_INDEX_ONE BIT(0)
  41. #define CLK_MUX_INDEX_BIT BIT(1)
  42. #define CLK_MUX_HIWORD_MASK BIT(2)
  43. #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
  44. #define CLK_MUX_ROUND_CLOSEST BIT(4)
  45. struct clk_mux {
  46. struct clk clk;
  47. void __iomem *reg;
  48. u32 *table;
  49. u32 mask;
  50. u8 shift;
  51. u8 flags;
  52. /*
  53. * Fields from struct clk_init_data - this struct has been
  54. * omitted to avoid too deep level of CCF for bootloader
  55. */
  56. const char * const *parent_names;
  57. u8 num_parents;
  58. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  59. u32 io_mux_val;
  60. #endif
  61. };
  62. #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
  63. extern const struct clk_ops clk_mux_ops;
  64. u8 clk_mux_get_parent(struct clk *clk);
  65. struct clk_gate {
  66. struct clk clk;
  67. void __iomem *reg;
  68. u8 bit_idx;
  69. u8 flags;
  70. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  71. u32 io_gate_val;
  72. #endif
  73. };
  74. #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
  75. #define CLK_GATE_SET_TO_DISABLE BIT(0)
  76. #define CLK_GATE_HIWORD_MASK BIT(1)
  77. extern const struct clk_ops clk_gate_ops;
  78. struct clk *clk_register_gate(struct device *dev, const char *name,
  79. const char *parent_name, unsigned long flags,
  80. void __iomem *reg, u8 bit_idx,
  81. u8 clk_gate_flags, spinlock_t *lock);
  82. struct clk_div_table {
  83. unsigned int val;
  84. unsigned int div;
  85. };
  86. struct clk_divider {
  87. struct clk clk;
  88. void __iomem *reg;
  89. u8 shift;
  90. u8 width;
  91. u8 flags;
  92. const struct clk_div_table *table;
  93. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  94. u32 io_divider_val;
  95. #endif
  96. };
  97. #define clk_div_mask(width) ((1 << (width)) - 1)
  98. #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
  99. #define CLK_DIVIDER_ONE_BASED BIT(0)
  100. #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
  101. #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
  102. #define CLK_DIVIDER_HIWORD_MASK BIT(3)
  103. #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
  104. #define CLK_DIVIDER_READ_ONLY BIT(5)
  105. #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
  106. extern const struct clk_ops clk_divider_ops;
  107. unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  108. unsigned int val,
  109. const struct clk_div_table *table,
  110. unsigned long flags, unsigned long width);
  111. struct clk_fixed_factor {
  112. struct clk clk;
  113. unsigned int mult;
  114. unsigned int div;
  115. };
  116. #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
  117. clk)
  118. struct clk_fixed_rate {
  119. struct clk clk;
  120. unsigned long fixed_rate;
  121. };
  122. #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
  123. struct clk_composite {
  124. struct clk clk;
  125. struct clk_ops ops;
  126. struct clk *mux;
  127. struct clk *rate;
  128. struct clk *gate;
  129. const struct clk_ops *mux_ops;
  130. const struct clk_ops *rate_ops;
  131. const struct clk_ops *gate_ops;
  132. };
  133. #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
  134. struct clk *clk_register_composite(struct device *dev, const char *name,
  135. const char * const *parent_names, int num_parents,
  136. struct clk *mux_clk, const struct clk_ops *mux_ops,
  137. struct clk *rate_clk, const struct clk_ops *rate_ops,
  138. struct clk *gate_clk, const struct clk_ops *gate_ops,
  139. unsigned long flags);
  140. int clk_register(struct clk *clk, const char *drv_name, const char *name,
  141. const char *parent_name);
  142. struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  143. const char *parent_name, unsigned long flags,
  144. unsigned int mult, unsigned int div);
  145. struct clk *clk_register_divider(struct device *dev, const char *name,
  146. const char *parent_name, unsigned long flags,
  147. void __iomem *reg, u8 shift, u8 width,
  148. u8 clk_divider_flags);
  149. struct clk *clk_register_mux(struct device *dev, const char *name,
  150. const char * const *parent_names, u8 num_parents,
  151. unsigned long flags,
  152. void __iomem *reg, u8 shift, u8 width,
  153. u8 clk_mux_flags);
  154. const char *clk_hw_get_name(const struct clk *hw);
  155. ulong clk_generic_get_rate(struct clk *clk);
  156. static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
  157. {
  158. return (struct clk *)dev_get_uclass_priv(dev);
  159. }
  160. #endif /* __LINUX_CLK_PROVIDER_H */