lattice.h 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Porting to U-Boot:
  4. *
  5. * (C) Copyright 2010
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  7. *
  8. * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
  9. *
  10. * Lattice Semiconductor Corp. Copyright 2009
  11. */
  12. #ifndef _VME_OPCODE_H
  13. #define _VME_OPCODE_H
  14. #define VME_VERSION_NUMBER "12.1"
  15. /* Maximum declarations. */
  16. #define VMEHEXMAX 60000L /* The hex file is split 60K per file. */
  17. #define SCANMAX 64000L /* The maximum SDR/SIR burst. */
  18. /*
  19. *
  20. * Supported JTAG state transitions.
  21. *
  22. */
  23. #define RESET 0x00
  24. #define IDLE 0x01
  25. #define IRPAUSE 0x02
  26. #define DRPAUSE 0x03
  27. #define SHIFTIR 0x04
  28. #define SHIFTDR 0x05
  29. /* 11/15/05 Nguyen changed to support DRCAPTURE*/
  30. #define DRCAPTURE 0x06
  31. /*
  32. * Flow control register bit definitions. A set bit indicates
  33. * that the register currently exhibits the corresponding mode.
  34. */
  35. #define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */
  36. #define CASCADE 0x0002 /* Currently splitting large SDR. */
  37. #define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */
  38. #define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */
  39. #define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */
  40. #define VERIFYUES 0x0200 /* Continue if fail is in effect. */
  41. /*
  42. * DataType register bit definitions. A set bit indicates
  43. * that the register currently holds the corresponding type of data.
  44. */
  45. #define EXPRESS 0x0001 /* Simultaneous program and verify. */
  46. #define SIR_DATA 0x0002 /* SIR is the active SVF command. */
  47. #define SDR_DATA 0x0004 /* SDR is the active SVF command. */
  48. #define COMPRESS 0x0008 /* Data is compressed. */
  49. #define TDI_DATA 0x0010 /* TDI data is present. */
  50. #define TDO_DATA 0x0020 /* TDO data is present. */
  51. #define MASK_DATA 0x0040 /* MASK data is present. */
  52. #define HEAP_IN 0x0080 /* Data is from the heap. */
  53. #define LHEAP_IN 0x0200 /* Data is from intel data buffer. */
  54. #define VARIABLE 0x0400 /* Data is from a declared variable. */
  55. #define CRC_DATA 0x0800 /* CRC data is pressent. */
  56. #define CMASK_DATA 0x1000 /* CMASK data is pressent. */
  57. #define RMASK_DATA 0x2000 /* RMASK data is pressent. */
  58. #define READ_DATA 0x4000 /* READ data is pressent. */
  59. #define DMASK_DATA 0x8000 /* DMASK data is pressent. */
  60. /*
  61. *
  62. * Pin opcodes.
  63. *
  64. */
  65. #define signalENABLE 0x1C /* ispENABLE pin. */
  66. #define signalTMS 0x1D /* TMS pin. */
  67. #define signalTCK 0x1E /* TCK pin. */
  68. #define signalTDI 0x1F /* TDI pin. */
  69. #define signalTRST 0x20 /* TRST pin. */
  70. /*
  71. *
  72. * Supported vendors.
  73. *
  74. */
  75. #define VENDOR 0x56
  76. #define LATTICE 0x01
  77. #define ALTERA 0x02
  78. #define XILINX 0x03
  79. /*
  80. * Opcode definitions.
  81. *
  82. * Note: opcodes must be unique.
  83. */
  84. #define ENDDATA 0x00 /* The end of the current SDR data stream. */
  85. #define RUNTEST 0x01 /* The duration to stay at the stable state. */
  86. #define ENDDR 0x02 /* The stable state after SDR. */
  87. #define ENDIR 0x03 /* The stable state after SIR. */
  88. #define ENDSTATE 0x04 /* The stable state after RUNTEST. */
  89. #define TRST 0x05 /* Assert the TRST pin. */
  90. #define HIR 0x06 /*
  91. * The sum of the IR bits of the
  92. * leading devices.
  93. */
  94. #define TIR 0x07 /*
  95. * The sum of the IR bits of the trailing
  96. * devices.
  97. */
  98. #define HDR 0x08 /* The number of leading devices. */
  99. #define TDR 0x09 /* The number of trailing devices. */
  100. #define ispEN 0x0A /* Assert the ispEN pin. */
  101. #define FREQUENCY 0x0B /*
  102. * The maximum clock rate to run the JTAG state
  103. * machine.
  104. */
  105. #define STATE 0x10 /* Move to the next stable state. */
  106. #define SIR 0x11 /* The instruction stream follows. */
  107. #define SDR 0x12 /* The data stream follows. */
  108. #define TDI 0x13 /* The following data stream feeds into
  109. the device. */
  110. #define TDO 0x14 /*
  111. * The following data stream is compared against
  112. * the device.
  113. */
  114. #define MASK 0x15 /* The following data stream is used as mask. */
  115. #define XSDR 0x16 /*
  116. * The following data stream is for simultaneous
  117. * program and verify.
  118. */
  119. #define XTDI 0x17 /* The following data stream is for shift in
  120. * only. It must be stored for the next
  121. * XSDR.
  122. */
  123. #define XTDO 0x18 /*
  124. * There is not data stream. The data stream
  125. * was stored from the previous XTDI.
  126. */
  127. #define MEM 0x19 /*
  128. * The maximum memory needed to allocate in
  129. * order hold one row of data.
  130. */
  131. #define WAIT 0x1A /* The duration of delay to observe. */
  132. #define TCK 0x1B /* The number of TCK pulses. */
  133. #define SHR 0x23 /*
  134. * Set the flow control register for
  135. * right shift
  136. */
  137. #define SHL 0x24 /*
  138. * Set the flow control register for left shift.
  139. */
  140. #define HEAP 0x32 /* The memory size needed to hold one loop. */
  141. #define REPEAT 0x33 /* The beginning of the loop. */
  142. #define LEFTPAREN 0x35 /* The beginning of data following the loop. */
  143. #define VAR 0x55 /* Plac holder for loop data. */
  144. #define SEC 0x1C /*
  145. * The delay time in seconds that must be
  146. * observed.
  147. */
  148. #define SMASK 0x1D /* The mask for TDI data. */
  149. #define MAX_WAIT 0x1E /* The absolute maximum wait time. */
  150. #define ON 0x1F /* Assert the targeted pin. */
  151. #define OFF 0x20 /* Dis-assert the targeted pin. */
  152. #define SETFLOW 0x30 /* Change the flow control register. */
  153. #define RESETFLOW 0x31 /* Clear the flow control register. */
  154. #define CRC 0x47 /*
  155. * The following data stream is used for CRC
  156. * calculation.
  157. */
  158. #define CMASK 0x48 /*
  159. * The following data stream is used as mask
  160. * for CRC calculation.
  161. */
  162. #define RMASK 0x49 /*
  163. * The following data stream is used as mask
  164. * for read and save.
  165. */
  166. #define READ 0x50 /*
  167. * The following data stream is used for read
  168. * and save.
  169. */
  170. #define ENDLOOP 0x59 /* The end of the repeat loop. */
  171. #define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */
  172. #define VUES 0x61 /* Support continue if fail. */
  173. #define DMASK 0x62 /*
  174. * The following data stream is used for dynamic
  175. * I/O.
  176. */
  177. #define COMMENT 0x63 /* Support SVF comments in the VME file. */
  178. #define HEADER 0x64 /* Support header in VME file. */
  179. #define FILE_CRC 0x65 /* Support crc-protected VME file. */
  180. #define LCOUNT 0x66 /* Support intelligent programming. */
  181. #define LDELAY 0x67 /* Support intelligent programming. */
  182. #define LSDR 0x68 /* Support intelligent programming. */
  183. #define LHEAP 0x69 /*
  184. * Memory needed to hold intelligent data
  185. * buffer
  186. */
  187. #define CONTINUE 0x70 /* Allow continuation. */
  188. #define LVDS 0x71 /* Support LVDS. */
  189. #define ENDVME 0x7F /* End of the VME file. */
  190. #define ENDFILE 0xFF /* End of file. */
  191. /*
  192. *
  193. * ispVM Embedded Return Codes.
  194. *
  195. */
  196. #define VME_VERIFICATION_FAILURE -1
  197. #define VME_FILE_READ_FAILURE -2
  198. #define VME_VERSION_FAILURE -3
  199. #define VME_INVALID_FILE -4
  200. #define VME_ARGUMENT_FAILURE -5
  201. #define VME_CRC_FAILURE -6
  202. #define g_ucPinTDI 0x01
  203. #define g_ucPinTCK 0x02
  204. #define g_ucPinTMS 0x04
  205. #define g_ucPinENABLE 0x08
  206. #define g_ucPinTRST 0x10
  207. /*
  208. *
  209. * Type definitions.
  210. *
  211. */
  212. /* Support LVDS */
  213. typedef struct {
  214. unsigned short usPositiveIndex;
  215. unsigned short usNegativeIndex;
  216. unsigned char ucUpdate;
  217. } LVDSPair;
  218. typedef enum {
  219. min_lattice_iface_type, /* insert all new types after this */
  220. lattice_jtag_mode, /* jtag/tap */
  221. max_lattice_iface_type /* insert all new types before this */
  222. } Lattice_iface;
  223. typedef enum {
  224. min_lattice_type,
  225. Lattice_XP2, /* Lattice XP2 Family */
  226. max_lattice_type /* insert all new types before this */
  227. } Lattice_Family;
  228. typedef struct {
  229. Lattice_Family family; /* part type */
  230. Lattice_iface iface; /* interface type */
  231. size_t size; /* bytes of data part can accept */
  232. void *iface_fns; /* interface function table */
  233. void *base; /* base interface address */
  234. int cookie; /* implementation specific cookie */
  235. char *desc; /* description string */
  236. } Lattice_desc; /* end, typedef Altera_desc */
  237. /* Board specific implementation specific function types */
  238. typedef void (*Lattice_jtag_init)(void);
  239. typedef void (*Lattice_jtag_set_tdi)(int v);
  240. typedef void (*Lattice_jtag_set_tms)(int v);
  241. typedef void (*Lattice_jtag_set_tck)(int v);
  242. typedef int (*Lattice_jtag_get_tdo)(void);
  243. typedef struct {
  244. Lattice_jtag_init jtag_init;
  245. Lattice_jtag_set_tdi jtag_set_tdi;
  246. Lattice_jtag_set_tms jtag_set_tms;
  247. Lattice_jtag_set_tck jtag_set_tck;
  248. Lattice_jtag_get_tdo jtag_get_tdo;
  249. } lattice_board_specific_func;
  250. void writePort(unsigned char pins, unsigned char value);
  251. unsigned char readPort(void);
  252. void sclock(void);
  253. void ispVMDelay(unsigned short int a_usMicroSecondDelay);
  254. void calibration(void);
  255. int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
  256. int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
  257. int lattice_info(Lattice_desc *desc);
  258. void ispVMStart(void);
  259. void ispVMEnd(void);
  260. extern void ispVMFreeMem(void);
  261. signed char ispVMCode(void);
  262. void ispVMDelay(unsigned short int a_usMicroSecondDelay);
  263. void ispVMCalculateCRC32(unsigned char a_ucData);
  264. unsigned char GetByte(void);
  265. void writePort(unsigned char pins, unsigned char value);
  266. unsigned char readPort(void);
  267. void sclock(void);
  268. #endif