gt64120.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
  4. * All rights reserved.
  5. * Authors: Carsten Langgaard <carstenl@mips.com>
  6. * Maciej W. Rozycki <macro@mips.com>
  7. * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  8. */
  9. #ifndef _ASM_GT64120_H
  10. #define _ASM_GT64120_H
  11. #define MSK(n) ((1 << (n)) - 1)
  12. /*
  13. * Register offset addresses
  14. */
  15. /* CPU Configuration. */
  16. #define GT_CPU_OFS 0x000
  17. #define GT_MULTI_OFS 0x120
  18. /* CPU Address Decode. */
  19. #define GT_SCS10LD_OFS 0x008
  20. #define GT_SCS10HD_OFS 0x010
  21. #define GT_SCS32LD_OFS 0x018
  22. #define GT_SCS32HD_OFS 0x020
  23. #define GT_CS20LD_OFS 0x028
  24. #define GT_CS20HD_OFS 0x030
  25. #define GT_CS3BOOTLD_OFS 0x038
  26. #define GT_CS3BOOTHD_OFS 0x040
  27. #define GT_PCI0IOLD_OFS 0x048
  28. #define GT_PCI0IOHD_OFS 0x050
  29. #define GT_PCI0M0LD_OFS 0x058
  30. #define GT_PCI0M0HD_OFS 0x060
  31. #define GT_ISD_OFS 0x068
  32. #define GT_PCI0M1LD_OFS 0x080
  33. #define GT_PCI0M1HD_OFS 0x088
  34. #define GT_PCI1IOLD_OFS 0x090
  35. #define GT_PCI1IOHD_OFS 0x098
  36. #define GT_PCI1M0LD_OFS 0x0a0
  37. #define GT_PCI1M0HD_OFS 0x0a8
  38. #define GT_PCI1M1LD_OFS 0x0b0
  39. #define GT_PCI1M1HD_OFS 0x0b8
  40. #define GT_PCI1M1LD_OFS 0x0b0
  41. #define GT_PCI1M1HD_OFS 0x0b8
  42. #define GT_SCS10AR_OFS 0x0d0
  43. #define GT_SCS32AR_OFS 0x0d8
  44. #define GT_CS20R_OFS 0x0e0
  45. #define GT_CS3BOOTR_OFS 0x0e8
  46. #define GT_PCI0IOREMAP_OFS 0x0f0
  47. #define GT_PCI0M0REMAP_OFS 0x0f8
  48. #define GT_PCI0M1REMAP_OFS 0x100
  49. #define GT_PCI1IOREMAP_OFS 0x108
  50. #define GT_PCI1M0REMAP_OFS 0x110
  51. #define GT_PCI1M1REMAP_OFS 0x118
  52. /* CPU Error Report. */
  53. #define GT_CPUERR_ADDRLO_OFS 0x070
  54. #define GT_CPUERR_ADDRHI_OFS 0x078
  55. #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
  56. #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
  57. #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
  58. /* CPU Sync Barrier. */
  59. #define GT_PCI0SYNC_OFS 0x0c0
  60. #define GT_PCI1SYNC_OFS 0x0c8
  61. /* SDRAM and Device Address Decode. */
  62. #define GT_SCS0LD_OFS 0x400
  63. #define GT_SCS0HD_OFS 0x404
  64. #define GT_SCS1LD_OFS 0x408
  65. #define GT_SCS1HD_OFS 0x40c
  66. #define GT_SCS2LD_OFS 0x410
  67. #define GT_SCS2HD_OFS 0x414
  68. #define GT_SCS3LD_OFS 0x418
  69. #define GT_SCS3HD_OFS 0x41c
  70. #define GT_CS0LD_OFS 0x420
  71. #define GT_CS0HD_OFS 0x424
  72. #define GT_CS1LD_OFS 0x428
  73. #define GT_CS1HD_OFS 0x42c
  74. #define GT_CS2LD_OFS 0x430
  75. #define GT_CS2HD_OFS 0x434
  76. #define GT_CS3LD_OFS 0x438
  77. #define GT_CS3HD_OFS 0x43c
  78. #define GT_BOOTLD_OFS 0x440
  79. #define GT_BOOTHD_OFS 0x444
  80. #define GT_ADERR_OFS 0x470
  81. /* SDRAM Configuration. */
  82. #define GT_SDRAM_CFG_OFS 0x448
  83. #define GT_SDRAM_OPMODE_OFS 0x474
  84. #define GT_SDRAM_BM_OFS 0x478
  85. #define GT_SDRAM_ADDRDECODE_OFS 0x47c
  86. /* SDRAM Parameters. */
  87. #define GT_SDRAM_B0_OFS 0x44c
  88. #define GT_SDRAM_B1_OFS 0x450
  89. #define GT_SDRAM_B2_OFS 0x454
  90. #define GT_SDRAM_B3_OFS 0x458
  91. /* Device Parameters. */
  92. #define GT_DEV_B0_OFS 0x45c
  93. #define GT_DEV_B1_OFS 0x460
  94. #define GT_DEV_B2_OFS 0x464
  95. #define GT_DEV_B3_OFS 0x468
  96. #define GT_DEV_BOOT_OFS 0x46c
  97. /* ECC. */
  98. #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
  99. #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
  100. #define GT_ECC_MEM 0x488 /* GT-64120A only */
  101. #define GT_ECC_CALC 0x48c /* GT-64120A only */
  102. #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
  103. /* DMA Record. */
  104. #define GT_DMA0_CNT_OFS 0x800
  105. #define GT_DMA1_CNT_OFS 0x804
  106. #define GT_DMA2_CNT_OFS 0x808
  107. #define GT_DMA3_CNT_OFS 0x80c
  108. #define GT_DMA0_SA_OFS 0x810
  109. #define GT_DMA1_SA_OFS 0x814
  110. #define GT_DMA2_SA_OFS 0x818
  111. #define GT_DMA3_SA_OFS 0x81c
  112. #define GT_DMA0_DA_OFS 0x820
  113. #define GT_DMA1_DA_OFS 0x824
  114. #define GT_DMA2_DA_OFS 0x828
  115. #define GT_DMA3_DA_OFS 0x82c
  116. #define GT_DMA0_NEXT_OFS 0x830
  117. #define GT_DMA1_NEXT_OFS 0x834
  118. #define GT_DMA2_NEXT_OFS 0x838
  119. #define GT_DMA3_NEXT_OFS 0x83c
  120. #define GT_DMA0_CUR_OFS 0x870
  121. #define GT_DMA1_CUR_OFS 0x874
  122. #define GT_DMA2_CUR_OFS 0x878
  123. #define GT_DMA3_CUR_OFS 0x87c
  124. /* DMA Channel Control. */
  125. #define GT_DMA0_CTRL_OFS 0x840
  126. #define GT_DMA1_CTRL_OFS 0x844
  127. #define GT_DMA2_CTRL_OFS 0x848
  128. #define GT_DMA3_CTRL_OFS 0x84c
  129. /* DMA Arbiter. */
  130. #define GT_DMA_ARB_OFS 0x860
  131. /* Timer/Counter. */
  132. #define GT_TC0_OFS 0x850
  133. #define GT_TC1_OFS 0x854
  134. #define GT_TC2_OFS 0x858
  135. #define GT_TC3_OFS 0x85c
  136. #define GT_TC_CONTROL_OFS 0x864
  137. /* PCI Internal. */
  138. #define GT_PCI0_CMD_OFS 0xc00
  139. #define GT_PCI0_TOR_OFS 0xc04
  140. #define GT_PCI0_BS_SCS10_OFS 0xc08
  141. #define GT_PCI0_BS_SCS32_OFS 0xc0c
  142. #define GT_PCI0_BS_CS20_OFS 0xc10
  143. #define GT_PCI0_BS_CS3BT_OFS 0xc14
  144. #define GT_PCI1_IACK_OFS 0xc30
  145. #define GT_PCI0_IACK_OFS 0xc34
  146. #define GT_PCI0_BARE_OFS 0xc3c
  147. #define GT_PCI0_PREFMBR_OFS 0xc40
  148. #define GT_PCI0_SCS10_BAR_OFS 0xc48
  149. #define GT_PCI0_SCS32_BAR_OFS 0xc4c
  150. #define GT_PCI0_CS20_BAR_OFS 0xc50
  151. #define GT_PCI0_CS3BT_BAR_OFS 0xc54
  152. #define GT_PCI0_SSCS10_BAR_OFS 0xc58
  153. #define GT_PCI0_SSCS32_BAR_OFS 0xc5c
  154. #define GT_PCI0_SCS3BT_BAR_OFS 0xc64
  155. #define GT_PCI1_CMD_OFS 0xc80
  156. #define GT_PCI1_TOR_OFS 0xc84
  157. #define GT_PCI1_BS_SCS10_OFS 0xc88
  158. #define GT_PCI1_BS_SCS32_OFS 0xc8c
  159. #define GT_PCI1_BS_CS20_OFS 0xc90
  160. #define GT_PCI1_BS_CS3BT_OFS 0xc94
  161. #define GT_PCI1_BARE_OFS 0xcbc
  162. #define GT_PCI1_PREFMBR_OFS 0xcc0
  163. #define GT_PCI1_SCS10_BAR_OFS 0xcc8
  164. #define GT_PCI1_SCS32_BAR_OFS 0xccc
  165. #define GT_PCI1_CS20_BAR_OFS 0xcd0
  166. #define GT_PCI1_CS3BT_BAR_OFS 0xcd4
  167. #define GT_PCI1_SSCS10_BAR_OFS 0xcd8
  168. #define GT_PCI1_SSCS32_BAR_OFS 0xcdc
  169. #define GT_PCI1_SCS3BT_BAR_OFS 0xce4
  170. #define GT_PCI1_CFGADDR_OFS 0xcf0
  171. #define GT_PCI1_CFGDATA_OFS 0xcf4
  172. #define GT_PCI0_CFGADDR_OFS 0xcf8
  173. #define GT_PCI0_CFGDATA_OFS 0xcfc
  174. /* Interrupts. */
  175. #define GT_INTRCAUSE_OFS 0xc18
  176. #define GT_INTRMASK_OFS 0xc1c
  177. #define GT_PCI0_ICMASK_OFS 0xc24
  178. #define GT_PCI0_SERR0MASK_OFS 0xc28
  179. #define GT_CPU_INTSEL_OFS 0xc70
  180. #define GT_PCI0_INTSEL_OFS 0xc74
  181. #define GT_HINTRCAUSE_OFS 0xc98
  182. #define GT_HINTRMASK_OFS 0xc9c
  183. #define GT_PCI0_HICMASK_OFS 0xca4
  184. #define GT_PCI1_SERR1MASK_OFS 0xca8
  185. /*
  186. * I2O Support Registers
  187. */
  188. #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
  189. #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
  190. #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
  191. #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
  192. #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
  193. #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
  194. #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
  195. #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
  196. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
  197. #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
  198. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
  199. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
  200. #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
  201. #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
  202. #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
  203. #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
  204. #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
  205. #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
  206. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
  207. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
  208. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
  209. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
  210. #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
  211. #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
  212. #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
  213. #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
  214. #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
  215. #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
  216. #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
  217. #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
  218. #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
  219. #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
  220. #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
  221. #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
  222. #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
  223. #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
  224. #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
  225. #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
  226. #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
  227. #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
  228. #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
  229. #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
  230. #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
  231. #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
  232. /*
  233. * Register encodings
  234. */
  235. #define GT_CPU_ENDIAN_SHF 12
  236. #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
  237. #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
  238. #define GT_CPU_WR_SHF 16
  239. #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
  240. #define GT_CPU_WR_BIT GT_CPU_WR_MSK
  241. #define GT_CPU_WR_DXDXDXDX 0
  242. #define GT_CPU_WR_DDDD 1
  243. #define GT_PCI_DCRM_SHF 21
  244. #define GT_PCI_LD_SHF 0
  245. #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
  246. #define GT_PCI_HD_SHF 0
  247. #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
  248. #define GT_PCI_REMAP_SHF 0
  249. #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
  250. #define GT_CFGADDR_CFGEN_SHF 31
  251. #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
  252. #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
  253. #define GT_CFGADDR_BUSNUM_SHF 16
  254. #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
  255. #define GT_CFGADDR_DEVNUM_SHF 11
  256. #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
  257. #define GT_CFGADDR_FUNCNUM_SHF 8
  258. #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
  259. #define GT_CFGADDR_REGNUM_SHF 2
  260. #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
  261. #define GT_SDRAM_BM_ORDER_SHF 2
  262. #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
  263. #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
  264. #define GT_SDRAM_BM_ORDER_SUB 1
  265. #define GT_SDRAM_BM_ORDER_LIN 0
  266. #define GT_SDRAM_BM_RSVD_ALL1 0xffb
  267. #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
  268. #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
  269. #define GT_SDRAM_ADDRDECODE_ADDR_0 0
  270. #define GT_SDRAM_ADDRDECODE_ADDR_1 1
  271. #define GT_SDRAM_ADDRDECODE_ADDR_2 2
  272. #define GT_SDRAM_ADDRDECODE_ADDR_3 3
  273. #define GT_SDRAM_ADDRDECODE_ADDR_4 4
  274. #define GT_SDRAM_ADDRDECODE_ADDR_5 5
  275. #define GT_SDRAM_ADDRDECODE_ADDR_6 6
  276. #define GT_SDRAM_ADDRDECODE_ADDR_7 7
  277. #define GT_SDRAM_B0_CASLAT_SHF 0
  278. #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
  279. #define GT_SDRAM_B0_CASLAT_2 1
  280. #define GT_SDRAM_B0_CASLAT_3 2
  281. #define GT_SDRAM_B0_FTDIS_SHF 2
  282. #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
  283. #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
  284. #define GT_SDRAM_B0_SRASPRCHG_SHF 3
  285. #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
  286. #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
  287. #define GT_SDRAM_B0_SRASPRCHG_2 0
  288. #define GT_SDRAM_B0_SRASPRCHG_3 1
  289. #define GT_SDRAM_B0_B0COMPAB_SHF 4
  290. #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
  291. #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
  292. #define GT_SDRAM_B0_64BITINT_SHF 5
  293. #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
  294. #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
  295. #define GT_SDRAM_B0_64BITINT_2 0
  296. #define GT_SDRAM_B0_64BITINT_4 1
  297. #define GT_SDRAM_B0_BW_SHF 6
  298. #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
  299. #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
  300. #define GT_SDRAM_B0_BW_32 0
  301. #define GT_SDRAM_B0_BW_64 1
  302. #define GT_SDRAM_B0_BLODD_SHF 7
  303. #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
  304. #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
  305. #define GT_SDRAM_B0_PAR_SHF 8
  306. #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
  307. #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
  308. #define GT_SDRAM_B0_BYPASS_SHF 9
  309. #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
  310. #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
  311. #define GT_SDRAM_B0_SRAS2SCAS_SHF 10
  312. #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
  313. #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
  314. #define GT_SDRAM_B0_SRAS2SCAS_2 0
  315. #define GT_SDRAM_B0_SRAS2SCAS_3 1
  316. #define GT_SDRAM_B0_SIZE_SHF 11
  317. #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
  318. #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
  319. #define GT_SDRAM_B0_SIZE_16M 0
  320. #define GT_SDRAM_B0_SIZE_64M 1
  321. #define GT_SDRAM_B0_EXTPAR_SHF 12
  322. #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
  323. #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
  324. #define GT_SDRAM_B0_BLEN_SHF 13
  325. #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
  326. #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
  327. #define GT_SDRAM_B0_BLEN_8 0
  328. #define GT_SDRAM_B0_BLEN_4 1
  329. #define GT_SDRAM_CFG_REFINT_SHF 0
  330. #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
  331. #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
  332. #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
  333. #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
  334. #define GT_SDRAM_CFG_RMW_SHF 15
  335. #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
  336. #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
  337. #define GT_SDRAM_CFG_NONSTAGREF_SHF 16
  338. #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
  339. #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
  340. #define GT_SDRAM_CFG_DUPCNTL_SHF 19
  341. #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
  342. #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
  343. #define GT_SDRAM_CFG_DUPBA_SHF 20
  344. #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
  345. #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
  346. #define GT_SDRAM_CFG_DUPEOT0_SHF 21
  347. #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
  348. #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
  349. #define GT_SDRAM_CFG_DUPEOT1_SHF 22
  350. #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
  351. #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
  352. #define GT_SDRAM_OPMODE_OP_SHF 0
  353. #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
  354. #define GT_SDRAM_OPMODE_OP_NORMAL 0
  355. #define GT_SDRAM_OPMODE_OP_NOP 1
  356. #define GT_SDRAM_OPMODE_OP_PRCHG 2
  357. #define GT_SDRAM_OPMODE_OP_MODE 3
  358. #define GT_SDRAM_OPMODE_OP_CBR 4
  359. #define GT_TC_CONTROL_ENTC0_SHF 0
  360. #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
  361. #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
  362. #define GT_TC_CONTROL_SELTC0_SHF 1
  363. #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
  364. #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
  365. #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
  366. #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \
  367. (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
  368. #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
  369. #define GT_PCI0_BARE_SWSCS32DIS_SHF 1
  370. #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
  371. #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
  372. #define GT_PCI0_BARE_SWSCS10DIS_SHF 2
  373. #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
  374. #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
  375. #define GT_PCI0_BARE_INTIODIS_SHF 3
  376. #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
  377. #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
  378. #define GT_PCI0_BARE_INTMEMDIS_SHF 4
  379. #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
  380. #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
  381. #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
  382. #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
  383. #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
  384. #define GT_PCI0_BARE_CS20DIS_SHF 6
  385. #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
  386. #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
  387. #define GT_PCI0_BARE_SCS32DIS_SHF 7
  388. #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
  389. #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
  390. #define GT_PCI0_BARE_SCS10DIS_SHF 8
  391. #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
  392. #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
  393. #define GT_INTRCAUSE_MASABORT0_SHF 18
  394. #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
  395. #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
  396. #define GT_INTRCAUSE_TARABORT0_SHF 19
  397. #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
  398. #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
  399. #define GT_PCI0_CFGADDR_REGNUM_SHF 2
  400. #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
  401. #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
  402. #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
  403. #define GT_PCI0_CFGADDR_DEVNUM_SHF 11
  404. #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
  405. #define GT_PCI0_CFGADDR_BUSNUM_SHF 16
  406. #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
  407. #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
  408. #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
  409. #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
  410. #define GT_PCI0_CMD_MBYTESWAP_SHF 0
  411. #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
  412. #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
  413. #define GT_PCI0_CMD_MWORDSWAP_SHF 10
  414. #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
  415. #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
  416. #define GT_PCI0_CMD_SBYTESWAP_SHF 16
  417. #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
  418. #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
  419. #define GT_PCI0_CMD_SWORDSWAP_SHF 11
  420. #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
  421. #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
  422. #define GT_INTR_T0EXP_SHF 8
  423. #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
  424. #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
  425. #define GT_INTR_RETRYCTR0_SHF 20
  426. #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
  427. #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
  428. /*
  429. * Misc
  430. */
  431. #define GT_DEF_PCI0_IO_BASE 0x10000000
  432. #define GT_DEF_PCI0_IO_SIZE 0x02000000
  433. #define GT_DEF_PCI0_MEM0_BASE 0x12000000
  434. #define GT_DEF_PCI0_MEM0_SIZE 0x02000000
  435. #define GT_DEF_BASE 0x14000000
  436. #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
  437. #define GT_LATTIM_MIN 6 /* Minimum lat */
  438. #endif /* _ASM_GT64120_H */