gdsys_fpga.h 4.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #ifndef __GDSYS_FPGA_H
  7. #define __GDSYS_FPGA_H
  8. #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
  9. int init_func_fpga(void);
  10. enum {
  11. FPGA_STATE_DONE_FAILED = 1 << 0,
  12. FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  13. FPGA_STATE_PLATFORM = 1 << 2,
  14. };
  15. int get_fpga_state(unsigned dev);
  16. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
  17. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
  18. extern struct ihs_fpga *fpga_ptr[];
  19. #define FPGA_SET_REG(ix, fld, val) \
  20. fpga_set_reg((ix), \
  21. &fpga_ptr[ix]->fld, \
  22. offsetof(struct ihs_fpga, fld), \
  23. val)
  24. #define FPGA_GET_REG(ix, fld, val) \
  25. fpga_get_reg((ix), \
  26. &fpga_ptr[ix]->fld, \
  27. offsetof(struct ihs_fpga, fld), \
  28. val)
  29. #endif
  30. struct ihs_gpio {
  31. u16 read;
  32. u16 clear;
  33. u16 set;
  34. };
  35. struct ihs_i2c {
  36. u16 interrupt_status;
  37. u16 interrupt_enable;
  38. u16 write_mailbox_ext;
  39. u16 write_mailbox;
  40. u16 read_mailbox_ext;
  41. u16 read_mailbox;
  42. };
  43. struct ihs_osd {
  44. u16 version;
  45. u16 features;
  46. u16 control;
  47. u16 xy_size;
  48. u16 xy_scale;
  49. u16 x_pos;
  50. u16 y_pos;
  51. };
  52. struct ihs_mdio {
  53. u16 control;
  54. u16 address_data;
  55. u16 rx_data;
  56. };
  57. struct ihs_io_ep {
  58. u16 transmit_data;
  59. u16 rx_tx_control;
  60. u16 receive_data;
  61. u16 rx_tx_status;
  62. u16 reserved;
  63. u16 device_address;
  64. u16 target_address;
  65. };
  66. #ifdef CONFIG_NEO
  67. struct ihs_fpga {
  68. u16 reflection_low; /* 0x0000 */
  69. u16 versions; /* 0x0002 */
  70. u16 fpga_features; /* 0x0004 */
  71. u16 fpga_version; /* 0x0006 */
  72. u16 reserved_0[8187]; /* 0x0008 */
  73. u16 reflection_high; /* 0x3ffe */
  74. };
  75. #endif
  76. #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
  77. struct ihs_fpga {
  78. u16 reflection_low; /* 0x0000 */
  79. u16 versions; /* 0x0002 */
  80. u16 fpga_version; /* 0x0004 */
  81. u16 fpga_features; /* 0x0006 */
  82. u16 reserved_0[1]; /* 0x0008 */
  83. u16 top_interrupt; /* 0x000a */
  84. u16 reserved_1[2]; /* 0x000c */
  85. u16 control; /* 0x0010 */
  86. u16 extended_control; /* 0x0012 */
  87. struct ihs_gpio gpio; /* 0x0014 */
  88. u16 mpc3w_control; /* 0x001a */
  89. u16 reserved_2[2]; /* 0x001c */
  90. struct ihs_io_ep ep; /* 0x0020 */
  91. u16 reserved_3[9]; /* 0x002e */
  92. struct ihs_i2c i2c0; /* 0x0040 */
  93. u16 reserved_4[10]; /* 0x004c */
  94. u16 mc_int; /* 0x0060 */
  95. u16 mc_int_en; /* 0x0062 */
  96. u16 mc_status; /* 0x0064 */
  97. u16 mc_control; /* 0x0066 */
  98. u16 mc_tx_data; /* 0x0068 */
  99. u16 mc_tx_address; /* 0x006a */
  100. u16 mc_tx_cmd; /* 0x006c */
  101. u16 mc_res; /* 0x006e */
  102. u16 mc_rx_cmd_status; /* 0x0070 */
  103. u16 mc_rx_data; /* 0x0072 */
  104. u16 reserved_5[69]; /* 0x0074 */
  105. u16 reflection_high; /* 0x00fe */
  106. struct ihs_osd osd0; /* 0x0100 */
  107. #ifdef CONFIG_SYS_OSD_DH
  108. u16 reserved_6[57]; /* 0x010e */
  109. struct ihs_osd osd1; /* 0x0180 */
  110. u16 reserved_7[9]; /* 0x018e */
  111. struct ihs_i2c i2c1; /* 0x01a0 */
  112. u16 reserved_8[1834]; /* 0x01ac */
  113. u16 videomem0[2048]; /* 0x1000 */
  114. u16 videomem1[2048]; /* 0x2000 */
  115. #else
  116. u16 reserved_6[889]; /* 0x010e */
  117. u16 videomem0[2048]; /* 0x0800 */
  118. #endif
  119. };
  120. #endif
  121. #ifdef CONFIG_STRIDER_CPU
  122. struct ihs_fpga {
  123. u16 reflection_low; /* 0x0000 */
  124. u16 versions; /* 0x0002 */
  125. u16 fpga_version; /* 0x0004 */
  126. u16 fpga_features; /* 0x0006 */
  127. u16 reserved_0[1]; /* 0x0008 */
  128. u16 top_interrupt; /* 0x000a */
  129. u16 reserved_1[3]; /* 0x000c */
  130. u16 extended_control; /* 0x0012 */
  131. struct ihs_gpio gpio; /* 0x0014 */
  132. u16 mpc3w_control; /* 0x001a */
  133. u16 reserved_2[2]; /* 0x001c */
  134. struct ihs_io_ep ep; /* 0x0020 */
  135. u16 reserved_3[9]; /* 0x002e */
  136. u16 mc_int; /* 0x0040 */
  137. u16 mc_int_en; /* 0x0042 */
  138. u16 mc_status; /* 0x0044 */
  139. u16 mc_control; /* 0x0046 */
  140. u16 mc_tx_data; /* 0x0048 */
  141. u16 mc_tx_address; /* 0x004a */
  142. u16 mc_tx_cmd; /* 0x004c */
  143. u16 mc_res; /* 0x004e */
  144. u16 mc_rx_cmd_status; /* 0x0050 */
  145. u16 mc_rx_data; /* 0x0052 */
  146. u16 reserved_4[62]; /* 0x0054 */
  147. struct ihs_i2c i2c0; /* 0x00d0 */
  148. };
  149. #endif
  150. #ifdef CONFIG_STRIDER_CON
  151. struct ihs_fpga {
  152. u16 reflection_low; /* 0x0000 */
  153. u16 versions; /* 0x0002 */
  154. u16 fpga_version; /* 0x0004 */
  155. u16 fpga_features; /* 0x0006 */
  156. u16 reserved_0[1]; /* 0x0008 */
  157. u16 top_interrupt; /* 0x000a */
  158. u16 reserved_1[4]; /* 0x000c */
  159. struct ihs_gpio gpio; /* 0x0014 */
  160. u16 mpc3w_control; /* 0x001a */
  161. u16 reserved_2[2]; /* 0x001c */
  162. struct ihs_io_ep ep; /* 0x0020 */
  163. u16 reserved_3[9]; /* 0x002e */
  164. struct ihs_i2c i2c0; /* 0x0040 */
  165. u16 reserved_4[10]; /* 0x004c */
  166. u16 mc_int; /* 0x0060 */
  167. u16 mc_int_en; /* 0x0062 */
  168. u16 mc_status; /* 0x0064 */
  169. u16 mc_control; /* 0x0066 */
  170. u16 mc_tx_data; /* 0x0068 */
  171. u16 mc_tx_address; /* 0x006a */
  172. u16 mc_tx_cmd; /* 0x006c */
  173. u16 mc_res; /* 0x006e */
  174. u16 mc_rx_cmd_status; /* 0x0070 */
  175. u16 mc_rx_data; /* 0x0072 */
  176. u16 reserved_5[70]; /* 0x0074 */
  177. struct ihs_osd osd0; /* 0x0100 */
  178. u16 reserved_6[889]; /* 0x010e */
  179. u16 videomem0[2048]; /* 0x0800 */
  180. };
  181. #endif
  182. #endif