fsl_usb.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale USB Controller
  4. *
  5. * Copyright 2013 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef _ASM_FSL_USB_H_
  8. #define _ASM_FSL_USB_H_
  9. #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  10. struct ccsr_usb_port_ctrl {
  11. u32 ctrl;
  12. u32 drvvbuscfg;
  13. u32 pwrfltcfg;
  14. u32 sts;
  15. u8 res_14[0xc];
  16. u32 bistcfg;
  17. u32 biststs;
  18. u32 abistcfg;
  19. u32 abiststs;
  20. u8 res_30[0x10];
  21. u32 xcvrprg;
  22. u32 anaprg;
  23. u32 anadrv;
  24. u32 anasts;
  25. };
  26. struct ccsr_usb_phy {
  27. u32 id;
  28. struct ccsr_usb_port_ctrl port1;
  29. u8 res_50[0xc];
  30. u32 tvr;
  31. u32 pllprg[4];
  32. u8 res_70[0x4];
  33. u32 anaccfg;
  34. u32 dbg;
  35. u8 res_7c[0x4];
  36. struct ccsr_usb_port_ctrl port2;
  37. u8 res_dc[0x334];
  38. };
  39. #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
  40. #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
  41. #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
  42. #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
  43. #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
  44. #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
  45. #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
  46. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  47. #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
  48. #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
  49. #define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
  50. #endif
  51. #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
  52. #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
  53. #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
  54. #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
  55. #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
  56. #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
  57. #define INC_DCNT_THRESHOLD_25MV (0 << 4)
  58. #define INC_DCNT_THRESHOLD_50MV (1 << 4)
  59. #define DEC_DCNT_THRESHOLD_25MV (2 << 4)
  60. #define DEC_DCNT_THRESHOLD_50MV (3 << 4)
  61. #else
  62. struct ccsr_usb_phy {
  63. u32 config1;
  64. u32 config2;
  65. u32 config3;
  66. u32 config4;
  67. u32 config5;
  68. u32 status1;
  69. u32 usb_enable_override;
  70. u8 res[0xe4];
  71. };
  72. #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
  73. #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
  74. #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
  75. #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
  76. #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
  77. #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
  78. #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  79. #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
  80. #endif
  81. /* USB Erratum Checking code */
  82. #if defined(CONFIG_PPC) || defined(CONFIG_ARM)
  83. bool has_dual_phy(void);
  84. bool has_erratum_a005275(void);
  85. bool has_erratum_a006261(void);
  86. bool has_erratum_a007075(void);
  87. bool has_erratum_a007798(void);
  88. bool has_erratum_a007792(void);
  89. bool has_erratum_a005697(void);
  90. bool has_erratum_a004477(void);
  91. bool has_erratum_a008751(void);
  92. bool has_erratum_a010151(void);
  93. #endif
  94. #endif /*_ASM_FSL_USB_H_ */