fsl_sec.h 9.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common internal memory map for some Freescale SoCs
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef __FSL_SEC_H
  8. #define __FSL_SEC_H
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #ifdef CONFIG_SYS_FSL_SEC_LE
  12. #define sec_in32(a) in_le32(a)
  13. #define sec_out32(a, v) out_le32(a, v)
  14. #define sec_in16(a) in_le16(a)
  15. #define sec_clrbits32 clrbits_le32
  16. #define sec_setbits32 setbits_le32
  17. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  18. #define sec_in32(a) in_be32(a)
  19. #define sec_out32(a, v) out_be32(a, v)
  20. #define sec_in16(a) in_be16(a)
  21. #define sec_clrbits32 clrbits_be32
  22. #define sec_setbits32 setbits_be32
  23. #elif defined(CONFIG_SYS_FSL_HAS_SEC)
  24. #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  25. #endif
  26. /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  27. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  28. /* RNG4 TRNG test registers */
  29. struct rng4tst {
  30. #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
  31. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
  32. both entropy shifter and
  33. statistical checker */
  34. #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
  35. entropy shifter and
  36. statistical checker */
  37. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  38. entropy shifter, raw data
  39. in statistical checker */
  40. #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
  41. u32 rtmctl; /* misc. control register */
  42. u32 rtscmisc; /* statistical check misc. register */
  43. u32 rtpkrrng; /* poker range register */
  44. #define RTSDCTL_ENT_DLY_MIN 3200
  45. #define RTSDCTL_ENT_DLY_MAX 12800
  46. union {
  47. u32 rtpkrmax; /* PRGM=1: poker max. limit register */
  48. u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
  49. };
  50. #define RTSDCTL_ENT_DLY_SHIFT 16
  51. #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  52. u32 rtsdctl; /* seed control register */
  53. union {
  54. u32 rtsblim; /* PRGM=1: sparse bit limit register */
  55. u32 rttotsam; /* PRGM=0: total samples register */
  56. };
  57. u32 rtfreqmin; /* frequency count min. limit register */
  58. #define RTFRQMAX_DISABLE (1 << 20)
  59. union {
  60. u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
  61. u32 rtfreqcnt; /* PRGM=0: freq. count register */
  62. };
  63. u32 rsvd1[40];
  64. #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
  65. #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
  66. #define RNG_STATE_HANDLE_MASK \
  67. (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
  68. u32 rdsta; /*RNG DRNG Status Register*/
  69. u32 rsvd2[15];
  70. };
  71. typedef struct ccsr_sec {
  72. u32 res0;
  73. u32 mcfgr; /* Master CFG Register */
  74. u8 res1[0x4];
  75. u32 scfgr;
  76. struct {
  77. u32 ms; /* Job Ring LIODN Register, MS */
  78. u32 ls; /* Job Ring LIODN Register, LS */
  79. } jrliodnr[4];
  80. u8 res2[0x2c];
  81. u32 jrstartr; /* Job Ring Start Register */
  82. struct {
  83. u32 ms; /* RTIC LIODN Register, MS */
  84. u32 ls; /* RTIC LIODN Register, LS */
  85. } rticliodnr[4];
  86. u8 res3[0x1c];
  87. u32 decorr; /* DECO Request Register */
  88. struct {
  89. u32 ms; /* DECO LIODN Register, MS */
  90. u32 ls; /* DECO LIODN Register, LS */
  91. } decoliodnr[16];
  92. u32 dar; /* DECO Avail Register */
  93. u32 drr; /* DECO Reset Register */
  94. u8 res5[0x4d8];
  95. struct rng4tst rng; /* RNG Registers */
  96. u8 res6[0x8a0];
  97. u32 crnr_ms; /* CHA Revision Number Register, MS */
  98. u32 crnr_ls; /* CHA Revision Number Register, LS */
  99. u32 ctpr_ms; /* Compile Time Parameters Register, MS */
  100. u32 ctpr_ls; /* Compile Time Parameters Register, LS */
  101. u8 res7[0x10];
  102. u32 far_ms; /* Fault Address Register, MS */
  103. u32 far_ls; /* Fault Address Register, LS */
  104. u32 falr; /* Fault Address LIODN Register */
  105. u32 fadr; /* Fault Address Detail Register */
  106. u8 res8[0x4];
  107. u32 csta; /* CAAM Status Register */
  108. u32 smpart; /* Secure Memory Partition Parameters */
  109. u32 smvid; /* Secure Memory Version ID */
  110. u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
  111. u32 ccbvid; /* CHA Cluster Block Version ID Register */
  112. u32 chavid_ms; /* CHA Version ID Register, MS */
  113. u32 chavid_ls; /* CHA Version ID Register, LS */
  114. u32 chanum_ms; /* CHA Number Register, MS */
  115. u32 chanum_ls; /* CHA Number Register, LS */
  116. u32 secvid_ms; /* SEC Version ID Register, MS */
  117. u32 secvid_ls; /* SEC Version ID Register, LS */
  118. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  119. u8 res9[0x6f020];
  120. #else
  121. u8 res9[0x6020];
  122. #endif
  123. u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
  124. u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  125. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  126. u8 res10[0x8ffd8];
  127. #else
  128. u8 res10[0x8fd8];
  129. #endif
  130. } ccsr_sec_t;
  131. #define SEC_CTPR_MS_AXI_LIODN 0x08000000
  132. #define SEC_CTPR_MS_QI 0x02000000
  133. #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
  134. #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
  135. #define SEC_RVID_MA 0x0f000000
  136. #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
  137. #define SEC_CHANUM_MS_JRNUM_SHIFT 28
  138. #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
  139. #define SEC_CHANUM_MS_DECONUM_SHIFT 24
  140. #define SEC_SECVID_MS_IPID_MASK 0xffff0000
  141. #define SEC_SECVID_MS_IPID_SHIFT 16
  142. #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
  143. #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
  144. #define SEC_CCBVID_ERA_MASK 0xff000000
  145. #define SEC_CCBVID_ERA_SHIFT 24
  146. #define SEC_SCFGR_RDBENABLE 0x00000400
  147. #define SEC_SCFGR_VIRT_EN 0x00008000
  148. #define SEC_CHAVID_LS_RNG_SHIFT 16
  149. #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
  150. #define CONFIG_JRSTARTR_JR0 0x00000001
  151. struct jr_regs {
  152. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  153. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  154. u32 irba_l;
  155. u32 irba_h;
  156. #else
  157. u32 irba_h;
  158. u32 irba_l;
  159. #endif
  160. u32 rsvd1;
  161. u32 irs;
  162. u32 rsvd2;
  163. u32 irsa;
  164. u32 rsvd3;
  165. u32 irja;
  166. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  167. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  168. u32 orba_l;
  169. u32 orba_h;
  170. #else
  171. u32 orba_h;
  172. u32 orba_l;
  173. #endif
  174. u32 rsvd4;
  175. u32 ors;
  176. u32 rsvd5;
  177. u32 orjr;
  178. u32 rsvd6;
  179. u32 orsf;
  180. u32 rsvd7;
  181. u32 jrsta;
  182. u32 rsvd8;
  183. u32 jrint;
  184. u32 jrcfg0;
  185. u32 jrcfg1;
  186. u32 rsvd9;
  187. u32 irri;
  188. u32 rsvd10;
  189. u32 orwi;
  190. u32 rsvd11;
  191. u32 jrcr;
  192. };
  193. /*
  194. * Scatter Gather Entry - Specifies the the Scatter Gather Format
  195. * related information
  196. */
  197. struct sg_entry {
  198. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  199. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  200. uint32_t addr_lo; /* Memory Address - lo */
  201. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  202. #else
  203. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  204. uint32_t addr_lo; /* Memory Address - lo */
  205. #endif
  206. uint32_t len_flag; /* Length of the data in the frame */
  207. #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
  208. #define SG_ENTRY_EXTENSION_BIT 0x80000000
  209. #define SG_ENTRY_FINAL_BIT 0x40000000
  210. uint32_t bpid_offset;
  211. #define SG_ENTRY_BPID_MASK 0x00FF0000
  212. #define SG_ENTRY_BPID_SHIFT 16
  213. #define SG_ENTRY_OFFSET_MASK 0x00001FFF
  214. #define SG_ENTRY_OFFSET_SHIFT 0
  215. };
  216. #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
  217. #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
  218. /* Job Ring Base Address */
  219. #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
  220. /* Secure Memory Offset varies accross versions */
  221. #define SM_V1_OFFSET 0x0f4
  222. #define SM_V2_OFFSET 0xa00
  223. /*Secure Memory Versioning */
  224. #define SMVID_V2 0x20105
  225. #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
  226. #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
  227. /* CAAM Job Ring 0 Registers */
  228. /* Secure Memory Partition Owner register */
  229. #define SMCSJR_PO (3 << 6)
  230. /* JR Allocation Error */
  231. #define SMCSJR_AERR (3 << 12)
  232. /* Secure memory partition 0 page 0 owner register */
  233. #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
  234. /* Secure memory command register */
  235. #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
  236. /* Secure memory command status register */
  237. #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
  238. /* Secure memory access permissions register */
  239. #define CAAM_SMAPJR(v, jr, y) \
  240. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
  241. /* Secure memory access group 2 register */
  242. #define CAAM_SMAG2JR(v, jr, y) \
  243. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
  244. /* Secure memory access group 1 register */
  245. #define CAAM_SMAG1JR(v, jr, y) \
  246. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
  247. /* Commands and macros for secure memory */
  248. #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
  249. #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
  250. #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
  251. #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
  252. #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
  253. #define CMD_PAGE_ALLOC 0x1
  254. #define CMD_PAGE_DEALLOC 0x2
  255. #define CMD_PART_DEALLOC 0x3
  256. #define CMD_INQUIRY 0x5
  257. #define CMD_COMPLETE (3 << 14)
  258. #define PAGE_AVAILABLE 0
  259. #define PAGE_OWNED (3 << 6)
  260. #define PAGE(x) (x << 16)
  261. #define PARTITION(x) (x << 8)
  262. #define PARTITION_OWNER(x) (0x3 << (x*2))
  263. /* Address of secure 4kbyte pages */
  264. #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
  265. #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
  266. #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
  267. #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
  268. #define JR_MID 2 /* Matches ROM configuration */
  269. #define KS_G1 (1 << JR_MID) /* CAAM only */
  270. #define PERM 0x0000B008 /* Clear on release, lock SMAP
  271. * lock SMAG group 1 Blob */
  272. /* HAB WRAPPED KEY header */
  273. #define WRP_HDR_SIZE 0x08
  274. #define HDR_TAG 0x81
  275. #define HDR_PAR 0x41
  276. /* HAB WRAPPED KEY Data */
  277. #define HAB_MOD 0x66
  278. #define HAB_ALG 0x55
  279. #define HAB_FLG 0x00
  280. /* Partition and Page IDs */
  281. #define PARTITION_1 1
  282. #define PAGE_1 1
  283. #define ERROR_IN_PAGE_ALLOC 1
  284. #define ECONSTRJDESC -1
  285. #endif
  286. /* blob_dek:
  287. * Encapsulates the src in a secure blob and stores it dst
  288. * @src: reference to the plaintext
  289. * @dst: reference to the output adrress
  290. * @len: size in bytes of src
  291. * @return: 0 on success, error otherwise
  292. */
  293. int blob_dek(const u8 *src, u8 *dst, u8 len);
  294. #if defined(CONFIG_ARCH_C29X)
  295. int sec_init_idx(uint8_t);
  296. #endif
  297. int sec_init(void);
  298. #endif
  299. #endif /* __FSL_SEC_H */