fsl_qe.h 9.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #ifndef __QE_H__
  9. #define __QE_H__
  10. #include "common.h"
  11. #ifdef CONFIG_U_QE
  12. #include <linux/immap_qe.h>
  13. #endif
  14. #define QE_NUM_OF_BRGS 16
  15. #define UCC_MAX_NUM 8
  16. #define QE_DATAONLY_BASE 0
  17. #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
  18. /* QE threads SNUM
  19. */
  20. typedef enum qe_snum_state {
  21. QE_SNUM_STATE_USED, /* used */
  22. QE_SNUM_STATE_FREE /* free */
  23. } qe_snum_state_e;
  24. typedef struct qe_snum {
  25. u8 num; /* snum */
  26. qe_snum_state_e state; /* state */
  27. } qe_snum_t;
  28. /* QE RISC allocation
  29. */
  30. #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
  31. #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
  32. #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
  33. #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
  34. #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
  35. QE_RISC_ALLOCATION_RISC2)
  36. #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
  37. QE_RISC_ALLOCATION_RISC2 | \
  38. QE_RISC_ALLOCATION_RISC3 | \
  39. QE_RISC_ALLOCATION_RISC4)
  40. /* QE CECR commands for UCC fast.
  41. */
  42. #define QE_CR_FLG 0x00010000
  43. #define QE_RESET 0x80000000
  44. #define QE_INIT_TX_RX 0x00000000
  45. #define QE_INIT_RX 0x00000001
  46. #define QE_INIT_TX 0x00000002
  47. #define QE_ENTER_HUNT_MODE 0x00000003
  48. #define QE_STOP_TX 0x00000004
  49. #define QE_GRACEFUL_STOP_TX 0x00000005
  50. #define QE_RESTART_TX 0x00000006
  51. #define QE_SWITCH_COMMAND 0x00000007
  52. #define QE_SET_GROUP_ADDRESS 0x00000008
  53. #define QE_INSERT_CELL 0x00000009
  54. #define QE_ATM_TRANSMIT 0x0000000a
  55. #define QE_CELL_POOL_GET 0x0000000b
  56. #define QE_CELL_POOL_PUT 0x0000000c
  57. #define QE_IMA_HOST_CMD 0x0000000d
  58. #define QE_ATM_MULTI_THREAD_INIT 0x00000011
  59. #define QE_ASSIGN_PAGE 0x00000012
  60. #define QE_START_FLOW_CONTROL 0x00000014
  61. #define QE_STOP_FLOW_CONTROL 0x00000015
  62. #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
  63. #define QE_GRACEFUL_STOP_RX 0x0000001a
  64. #define QE_RESTART_RX 0x0000001b
  65. /* QE CECR Sub Block Code - sub block code of QE command.
  66. */
  67. #define QE_CR_SUBBLOCK_INVALID 0x00000000
  68. #define QE_CR_SUBBLOCK_USB 0x03200000
  69. #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
  70. #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
  71. #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
  72. #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
  73. #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
  74. #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
  75. #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
  76. #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
  77. #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
  78. #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
  79. #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
  80. #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
  81. #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
  82. #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
  83. #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
  84. #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
  85. #define QE_CR_SUBBLOCK_MCC1 0x03800000
  86. #define QE_CR_SUBBLOCK_MCC2 0x03a00000
  87. #define QE_CR_SUBBLOCK_MCC3 0x03000000
  88. #define QE_CR_SUBBLOCK_IDMA1 0x02800000
  89. #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
  90. #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
  91. #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
  92. #define QE_CR_SUBBLOCK_HPAC 0x01e00000
  93. #define QE_CR_SUBBLOCK_SPI1 0x01400000
  94. #define QE_CR_SUBBLOCK_SPI2 0x01600000
  95. #define QE_CR_SUBBLOCK_RAND 0x01c00000
  96. #define QE_CR_SUBBLOCK_TIMER 0x01e00000
  97. #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
  98. /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
  99. */
  100. #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
  101. #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
  102. #define QE_CR_PROTOCOL_ATM_POS 0x0A
  103. #define QE_CR_PROTOCOL_ETHERNET 0x0C
  104. #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
  105. #define QE_CR_PROTOCOL_SHIFT 6
  106. /* QE ASSIGN PAGE command
  107. */
  108. #define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
  109. /* Communication Direction.
  110. */
  111. typedef enum comm_dir {
  112. COMM_DIR_NONE = 0,
  113. COMM_DIR_RX = 1,
  114. COMM_DIR_TX = 2,
  115. COMM_DIR_RX_AND_TX = 3
  116. } comm_dir_e;
  117. /* Clocks and BRG's
  118. */
  119. typedef enum qe_clock {
  120. QE_CLK_NONE = 0,
  121. QE_BRG1, /* Baud Rate Generator 1 */
  122. QE_BRG2, /* Baud Rate Generator 2 */
  123. QE_BRG3, /* Baud Rate Generator 3 */
  124. QE_BRG4, /* Baud Rate Generator 4 */
  125. QE_BRG5, /* Baud Rate Generator 5 */
  126. QE_BRG6, /* Baud Rate Generator 6 */
  127. QE_BRG7, /* Baud Rate Generator 7 */
  128. QE_BRG8, /* Baud Rate Generator 8 */
  129. QE_BRG9, /* Baud Rate Generator 9 */
  130. QE_BRG10, /* Baud Rate Generator 10 */
  131. QE_BRG11, /* Baud Rate Generator 11 */
  132. QE_BRG12, /* Baud Rate Generator 12 */
  133. QE_BRG13, /* Baud Rate Generator 13 */
  134. QE_BRG14, /* Baud Rate Generator 14 */
  135. QE_BRG15, /* Baud Rate Generator 15 */
  136. QE_BRG16, /* Baud Rate Generator 16 */
  137. QE_CLK1, /* Clock 1 */
  138. QE_CLK2, /* Clock 2 */
  139. QE_CLK3, /* Clock 3 */
  140. QE_CLK4, /* Clock 4 */
  141. QE_CLK5, /* Clock 5 */
  142. QE_CLK6, /* Clock 6 */
  143. QE_CLK7, /* Clock 7 */
  144. QE_CLK8, /* Clock 8 */
  145. QE_CLK9, /* Clock 9 */
  146. QE_CLK10, /* Clock 10 */
  147. QE_CLK11, /* Clock 11 */
  148. QE_CLK12, /* Clock 12 */
  149. QE_CLK13, /* Clock 13 */
  150. QE_CLK14, /* Clock 14 */
  151. QE_CLK15, /* Clock 15 */
  152. QE_CLK16, /* Clock 16 */
  153. QE_CLK17, /* Clock 17 */
  154. QE_CLK18, /* Clock 18 */
  155. QE_CLK19, /* Clock 19 */
  156. QE_CLK20, /* Clock 20 */
  157. QE_CLK21, /* Clock 21 */
  158. QE_CLK22, /* Clock 22 */
  159. QE_CLK23, /* Clock 23 */
  160. QE_CLK24, /* Clock 24 */
  161. QE_CLK_DUMMY
  162. } qe_clock_e;
  163. /* QE CMXGCR register
  164. */
  165. #define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
  166. #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
  167. /* QE CMXUCR registers
  168. */
  169. #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
  170. /* QE BRG configuration register
  171. */
  172. #define QE_BRGC_ENABLE 0x00010000
  173. #define QE_BRGC_DIVISOR_SHIFT 1
  174. #define QE_BRGC_DIVISOR_MAX 0xFFF
  175. #define QE_BRGC_DIV16 1
  176. /* QE SDMA registers
  177. */
  178. #define QE_SDSR_BER1 0x02000000
  179. #define QE_SDSR_BER2 0x01000000
  180. #define QE_SDMR_GLB_1_MSK 0x80000000
  181. #define QE_SDMR_ADR_SEL 0x20000000
  182. #define QE_SDMR_BER1_MSK 0x02000000
  183. #define QE_SDMR_BER2_MSK 0x01000000
  184. #define QE_SDMR_EB1_MSK 0x00800000
  185. #define QE_SDMR_ER1_MSK 0x00080000
  186. #define QE_SDMR_ER2_MSK 0x00040000
  187. #define QE_SDMR_CEN_MASK 0x0000E000
  188. #define QE_SDMR_SBER_1 0x00000200
  189. #define QE_SDMR_SBER_2 0x00000200
  190. #define QE_SDMR_EB1_PR_MASK 0x000000C0
  191. #define QE_SDMR_ER1_PR 0x00000008
  192. #define QE_SDMR_CEN_SHIFT 13
  193. #define QE_SDMR_EB1_PR_SHIFT 6
  194. #define QE_SDTM_MSNUM_SHIFT 24
  195. #define QE_SDEBCR_BA_MASK 0x01FFFFFF
  196. /* Communication Processor */
  197. #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
  198. #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
  199. #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
  200. /* I-RAM */
  201. #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
  202. #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
  203. #define QE_IRAM_READY 0x80000000
  204. /* Structure that defines QE firmware binary files.
  205. *
  206. * See doc/README.qe_firmware for a description of these fields.
  207. */
  208. struct qe_firmware {
  209. struct qe_header {
  210. u32 length; /* Length of the entire structure, in bytes */
  211. u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
  212. u8 version; /* Version of this layout. First ver is '1' */
  213. } header;
  214. u8 id[62]; /* Null-terminated identifier string */
  215. u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
  216. u8 count; /* Number of microcode[] structures */
  217. struct {
  218. u16 model; /* The SOC model */
  219. u8 major; /* The SOC revision major */
  220. u8 minor; /* The SOC revision minor */
  221. } __attribute__ ((packed)) soc;
  222. u8 padding[4]; /* Reserved, for alignment */
  223. u64 extended_modes; /* Extended modes */
  224. u32 vtraps[8]; /* Virtual trap addresses */
  225. u8 reserved[4]; /* Reserved, for future expansion */
  226. struct qe_microcode {
  227. u8 id[32]; /* Null-terminated identifier */
  228. u32 traps[16]; /* Trap addresses, 0 == ignore */
  229. u32 eccr; /* The value for the ECCR register */
  230. u32 iram_offset;/* Offset into I-RAM for the code */
  231. u32 count; /* Number of 32-bit words of the code */
  232. u32 code_offset;/* Offset of the actual microcode */
  233. u8 major; /* The microcode version major */
  234. u8 minor; /* The microcode version minor */
  235. u8 revision; /* The microcode version revision */
  236. u8 padding; /* Reserved, for alignment */
  237. u8 reserved[4]; /* Reserved, for future expansion */
  238. } __attribute__ ((packed)) microcode[1];
  239. /* All microcode binaries should be located here */
  240. /* CRC32 should be located here, after the microcode binaries */
  241. } __attribute__ ((packed));
  242. struct qe_firmware_info {
  243. char id[64]; /* Firmware name */
  244. u32 vtraps[8]; /* Virtual trap addresses */
  245. u64 extended_modes; /* Extended modes */
  246. };
  247. void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
  248. void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
  249. uint qe_muram_alloc(uint size, uint align);
  250. void *qe_muram_addr(uint offset);
  251. int qe_get_snum(void);
  252. void qe_put_snum(u8 snum);
  253. void qe_init(uint qe_base);
  254. void qe_reset(void);
  255. void qe_assign_page(uint snum, uint para_ram_base);
  256. int qe_set_brg(uint brg, uint rate);
  257. int qe_set_mii_clk_src(int ucc_num);
  258. int qe_upload_firmware(const struct qe_firmware *firmware);
  259. struct qe_firmware_info *qe_get_firmware_info(void);
  260. void ft_qe_setup(void *blob);
  261. void qe_init(uint qe_base);
  262. void qe_reset(void);
  263. #ifdef CONFIG_U_QE
  264. void u_qe_init(void);
  265. int u_qe_upload_firmware(const struct qe_firmware *firmware);
  266. void u_qe_resume(void);
  267. int u_qe_firmware_resume(const struct qe_firmware *firmware,
  268. qe_map_t *qe_immrr);
  269. #endif
  270. #endif /* __QE_H__ */