fsl_mmdc.h 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef FSL_MMDC_H
  6. #define FSL_MMDC_H
  7. /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
  8. #define MPWLGCR_HW_WL_EN (1 << 0)
  9. /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
  10. #define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
  11. /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
  12. #define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
  13. /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
  14. #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
  15. /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
  16. #define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
  17. /* MMDC Core Refresh Control Register (MMDC_MDREF) */
  18. #define MDREF_START_REFRESH (1 << 0)
  19. /* MMDC Core Special Command Register (MDSCR) */
  20. #define CMD_ADDR_MSB_MR_OP(x) (x << 24)
  21. #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
  22. #define MDSCR_DISABLE_CFG_REQ (0 << 15)
  23. #define MDSCR_ENABLE_CON_REQ (1 << 15)
  24. #define MDSCR_CON_ACK (1 << 14)
  25. #define MDSCR_WL_EN (1 << 9)
  26. #define CMD_NORMAL (0 << 4)
  27. #define CMD_PRECHARGE (1 << 4)
  28. #define CMD_AUTO_REFRESH (2 << 4)
  29. #define CMD_LOAD_MODE_REG (3 << 4)
  30. #define CMD_ZQ_CALIBRATION (4 << 4)
  31. #define CMD_PRECHARGE_BANK_OPEN (5 << 4)
  32. #define CMD_MRR (6 << 4)
  33. #define CMD_BANK_ADDR_0 0x0
  34. #define CMD_BANK_ADDR_1 0x1
  35. #define CMD_BANK_ADDR_2 0x2
  36. #define CMD_BANK_ADDR_3 0x3
  37. #define CMD_BANK_ADDR_4 0x4
  38. #define CMD_BANK_ADDR_5 0x5
  39. #define CMD_BANK_ADDR_6 0x6
  40. #define CMD_BANK_ADDR_7 0x7
  41. /* MMDC Core Control Register (MDCTL) */
  42. #define MDCTL_SDE0 (1 << 31)
  43. #define MDCTL_SDE1 (1 << 30)
  44. /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
  45. #define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
  46. /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
  47. #define MMDC_MPMUR0_FRC_MSR (1 << 11)
  48. /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
  49. /* default 64 for a quarter cycle delay */
  50. #define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
  51. /* MMDC Registers */
  52. struct mmdc_regs {
  53. u32 mdctl;
  54. u32 mdpdc;
  55. u32 mdotc;
  56. u32 mdcfg0;
  57. u32 mdcfg1;
  58. u32 mdcfg2;
  59. u32 mdmisc;
  60. u32 mdscr;
  61. u32 mdref;
  62. u32 res1[2];
  63. u32 mdrwd;
  64. u32 mdor;
  65. u32 mdmrr;
  66. u32 mdcfg3lp;
  67. u32 mdmr4;
  68. u32 mdasp;
  69. u32 res2[239];
  70. u32 maarcr;
  71. u32 mapsr;
  72. u32 maexidr0;
  73. u32 maexidr1;
  74. u32 madpcr0;
  75. u32 madpcr1;
  76. u32 madpsr0;
  77. u32 madpsr1;
  78. u32 madpsr2;
  79. u32 madpsr3;
  80. u32 madpsr4;
  81. u32 madpsr5;
  82. u32 masbs0;
  83. u32 masbs1;
  84. u32 res3[2];
  85. u32 magenp;
  86. u32 res4[239];
  87. u32 mpzqhwctrl;
  88. u32 mpzqswctrl;
  89. u32 mpwlgcr;
  90. u32 mpwldectrl0;
  91. u32 mpwldectrl1;
  92. u32 mpwldlst;
  93. u32 mpodtctrl;
  94. u32 mprddqby0dl;
  95. u32 mprddqby1dl;
  96. u32 mprddqby2dl;
  97. u32 mprddqby3dl;
  98. u32 mpwrdqby0dl;
  99. u32 mpwrdqby1dl;
  100. u32 mpwrdqby2dl;
  101. u32 mpwrdqby3dl;
  102. u32 mpdgctrl0;
  103. u32 mpdgctrl1;
  104. u32 mpdgdlst0;
  105. u32 mprddlctl;
  106. u32 mprddlst;
  107. u32 mpwrdlctl;
  108. u32 mpwrdlst;
  109. u32 mpsdctrl;
  110. u32 mpzqlp2ctl;
  111. u32 mprddlhwctl;
  112. u32 mpwrdlhwctl;
  113. u32 mprddlhwst0;
  114. u32 mprddlhwst1;
  115. u32 mpwrdlhwst0;
  116. u32 mpwrdlhwst1;
  117. u32 mpwlhwerr;
  118. u32 mpdghwst0;
  119. u32 mpdghwst1;
  120. u32 mpdghwst2;
  121. u32 mpdghwst3;
  122. u32 mppdcmpr1;
  123. u32 mppdcmpr2;
  124. u32 mpswdar0;
  125. u32 mpswdrdr0;
  126. u32 mpswdrdr1;
  127. u32 mpswdrdr2;
  128. u32 mpswdrdr3;
  129. u32 mpswdrdr4;
  130. u32 mpswdrdr5;
  131. u32 mpswdrdr6;
  132. u32 mpswdrdr7;
  133. u32 mpmur0;
  134. u32 mpwrcadl;
  135. u32 mpdccr;
  136. };
  137. struct fsl_mmdc_info {
  138. u32 mdctl;
  139. u32 mdpdc;
  140. u32 mdotc;
  141. u32 mdcfg0;
  142. u32 mdcfg1;
  143. u32 mdcfg2;
  144. u32 mdmisc;
  145. u32 mdref;
  146. u32 mdrwd;
  147. u32 mdor;
  148. u32 mdasp;
  149. u32 mpodtctrl;
  150. u32 mpzqhwctrl;
  151. u32 mprddlctl;
  152. };
  153. void mmdc_init(const struct fsl_mmdc_info *);
  154. #endif /* FSL_MMDC_H */