fsl_immap.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common internal memory map for some Freescale SoCs
  4. *
  5. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef __FSL_IMMAP_H
  8. #define __FSL_IMMAP_H
  9. /*
  10. * DDR memory controller registers
  11. * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
  12. */
  13. struct ccsr_ddr {
  14. u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
  15. u8 res_04[4];
  16. u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
  17. u8 res_0c[4];
  18. u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
  19. u8 res_14[4];
  20. u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
  21. u8 res_1c[100];
  22. u32 cs0_config; /* Chip Select Configuration */
  23. u32 cs1_config; /* Chip Select Configuration */
  24. u32 cs2_config; /* Chip Select Configuration */
  25. u32 cs3_config; /* Chip Select Configuration */
  26. u8 res_90[48];
  27. u32 cs0_config_2; /* Chip Select Configuration 2 */
  28. u32 cs1_config_2; /* Chip Select Configuration 2 */
  29. u32 cs2_config_2; /* Chip Select Configuration 2 */
  30. u32 cs3_config_2; /* Chip Select Configuration 2 */
  31. u8 res_d0[48];
  32. u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
  33. u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
  34. u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
  35. u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
  36. u32 sdram_cfg; /* SDRAM Control Configuration */
  37. u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
  38. u32 sdram_mode; /* SDRAM Mode Configuration */
  39. u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
  40. u32 sdram_md_cntl; /* SDRAM Mode Control */
  41. u32 sdram_interval; /* SDRAM Interval Configuration */
  42. u32 sdram_data_init; /* SDRAM Data initialization */
  43. u8 res_12c[4];
  44. u32 sdram_clk_cntl; /* SDRAM Clock Control */
  45. u8 res_134[20];
  46. u32 init_addr; /* training init addr */
  47. u32 init_ext_addr; /* training init extended addr */
  48. u8 res_150[16];
  49. u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
  50. u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
  51. u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
  52. u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
  53. u32 ddr_zq_cntl; /* ZQ calibration control*/
  54. u32 ddr_wrlvl_cntl; /* write leveling control*/
  55. u8 reg_178[4];
  56. u32 ddr_sr_cntr; /* self refresh counter */
  57. u32 ddr_sdram_rcw_1; /* Control Words 1 */
  58. u32 ddr_sdram_rcw_2; /* Control Words 2 */
  59. u8 reg_188[8];
  60. u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
  61. u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
  62. u8 res_198[0x1a0-0x198];
  63. u32 ddr_sdram_rcw_3;
  64. u32 ddr_sdram_rcw_4;
  65. u32 ddr_sdram_rcw_5;
  66. u32 ddr_sdram_rcw_6;
  67. u8 res_1b0[0x200-0x1b0];
  68. u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
  69. u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
  70. u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
  71. u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
  72. u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
  73. u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
  74. u8 res_218[0x220-0x218];
  75. u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
  76. u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
  77. u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
  78. u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
  79. u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
  80. u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
  81. u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
  82. u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
  83. u8 res_240[0x250-0x240];
  84. u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
  85. u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
  86. u8 res_258[0x260-0x258];
  87. u32 sdram_cfg_3;
  88. u8 res_264[0x400-0x264];
  89. u32 dq_map_0;
  90. u32 dq_map_1;
  91. u32 dq_map_2;
  92. u32 dq_map_3;
  93. u8 res_410[0xb20-0x410];
  94. u32 ddr_dsr1; /* Debug Status 1 */
  95. u32 ddr_dsr2; /* Debug Status 2 */
  96. u32 ddr_cdr1; /* Control Driver 1 */
  97. u32 ddr_cdr2; /* Control Driver 2 */
  98. u8 res_b30[200];
  99. u32 ip_rev1; /* IP Block Revision 1 */
  100. u32 ip_rev2; /* IP Block Revision 2 */
  101. u32 eor; /* Enhanced Optimization Register */
  102. u8 res_c04[252];
  103. u32 mtcr; /* Memory Test Control Register */
  104. u8 res_d04[28];
  105. u32 mtp1; /* Memory Test Pattern 1 */
  106. u32 mtp2; /* Memory Test Pattern 2 */
  107. u32 mtp3; /* Memory Test Pattern 3 */
  108. u32 mtp4; /* Memory Test Pattern 4 */
  109. u32 mtp5; /* Memory Test Pattern 5 */
  110. u32 mtp6; /* Memory Test Pattern 6 */
  111. u32 mtp7; /* Memory Test Pattern 7 */
  112. u32 mtp8; /* Memory Test Pattern 8 */
  113. u32 mtp9; /* Memory Test Pattern 9 */
  114. u32 mtp10; /* Memory Test Pattern 10 */
  115. u8 res_d48[184];
  116. u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
  117. u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
  118. u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
  119. u8 res_e0c[20];
  120. u32 capture_data_hi; /* Data Path Read Capture High */
  121. u32 capture_data_lo; /* Data Path Read Capture Low */
  122. u32 capture_ecc; /* Data Path Read Capture ECC */
  123. u8 res_e2c[20];
  124. u32 err_detect; /* Error Detect */
  125. u32 err_disable; /* Error Disable */
  126. u32 err_int_en;
  127. u32 capture_attributes; /* Error Attrs Capture */
  128. u32 capture_address; /* Error Addr Capture */
  129. u32 capture_ext_address; /* Error Extended Addr Capture */
  130. u32 err_sbe; /* Single-Bit ECC Error Management */
  131. u8 res_e5c[164];
  132. u32 debug[64]; /* debug_1 to debug_64 */
  133. };
  134. #ifdef CONFIG_SYS_FSL_HAS_CCI400
  135. #define CCI400_CTRLORD_TERM_BARRIER 0x00000008
  136. #define CCI400_CTRLORD_EN_BARRIER 0
  137. #define CCI400_SHAORD_NON_SHAREABLE 0x00000002
  138. #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
  139. #define CCI400_SNOOP_REQ_EN 0x00000001
  140. /* CCI-400 registers */
  141. struct ccsr_cci400 {
  142. u32 ctrl_ord; /* Control Override */
  143. u32 spec_ctrl; /* Speculation Control */
  144. u32 secure_access; /* Secure Access */
  145. u32 status; /* Status */
  146. u32 impr_err; /* Imprecise Error */
  147. u8 res_14[0x100 - 0x14];
  148. u32 pmcr; /* Performance Monitor Control */
  149. u8 res_104[0xfd0 - 0x104];
  150. u32 pid[8]; /* Peripheral ID */
  151. u32 cid[4]; /* Component ID */
  152. struct {
  153. u32 snoop_ctrl; /* Snoop Control */
  154. u32 sha_ord; /* Shareable Override */
  155. u8 res_1008[0x1100 - 0x1008];
  156. u32 rc_qos_ord; /* read channel QoS Value Override */
  157. u32 wc_qos_ord; /* read channel QoS Value Override */
  158. u8 res_1108[0x110c - 0x1108];
  159. u32 qos_ctrl; /* QoS Control */
  160. u32 max_ot; /* Max OT */
  161. u8 res_1114[0x1130 - 0x1114];
  162. u32 target_lat; /* Target Latency */
  163. u32 latency_regu; /* Latency Regulation */
  164. u32 qos_range; /* QoS Range */
  165. u8 res_113c[0x2000 - 0x113c];
  166. } slave[5]; /* Slave Interface */
  167. u8 res_6000[0x9004 - 0x6000];
  168. u32 cycle_counter; /* Cycle counter */
  169. u32 count_ctrl; /* Count Control */
  170. u32 overflow_status; /* Overflow Flag Status */
  171. u8 res_9010[0xa000 - 0x9010];
  172. struct {
  173. u32 event_select; /* Event Select */
  174. u32 event_count; /* Event Count */
  175. u32 counter_ctrl; /* Counter Control */
  176. u32 overflow_status; /* Overflow Flag Status */
  177. u8 res_a010[0xb000 - 0xa010];
  178. } pcounter[4]; /* Performance Counter */
  179. u8 res_e004[0x10000 - 0xe004];
  180. };
  181. #endif
  182. #endif /* __FSL_IMMAP_H */