fsl_ifc.h 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  5. */
  6. #ifndef __FSL_IFC_H
  7. #define __FSL_IFC_H
  8. #ifdef CONFIG_FSL_IFC
  9. #include <config.h>
  10. #include <common.h>
  11. #ifdef CONFIG_ARM
  12. #include <asm/arch/soc.h>
  13. #endif
  14. #define FSL_IFC_V1_1_0 0x01010000
  15. #define FSL_IFC_V2_0_0 0x02000000
  16. #ifdef CONFIG_SYS_FSL_IFC_LE
  17. #define ifc_in32(a) in_le32(a)
  18. #define ifc_out32(a, v) out_le32(a, v)
  19. #define ifc_in16(a) in_le16(a)
  20. #define ifc_out16(a, v) out_le16(a, v)
  21. #elif defined(CONFIG_SYS_FSL_IFC_BE)
  22. #define ifc_in32(a) in_be32(a)
  23. #define ifc_out32(a, v) out_be32(a, v)
  24. #define ifc_in16(a) in_be16(a)
  25. #define ifc_out16(a, v) out_be16(a, v)
  26. #else
  27. #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
  28. #endif
  29. /*
  30. * CSPR - Chip Select Property Register
  31. */
  32. #define CSPR_BA 0xFFFF0000
  33. #define CSPR_BA_SHIFT 16
  34. #define CSPR_PORT_SIZE 0x00000180
  35. #define CSPR_PORT_SIZE_SHIFT 7
  36. /* Port Size 8 bit */
  37. #define CSPR_PORT_SIZE_8 0x00000080
  38. /* Port Size 16 bit */
  39. #define CSPR_PORT_SIZE_16 0x00000100
  40. /* Port Size 32 bit */
  41. #define CSPR_PORT_SIZE_32 0x00000180
  42. /* Write Protect */
  43. #define CSPR_WP 0x00000040
  44. #define CSPR_WP_SHIFT 6
  45. /* Machine Select */
  46. #define CSPR_MSEL 0x00000006
  47. #define CSPR_MSEL_SHIFT 1
  48. /* NOR */
  49. #define CSPR_MSEL_NOR 0x00000000
  50. /* NAND */
  51. #define CSPR_MSEL_NAND 0x00000002
  52. /* GPCM */
  53. #define CSPR_MSEL_GPCM 0x00000004
  54. /* Bank Valid */
  55. #define CSPR_V 0x00000001
  56. #define CSPR_V_SHIFT 0
  57. /* Convert an address into the right format for the CSPR Registers */
  58. #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
  59. /*
  60. * Address Mask Register
  61. */
  62. #define IFC_AMASK_MASK 0xFFFF0000
  63. #define IFC_AMASK_SHIFT 16
  64. #define IFC_AMASK(n) (IFC_AMASK_MASK << \
  65. (LOG2(n) - IFC_AMASK_SHIFT))
  66. /*
  67. * Chip Select Option Register IFC_NAND Machine
  68. */
  69. /* Enable ECC Encoder */
  70. #define CSOR_NAND_ECC_ENC_EN 0x80000000
  71. #define CSOR_NAND_ECC_MODE_MASK 0x30000000
  72. /* 4 bit correction per 520 Byte sector */
  73. #define CSOR_NAND_ECC_MODE_4 0x00000000
  74. /* 8 bit correction per 528 Byte sector */
  75. #define CSOR_NAND_ECC_MODE_8 0x10000000
  76. /* Enable ECC Decoder */
  77. #define CSOR_NAND_ECC_DEC_EN 0x04000000
  78. /* Row Address Length */
  79. #define CSOR_NAND_RAL_MASK 0x01800000
  80. #define CSOR_NAND_RAL_SHIFT 20
  81. #define CSOR_NAND_RAL_1 0x00000000
  82. #define CSOR_NAND_RAL_2 0x00800000
  83. #define CSOR_NAND_RAL_3 0x01000000
  84. #define CSOR_NAND_RAL_4 0x01800000
  85. /* Page Size 512b, 2k, 4k */
  86. #define CSOR_NAND_PGS_MASK 0x00180000
  87. #define CSOR_NAND_PGS_SHIFT 16
  88. #define CSOR_NAND_PGS_512 0x00000000
  89. #define CSOR_NAND_PGS_2K 0x00080000
  90. #define CSOR_NAND_PGS_4K 0x00100000
  91. #define CSOR_NAND_PGS_8K 0x00180000
  92. /* Spare region Size */
  93. #define CSOR_NAND_SPRZ_MASK 0x0000E000
  94. #define CSOR_NAND_SPRZ_SHIFT 13
  95. #define CSOR_NAND_SPRZ_16 0x00000000
  96. #define CSOR_NAND_SPRZ_64 0x00002000
  97. #define CSOR_NAND_SPRZ_128 0x00004000
  98. #define CSOR_NAND_SPRZ_210 0x00006000
  99. #define CSOR_NAND_SPRZ_218 0x00008000
  100. #define CSOR_NAND_SPRZ_224 0x0000A000
  101. #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
  102. /* Pages Per Block */
  103. #define CSOR_NAND_PB_MASK 0x00000700
  104. #define CSOR_NAND_PB_SHIFT 8
  105. #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
  106. /* Time for Read Enable High to Output High Impedance */
  107. #define CSOR_NAND_TRHZ_MASK 0x0000001C
  108. #define CSOR_NAND_TRHZ_SHIFT 2
  109. #define CSOR_NAND_TRHZ_20 0x00000000
  110. #define CSOR_NAND_TRHZ_40 0x00000004
  111. #define CSOR_NAND_TRHZ_60 0x00000008
  112. #define CSOR_NAND_TRHZ_80 0x0000000C
  113. #define CSOR_NAND_TRHZ_100 0x00000010
  114. /* Buffer control disable */
  115. #define CSOR_NAND_BCTLD 0x00000001
  116. /*
  117. * Chip Select Option Register - NOR Flash Mode
  118. */
  119. /* Enable Address shift Mode */
  120. #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
  121. /* Page Read Enable from NOR device */
  122. #define CSOR_NOR_PGRD_EN 0x10000000
  123. /* AVD Toggle Enable during Burst Program */
  124. #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
  125. /* Address Data Multiplexing Shift */
  126. #define CSOR_NOR_ADM_MASK 0x0003E000
  127. #define CSOR_NOR_ADM_SHIFT_SHIFT 13
  128. #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
  129. /* Type of the NOR device hooked */
  130. #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
  131. #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
  132. /* Time for Read Enable High to Output High Impedance */
  133. #define CSOR_NOR_TRHZ_MASK 0x0000001C
  134. #define CSOR_NOR_TRHZ_SHIFT 2
  135. #define CSOR_NOR_TRHZ_20 0x00000000
  136. #define CSOR_NOR_TRHZ_40 0x00000004
  137. #define CSOR_NOR_TRHZ_60 0x00000008
  138. #define CSOR_NOR_TRHZ_80 0x0000000C
  139. #define CSOR_NOR_TRHZ_100 0x00000010
  140. /* Buffer control disable */
  141. #define CSOR_NOR_BCTLD 0x00000001
  142. /*
  143. * Chip Select Option Register - GPCM Mode
  144. */
  145. /* GPCM Mode - Normal */
  146. #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
  147. /* GPCM Mode - GenericASIC */
  148. #define CSOR_GPCM_GPMODE_ASIC 0x80000000
  149. /* Parity Mode odd/even */
  150. #define CSOR_GPCM_PARITY_EVEN 0x40000000
  151. /* Parity Checking enable/disable */
  152. #define CSOR_GPCM_PAR_EN 0x20000000
  153. /* GPCM Timeout Count */
  154. #define CSOR_GPCM_GPTO_MASK 0x0F000000
  155. #define CSOR_GPCM_GPTO_SHIFT 24
  156. #define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
  157. /* GPCM External Access Termination mode for read access */
  158. #define CSOR_GPCM_RGETA_EXT 0x00080000
  159. /* GPCM External Access Termination mode for write access */
  160. #define CSOR_GPCM_WGETA_EXT 0x00040000
  161. /* Address Data Multiplexing Shift */
  162. #define CSOR_GPCM_ADM_MASK 0x0003E000
  163. #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
  164. #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
  165. /* Generic ASIC Parity error indication delay */
  166. #define CSOR_GPCM_GAPERRD_MASK 0x00000180
  167. #define CSOR_GPCM_GAPERRD_SHIFT 7
  168. #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
  169. /* Time for Read Enable High to Output High Impedance */
  170. #define CSOR_GPCM_TRHZ_MASK 0x0000001C
  171. #define CSOR_GPCM_TRHZ_20 0x00000000
  172. #define CSOR_GPCM_TRHZ_40 0x00000004
  173. #define CSOR_GPCM_TRHZ_60 0x00000008
  174. #define CSOR_GPCM_TRHZ_80 0x0000000C
  175. #define CSOR_GPCM_TRHZ_100 0x00000010
  176. /* Buffer control disable */
  177. #define CSOR_GPCM_BCTLD 0x00000001
  178. /*
  179. * Flash Timing Registers (FTIM0 - FTIM2_CSn)
  180. */
  181. /*
  182. * FTIM0 - NAND Flash Mode
  183. */
  184. #define FTIM0_NAND 0x7EFF3F3F
  185. #define FTIM0_NAND_TCCST_SHIFT 25
  186. #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
  187. #define FTIM0_NAND_TWP_SHIFT 16
  188. #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
  189. #define FTIM0_NAND_TWCHT_SHIFT 8
  190. #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
  191. #define FTIM0_NAND_TWH_SHIFT 0
  192. #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
  193. /*
  194. * FTIM1 - NAND Flash Mode
  195. */
  196. #define FTIM1_NAND 0xFFFF3FFF
  197. #define FTIM1_NAND_TADLE_SHIFT 24
  198. #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
  199. #define FTIM1_NAND_TWBE_SHIFT 16
  200. #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
  201. #define FTIM1_NAND_TRR_SHIFT 8
  202. #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
  203. #define FTIM1_NAND_TRP_SHIFT 0
  204. #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
  205. /*
  206. * FTIM2 - NAND Flash Mode
  207. */
  208. #define FTIM2_NAND 0x1FE1F8FF
  209. #define FTIM2_NAND_TRAD_SHIFT 21
  210. #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
  211. #define FTIM2_NAND_TREH_SHIFT 11
  212. #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
  213. #define FTIM2_NAND_TWHRE_SHIFT 0
  214. #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
  215. /*
  216. * FTIM3 - NAND Flash Mode
  217. */
  218. #define FTIM3_NAND 0xFF000000
  219. #define FTIM3_NAND_TWW_SHIFT 24
  220. #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
  221. /*
  222. * FTIM0 - NOR Flash Mode
  223. */
  224. #define FTIM0_NOR 0xF03F3F3F
  225. #define FTIM0_NOR_TACSE_SHIFT 28
  226. #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
  227. #define FTIM0_NOR_TEADC_SHIFT 16
  228. #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
  229. #define FTIM0_NOR_TAVDS_SHIFT 8
  230. #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
  231. #define FTIM0_NOR_TEAHC_SHIFT 0
  232. #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
  233. /*
  234. * FTIM1 - NOR Flash Mode
  235. */
  236. #define FTIM1_NOR 0xFF003F3F
  237. #define FTIM1_NOR_TACO_SHIFT 24
  238. #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
  239. #define FTIM1_NOR_TRAD_NOR_SHIFT 8
  240. #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
  241. #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
  242. #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
  243. /*
  244. * FTIM2 - NOR Flash Mode
  245. */
  246. #define FTIM2_NOR 0x0F3CFCFF
  247. #define FTIM2_NOR_TCS_SHIFT 24
  248. #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
  249. #define FTIM2_NOR_TCH_SHIFT 18
  250. #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
  251. #define FTIM2_NOR_TWPH_SHIFT 10
  252. #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
  253. #define FTIM2_NOR_TWP_SHIFT 0
  254. #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
  255. /*
  256. * FTIM0 - Normal GPCM Mode
  257. */
  258. #define FTIM0_GPCM 0xF03F3F3F
  259. #define FTIM0_GPCM_TACSE_SHIFT 28
  260. #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
  261. #define FTIM0_GPCM_TEADC_SHIFT 16
  262. #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
  263. #define FTIM0_GPCM_TAVDS_SHIFT 8
  264. #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
  265. #define FTIM0_GPCM_TEAHC_SHIFT 0
  266. #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
  267. /*
  268. * FTIM1 - Normal GPCM Mode
  269. */
  270. #define FTIM1_GPCM 0xFF003F00
  271. #define FTIM1_GPCM_TACO_SHIFT 24
  272. #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
  273. #define FTIM1_GPCM_TRAD_SHIFT 8
  274. #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
  275. /*
  276. * FTIM2 - Normal GPCM Mode
  277. */
  278. #define FTIM2_GPCM 0x0F3C00FF
  279. #define FTIM2_GPCM_TCS_SHIFT 24
  280. #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
  281. #define FTIM2_GPCM_TCH_SHIFT 18
  282. #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
  283. #define FTIM2_GPCM_TWP_SHIFT 0
  284. #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
  285. /*
  286. * Ready Busy Status Register (RB_STAT)
  287. */
  288. /* CSn is READY */
  289. #define IFC_RB_STAT_READY_CS0 0x80000000
  290. #define IFC_RB_STAT_READY_CS1 0x40000000
  291. #define IFC_RB_STAT_READY_CS2 0x20000000
  292. #define IFC_RB_STAT_READY_CS3 0x10000000
  293. /*
  294. * General Control Register (GCR)
  295. */
  296. #define IFC_GCR_MASK 0x8000F800
  297. /* reset all IFC hardware */
  298. #define IFC_GCR_SOFT_RST_ALL 0x80000000
  299. /* Turnaroud Time of external buffer */
  300. #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
  301. #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
  302. /*
  303. * Common Event and Error Status Register (CM_EVTER_STAT)
  304. */
  305. /* Chip select error */
  306. #define IFC_CM_EVTER_STAT_CSER 0x80000000
  307. /*
  308. * Common Event and Error Enable Register (CM_EVTER_EN)
  309. */
  310. /* Chip select error checking enable */
  311. #define IFC_CM_EVTER_EN_CSEREN 0x80000000
  312. /*
  313. * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
  314. */
  315. /* Chip select error interrupt enable */
  316. #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
  317. /*
  318. * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
  319. */
  320. /* transaction type of error Read/Write */
  321. #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
  322. #define IFC_CM_ERATTR0_ERAID 0x0FF00000
  323. #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
  324. /*
  325. * Clock Control Register (CCR)
  326. */
  327. #define IFC_CCR_MASK 0x0F0F8800
  328. /* Clock division ratio */
  329. #define IFC_CCR_CLK_DIV_MASK 0x0F000000
  330. #define IFC_CCR_CLK_DIV_SHIFT 24
  331. #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
  332. /* IFC Clock Delay */
  333. #define IFC_CCR_CLK_DLY_MASK 0x000F0000
  334. #define IFC_CCR_CLK_DLY_SHIFT 16
  335. #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
  336. /* Invert IFC clock before sending out */
  337. #define IFC_CCR_INV_CLK_EN 0x00008000
  338. /* Fedback IFC Clock */
  339. #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
  340. /*
  341. * Clock Status Register (CSR)
  342. */
  343. /* Clk is stable */
  344. #define IFC_CSR_CLK_STAT_STABLE 0x80000000
  345. /*
  346. * IFC_NAND Machine Specific Registers
  347. */
  348. /*
  349. * NAND Configuration Register (NCFGR)
  350. */
  351. /* Auto Boot Mode */
  352. #define IFC_NAND_NCFGR_BOOT 0x80000000
  353. /* SRAM INIT EN */
  354. #define IFC_NAND_SRAM_INIT_EN 0x20000000
  355. /* Addressing Mode-ROW0+n/COL0 */
  356. #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
  357. /* Addressing Mode-ROW0+n/COL0+n */
  358. #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
  359. /* Number of loop iterations of FIR sequences for multi page operations */
  360. #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
  361. #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
  362. #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
  363. /* Number of wait cycles */
  364. #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
  365. #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
  366. /*
  367. * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
  368. */
  369. /* General purpose FCM flash command bytes CMD0-CMD7 */
  370. #define IFC_NAND_FCR0_CMD0 0xFF000000
  371. #define IFC_NAND_FCR0_CMD0_SHIFT 24
  372. #define IFC_NAND_FCR0_CMD1 0x00FF0000
  373. #define IFC_NAND_FCR0_CMD1_SHIFT 16
  374. #define IFC_NAND_FCR0_CMD2 0x0000FF00
  375. #define IFC_NAND_FCR0_CMD2_SHIFT 8
  376. #define IFC_NAND_FCR0_CMD3 0x000000FF
  377. #define IFC_NAND_FCR0_CMD3_SHIFT 0
  378. #define IFC_NAND_FCR1_CMD4 0xFF000000
  379. #define IFC_NAND_FCR1_CMD4_SHIFT 24
  380. #define IFC_NAND_FCR1_CMD5 0x00FF0000
  381. #define IFC_NAND_FCR1_CMD5_SHIFT 16
  382. #define IFC_NAND_FCR1_CMD6 0x0000FF00
  383. #define IFC_NAND_FCR1_CMD6_SHIFT 8
  384. #define IFC_NAND_FCR1_CMD7 0x000000FF
  385. #define IFC_NAND_FCR1_CMD7_SHIFT 0
  386. /*
  387. * Flash ROW and COL Address Register (ROWn, COLn)
  388. */
  389. /* Main/spare region locator */
  390. #define IFC_NAND_COL_MS 0x80000000
  391. /* Column Address */
  392. #define IFC_NAND_COL_CA_MASK 0x00000FFF
  393. /*
  394. * NAND Flash Byte Count Register (NAND_BC)
  395. */
  396. /* Byte Count for read/Write */
  397. #define IFC_NAND_BC 0x000001FF
  398. /*
  399. * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
  400. */
  401. /* NAND Machine specific opcodes OP0-OP14*/
  402. #define IFC_NAND_FIR0_OP0 0xFC000000
  403. #define IFC_NAND_FIR0_OP0_SHIFT 26
  404. #define IFC_NAND_FIR0_OP1 0x03F00000
  405. #define IFC_NAND_FIR0_OP1_SHIFT 20
  406. #define IFC_NAND_FIR0_OP2 0x000FC000
  407. #define IFC_NAND_FIR0_OP2_SHIFT 14
  408. #define IFC_NAND_FIR0_OP3 0x00003F00
  409. #define IFC_NAND_FIR0_OP3_SHIFT 8
  410. #define IFC_NAND_FIR0_OP4 0x000000FC
  411. #define IFC_NAND_FIR0_OP4_SHIFT 2
  412. #define IFC_NAND_FIR1_OP5 0xFC000000
  413. #define IFC_NAND_FIR1_OP5_SHIFT 26
  414. #define IFC_NAND_FIR1_OP6 0x03F00000
  415. #define IFC_NAND_FIR1_OP6_SHIFT 20
  416. #define IFC_NAND_FIR1_OP7 0x000FC000
  417. #define IFC_NAND_FIR1_OP7_SHIFT 14
  418. #define IFC_NAND_FIR1_OP8 0x00003F00
  419. #define IFC_NAND_FIR1_OP8_SHIFT 8
  420. #define IFC_NAND_FIR1_OP9 0x000000FC
  421. #define IFC_NAND_FIR1_OP9_SHIFT 2
  422. #define IFC_NAND_FIR2_OP10 0xFC000000
  423. #define IFC_NAND_FIR2_OP10_SHIFT 26
  424. #define IFC_NAND_FIR2_OP11 0x03F00000
  425. #define IFC_NAND_FIR2_OP11_SHIFT 20
  426. #define IFC_NAND_FIR2_OP12 0x000FC000
  427. #define IFC_NAND_FIR2_OP12_SHIFT 14
  428. #define IFC_NAND_FIR2_OP13 0x00003F00
  429. #define IFC_NAND_FIR2_OP13_SHIFT 8
  430. #define IFC_NAND_FIR2_OP14 0x000000FC
  431. #define IFC_NAND_FIR2_OP14_SHIFT 2
  432. /*
  433. * Instruction opcodes to be programmed
  434. * in FIR registers- 6bits
  435. */
  436. enum ifc_nand_fir_opcodes {
  437. IFC_FIR_OP_NOP,
  438. IFC_FIR_OP_CA0,
  439. IFC_FIR_OP_CA1,
  440. IFC_FIR_OP_CA2,
  441. IFC_FIR_OP_CA3,
  442. IFC_FIR_OP_RA0,
  443. IFC_FIR_OP_RA1,
  444. IFC_FIR_OP_RA2,
  445. IFC_FIR_OP_RA3,
  446. IFC_FIR_OP_CMD0,
  447. IFC_FIR_OP_CMD1,
  448. IFC_FIR_OP_CMD2,
  449. IFC_FIR_OP_CMD3,
  450. IFC_FIR_OP_CMD4,
  451. IFC_FIR_OP_CMD5,
  452. IFC_FIR_OP_CMD6,
  453. IFC_FIR_OP_CMD7,
  454. IFC_FIR_OP_CW0,
  455. IFC_FIR_OP_CW1,
  456. IFC_FIR_OP_CW2,
  457. IFC_FIR_OP_CW3,
  458. IFC_FIR_OP_CW4,
  459. IFC_FIR_OP_CW5,
  460. IFC_FIR_OP_CW6,
  461. IFC_FIR_OP_CW7,
  462. IFC_FIR_OP_WBCD,
  463. IFC_FIR_OP_RBCD,
  464. IFC_FIR_OP_BTRD,
  465. IFC_FIR_OP_RDSTAT,
  466. IFC_FIR_OP_NWAIT,
  467. IFC_FIR_OP_WFR,
  468. IFC_FIR_OP_SBRD,
  469. IFC_FIR_OP_UA,
  470. IFC_FIR_OP_RB,
  471. };
  472. /*
  473. * NAND Chip Select Register (NAND_CSEL)
  474. */
  475. #define IFC_NAND_CSEL 0x0C000000
  476. #define IFC_NAND_CSEL_SHIFT 26
  477. #define IFC_NAND_CSEL_CS0 0x00000000
  478. #define IFC_NAND_CSEL_CS1 0x04000000
  479. #define IFC_NAND_CSEL_CS2 0x08000000
  480. #define IFC_NAND_CSEL_CS3 0x0C000000
  481. /*
  482. * NAND Operation Sequence Start (NANDSEQ_STRT)
  483. */
  484. /* NAND Flash Operation Start */
  485. #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
  486. /* Automatic Erase */
  487. #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
  488. /* Automatic Program */
  489. #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
  490. /* Automatic Copyback */
  491. #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
  492. /* Automatic Read Operation */
  493. #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
  494. /* Automatic Status Read */
  495. #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
  496. /*
  497. * NAND Event and Error Status Register (NAND_EVTER_STAT)
  498. */
  499. /* Operation Complete */
  500. #define IFC_NAND_EVTER_STAT_OPC 0x80000000
  501. /* Flash Timeout Error */
  502. #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
  503. /* Write Protect Error */
  504. #define IFC_NAND_EVTER_STAT_WPER 0x04000000
  505. /* ECC Error */
  506. #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
  507. /* RCW Load Done */
  508. #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
  509. /* Boot Loadr Done */
  510. #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
  511. /* Bad Block Indicator search select */
  512. #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
  513. /*
  514. * NAND Flash Page Read Completion Event Status Register
  515. * (PGRDCMPL_EVT_STAT)
  516. */
  517. #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
  518. /* Small Page 0-15 Done */
  519. #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
  520. /* Large Page(2K) 0-3 Done */
  521. #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
  522. /* Large Page(4K) 0-1 Done */
  523. #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
  524. /*
  525. * NAND Event and Error Enable Register (NAND_EVTER_EN)
  526. */
  527. /* Operation complete event enable */
  528. #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
  529. /* Page read complete event enable */
  530. #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
  531. /* Flash Timeout error enable */
  532. #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
  533. /* Write Protect error enable */
  534. #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
  535. /* ECC error logging enable */
  536. #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
  537. /*
  538. * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
  539. */
  540. /* Enable interrupt for operation complete */
  541. #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
  542. /* Enable interrupt for Page read complete */
  543. #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
  544. /* Enable interrupt for Flash timeout error */
  545. #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
  546. /* Enable interrupt for Write protect error */
  547. #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
  548. /* Enable interrupt for ECC error*/
  549. #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
  550. /*
  551. * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
  552. */
  553. #define IFC_NAND_ERATTR0_MASK 0x0C080000
  554. /* Error on CS0-3 for NAND */
  555. #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
  556. #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
  557. #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
  558. #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
  559. /* Transaction type of error Read/Write */
  560. #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
  561. /*
  562. * NAND Flash Status Register (NAND_FSR)
  563. */
  564. /* First byte of data read from read status op */
  565. #define IFC_NAND_NFSR_RS0 0xFF000000
  566. /* Second byte of data read from read status op */
  567. #define IFC_NAND_NFSR_RS1 0x00FF0000
  568. /*
  569. * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
  570. */
  571. /* Number of ECC errors on sector n (n = 0-15) */
  572. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
  573. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
  574. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
  575. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
  576. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
  577. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
  578. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
  579. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
  580. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
  581. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
  582. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
  583. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
  584. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
  585. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
  586. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
  587. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
  588. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
  589. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
  590. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
  591. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
  592. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
  593. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
  594. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
  595. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
  596. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
  597. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
  598. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
  599. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
  600. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
  601. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
  602. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
  603. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
  604. /*
  605. * NAND Control Register (NANDCR)
  606. */
  607. #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
  608. #define IFC_NAND_NCR_FTOCNT_SHIFT 25
  609. #define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
  610. /*
  611. * NAND_AUTOBOOT_TRGR
  612. */
  613. /* Trigger RCW load */
  614. #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
  615. /* Trigget Auto Boot */
  616. #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
  617. /*
  618. * NAND_MDR
  619. */
  620. /* 1st read data byte when opcode SBRD */
  621. #define IFC_NAND_MDR_RDATA0 0xFF000000
  622. /* 2nd read data byte when opcode SBRD */
  623. #define IFC_NAND_MDR_RDATA1 0x00FF0000
  624. /*
  625. * NOR Machine Specific Registers
  626. */
  627. /*
  628. * NOR Event and Error Status Register (NOR_EVTER_STAT)
  629. */
  630. /* NOR Command Sequence Operation Complete */
  631. #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
  632. /* Write Protect Error */
  633. #define IFC_NOR_EVTER_STAT_WPER 0x04000000
  634. /* Command Sequence Timeout Error */
  635. #define IFC_NOR_EVTER_STAT_STOER 0x01000000
  636. /*
  637. * NOR Event and Error Enable Register (NOR_EVTER_EN)
  638. */
  639. /* NOR Command Seq complete event enable */
  640. #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
  641. /* Write Protect Error Checking Enable */
  642. #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
  643. /* Timeout Error Enable */
  644. #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
  645. /*
  646. * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
  647. */
  648. /* Enable interrupt for OPC complete */
  649. #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
  650. /* Enable interrupt for write protect error */
  651. #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
  652. /* Enable interrupt for timeout error */
  653. #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
  654. /*
  655. * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
  656. */
  657. /* Source ID for error transaction */
  658. #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
  659. /* AXI ID for error transation */
  660. #define IFC_NOR_ERATTR0_ERAID 0x000FF000
  661. /* Chip select corresponds to NOR error */
  662. #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
  663. #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
  664. #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
  665. #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
  666. /* Type of transaction read/write */
  667. #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
  668. /*
  669. * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
  670. */
  671. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
  672. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
  673. /*
  674. * NOR Control Register (NORCR)
  675. */
  676. #define IFC_NORCR_MASK 0x0F0F0000
  677. /* No. of Address/Data Phase */
  678. #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
  679. #define IFC_NORCR_NUM_PHASE_SHIFT 24
  680. #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
  681. /* Sequence Timeout Count */
  682. #define IFC_NORCR_STOCNT_MASK 0x000F0000
  683. #define IFC_NORCR_STOCNT_SHIFT 16
  684. #define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
  685. /*
  686. * GPCM Machine specific registers
  687. */
  688. /*
  689. * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
  690. */
  691. /* Timeout error */
  692. #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
  693. /* Parity error */
  694. #define IFC_GPCM_EVTER_STAT_PER 0x01000000
  695. /*
  696. * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
  697. */
  698. /* Timeout error enable */
  699. #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
  700. /* Parity error enable */
  701. #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
  702. /*
  703. * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
  704. */
  705. /* Enable Interrupt for timeout error */
  706. #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
  707. /* Enable Interrupt for Parity error */
  708. #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
  709. /*
  710. * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
  711. */
  712. /* Source ID for error transaction */
  713. #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
  714. /* AXI ID for error transaction */
  715. #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
  716. /* Chip select corresponds to GPCM error */
  717. #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
  718. #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
  719. #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
  720. #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
  721. /* Type of transaction read/Write */
  722. #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
  723. /*
  724. * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
  725. */
  726. /* On which beat of address/data parity error is observed */
  727. #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
  728. /* Parity Error on byte */
  729. #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
  730. /* Parity Error reported in addr or data phase */
  731. #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
  732. /*
  733. * GPCM Status Register (GPCM_STAT)
  734. */
  735. #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
  736. #ifndef __ASSEMBLY__
  737. #include <asm/io.h>
  738. extern void print_ifc_regs(void);
  739. extern void init_early_memctl_regs(void);
  740. void init_final_memctl_regs(void);
  741. #define IFC_RREGS_4KOFFSET (4*1024)
  742. #define IFC_RREGS_64KOFFSET (64*1024)
  743. #define IFC_FCM_BASE_ADDR \
  744. ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
  745. #define get_ifc_cspr_ext(i) \
  746. (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
  747. #define get_ifc_cspr(i) \
  748. (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
  749. #define get_ifc_csor_ext(i) \
  750. (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
  751. #define get_ifc_csor(i) \
  752. (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
  753. #define get_ifc_amask(i) \
  754. (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
  755. #define get_ifc_ftim(i, j) \
  756. (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
  757. #define set_ifc_cspr_ext(i, v) \
  758. (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
  759. #define set_ifc_cspr(i, v) \
  760. (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
  761. #define set_ifc_csor_ext(i, v) \
  762. (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
  763. #define set_ifc_csor(i, v) \
  764. (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
  765. #define set_ifc_amask(i, v) \
  766. (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
  767. #define set_ifc_ftim(i, j, v) \
  768. (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
  769. enum ifc_chip_sel {
  770. IFC_CS0,
  771. IFC_CS1,
  772. IFC_CS2,
  773. IFC_CS3,
  774. IFC_CS4,
  775. IFC_CS5,
  776. IFC_CS6,
  777. IFC_CS7,
  778. };
  779. enum ifc_ftims {
  780. IFC_FTIM0,
  781. IFC_FTIM1,
  782. IFC_FTIM2,
  783. IFC_FTIM3,
  784. };
  785. /*
  786. * IFC Controller NAND Machine registers
  787. */
  788. struct fsl_ifc_nand {
  789. u32 ncfgr;
  790. u32 res1[0x4];
  791. u32 nand_fcr0;
  792. u32 nand_fcr1;
  793. u32 res2[0x8];
  794. u32 row0;
  795. u32 res3;
  796. u32 col0;
  797. u32 res4;
  798. u32 row1;
  799. u32 res5;
  800. u32 col1;
  801. u32 res6;
  802. u32 row2;
  803. u32 res7;
  804. u32 col2;
  805. u32 res8;
  806. u32 row3;
  807. u32 res9;
  808. u32 col3;
  809. u32 res10[0x24];
  810. u32 nand_fbcr;
  811. u32 res11;
  812. u32 nand_fir0;
  813. u32 nand_fir1;
  814. u32 nand_fir2;
  815. u32 res12[0x10];
  816. u32 nand_csel;
  817. u32 res13;
  818. u32 nandseq_strt;
  819. u32 res14;
  820. u32 nand_evter_stat;
  821. u32 res15;
  822. u32 pgrdcmpl_evt_stat;
  823. u32 res16[0x2];
  824. u32 nand_evter_en;
  825. u32 res17[0x2];
  826. u32 nand_evter_intr_en;
  827. u32 nand_vol_addr_stat;
  828. u32 res18;
  829. u32 nand_erattr0;
  830. u32 nand_erattr1;
  831. u32 res19[0x10];
  832. u32 nand_fsr;
  833. u32 res20[0x1];
  834. u32 nand_eccstat[8];
  835. u32 res21[0x1c];
  836. u32 nanndcr;
  837. u32 res22[0x2];
  838. u32 nand_autoboot_trgr;
  839. u32 res23;
  840. u32 nand_mdr;
  841. u32 res24[0x1c];
  842. u32 nand_dll_lowcfg0;
  843. u32 nand_dll_lowcfg1;
  844. u32 res25;
  845. u32 nand_dll_lowstat;
  846. u32 res26[0x3C];
  847. };
  848. /*
  849. * IFC controller NOR Machine registers
  850. */
  851. struct fsl_ifc_nor {
  852. u32 nor_evter_stat;
  853. u32 res1[0x2];
  854. u32 nor_evter_en;
  855. u32 res2[0x2];
  856. u32 nor_evter_intr_en;
  857. u32 res3[0x2];
  858. u32 nor_erattr0;
  859. u32 nor_erattr1;
  860. u32 nor_erattr2;
  861. u32 res4[0x4];
  862. u32 norcr;
  863. u32 res5[0xEF];
  864. };
  865. /*
  866. * IFC controller GPCM Machine registers
  867. */
  868. struct fsl_ifc_gpcm {
  869. u32 gpcm_evter_stat;
  870. u32 res1[0x2];
  871. u32 gpcm_evter_en;
  872. u32 res2[0x2];
  873. u32 gpcm_evter_intr_en;
  874. u32 res3[0x2];
  875. u32 gpcm_erattr0;
  876. u32 gpcm_erattr1;
  877. u32 gpcm_erattr2;
  878. u32 gpcm_stat;
  879. };
  880. #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
  881. #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
  882. #define IFC_CSPR_REG_LEN 148
  883. #define IFC_AMASK_REG_LEN 144
  884. #define IFC_CSOR_REG_LEN 144
  885. #define IFC_FTIM_REG_LEN 576
  886. #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
  887. CONFIG_SYS_FSL_IFC_BANK_COUNT
  888. #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
  889. CONFIG_SYS_FSL_IFC_BANK_COUNT
  890. #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
  891. CONFIG_SYS_FSL_IFC_BANK_COUNT
  892. #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
  893. CONFIG_SYS_FSL_IFC_BANK_COUNT
  894. #else
  895. #error IFC BANK count not vaild
  896. #endif
  897. #else
  898. #error IFC BANK count not defined
  899. #endif
  900. struct fsl_ifc_cspr {
  901. u32 cspr_ext;
  902. u32 cspr;
  903. u32 res;
  904. };
  905. struct fsl_ifc_amask {
  906. u32 amask;
  907. u32 res[0x2];
  908. };
  909. struct fsl_ifc_csor {
  910. u32 csor;
  911. u32 csor_ext;
  912. u32 res;
  913. };
  914. struct fsl_ifc_ftim {
  915. u32 ftim[4];
  916. u32 res[0x8];
  917. };
  918. /*
  919. * IFC Controller Global Registers
  920. * FCM - Flash control machine
  921. */
  922. struct fsl_ifc_fcm {
  923. u32 ifc_rev;
  924. u32 res1[0x2];
  925. struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  926. u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
  927. struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  928. u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
  929. struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  930. u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
  931. struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
  932. u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
  933. u32 rb_stat;
  934. u32 rb_map;
  935. u32 wp_map;
  936. u32 ifc_gcr;
  937. u32 res7[0x2];
  938. u32 cm_evter_stat;
  939. u32 res8[0x2];
  940. u32 cm_evter_en;
  941. u32 res9[0x2];
  942. u32 cm_evter_intr_en;
  943. u32 res10[0x2];
  944. u32 cm_erattr0;
  945. u32 cm_erattr1;
  946. u32 res11[0x2];
  947. u32 ifc_ccr;
  948. u32 ifc_csr;
  949. u32 ddr_ccr_low;
  950. };
  951. struct fsl_ifc_runtime {
  952. struct fsl_ifc_nand ifc_nand;
  953. struct fsl_ifc_nor ifc_nor;
  954. struct fsl_ifc_gpcm ifc_gpcm;
  955. };
  956. struct fsl_ifc {
  957. struct fsl_ifc_fcm *gregs;
  958. struct fsl_ifc_runtime *rregs;
  959. };
  960. struct ifc_regs {
  961. const char *name;
  962. u32 pr;
  963. u32 pr_ext;
  964. u32 amask;
  965. u32 or;
  966. u32 ftim[4];
  967. u32 or_ext;
  968. u32 pr_final;
  969. u32 amask_final;
  970. };
  971. struct ifc_regs_info {
  972. struct ifc_regs *regs;
  973. u32 cs_size;
  974. };
  975. #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  976. #undef CSPR_MSEL_NOR
  977. #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
  978. #endif
  979. #endif /* CONFIG_FSL_IFC */
  980. #endif /* __ASSEMBLY__ */
  981. #endif /* __FSL_IFC_H */