fsl_fman.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * MPC85xx Internal Memory Map
  4. *
  5. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef __FSL_FMAN_H__
  8. #define __FSL_FMAN_H__
  9. #include <asm/types.h>
  10. typedef struct fm_bmi_common {
  11. u32 fmbm_init; /* BMI initialization */
  12. u32 fmbm_cfg1; /* BMI configuration1 */
  13. u32 fmbm_cfg2; /* BMI configuration2 */
  14. u32 res0[0x5];
  15. u32 fmbm_ievr; /* interrupt event register */
  16. u32 fmbm_ier; /* interrupt enable register */
  17. u32 fmbm_ifr; /* interrupt force register */
  18. u32 res1[0x5];
  19. u32 fmbm_arb[0x8]; /* BMI arbitration */
  20. u32 res2[0x28];
  21. u32 fmbm_gde; /* global debug enable */
  22. u32 fmbm_pp[0x3f]; /* BMI port parameters */
  23. u32 res3;
  24. u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */
  25. u32 res4;
  26. u32 fmbm_ppid[0x3f];/* port partition ID */
  27. } fm_bmi_common_t;
  28. typedef struct fm_qmi_common {
  29. u32 fmqm_gc; /* general configuration register */
  30. u32 res0;
  31. u32 fmqm_eie; /* error interrupt event register */
  32. u32 fmqm_eien; /* error interrupt enable register */
  33. u32 fmqm_eif; /* error interrupt force register */
  34. u32 fmqm_ie; /* interrupt event register */
  35. u32 fmqm_ien; /* interrupt enable register */
  36. u32 fmqm_if; /* interrupt force register */
  37. u32 fmqm_gs; /* global status register */
  38. u32 fmqm_ts; /* task status register */
  39. u32 fmqm_etfc; /* enqueue total frame counter */
  40. u32 fmqm_dtfc; /* dequeue total frame counter */
  41. u32 fmqm_dc0; /* dequeue counter 0 */
  42. u32 fmqm_dc1; /* dequeue counter 1 */
  43. u32 fmqm_dc2; /* dequeue counter 2 */
  44. u32 fmqm_dc3; /* dequeue counter 3 */
  45. u32 fmqm_dfnoc; /* dequeue FQID not override counter */
  46. u32 fmqm_dfcc; /* dequeue FQID from context counter */
  47. u32 fmqm_dffc; /* dequeue FQID from FD counter */
  48. u32 fmqm_dcc; /* dequeue confirm counter */
  49. u32 res1[0xc];
  50. u32 fmqm_dtrc; /* debug trap configuration register */
  51. u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */
  52. u32 res3[0x2];
  53. u32 res4[0xdc]; /* missing debug regs */
  54. } fm_qmi_common_t;
  55. typedef struct fm_bmi {
  56. u8 res[1024];
  57. } fm_bmi_t;
  58. typedef struct fm_qmi {
  59. u8 res[1024];
  60. } fm_qmi_t;
  61. struct fm_bmi_rx_port {
  62. u32 fmbm_rcfg; /* Rx configuration */
  63. u32 fmbm_rst; /* Rx status */
  64. u32 fmbm_rda; /* Rx DMA attributes */
  65. u32 fmbm_rfp; /* Rx FIFO parameters */
  66. u32 fmbm_rfed; /* Rx frame end data */
  67. u32 fmbm_ricp; /* Rx internal context parameters */
  68. u32 fmbm_rim; /* Rx internal margins */
  69. u32 fmbm_rebm; /* Rx external buffer margins */
  70. u32 fmbm_rfne; /* Rx frame next engine */
  71. u32 fmbm_rfca; /* Rx frame command attributes */
  72. u32 fmbm_rfpne; /* Rx frame parser next engine */
  73. u32 fmbm_rpso; /* Rx parse start offset */
  74. u32 fmbm_rpp; /* Rx policer profile */
  75. u32 fmbm_rccb; /* Rx coarse classification base */
  76. u32 res1[0x2];
  77. u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */
  78. u32 fmbm_rfqid; /* Rx frame queue ID */
  79. u32 fmbm_refqid; /* Rx error frame queue ID */
  80. u32 fmbm_rfsdm; /* Rx frame status discard mask */
  81. u32 fmbm_rfsem; /* Rx frame status error mask */
  82. u32 fmbm_rfene; /* Rx frame enqueue next engine */
  83. u32 res2[0x23];
  84. u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */
  85. u32 fmbm_acnt[0x8]; /* allocate counter */
  86. u32 res3[0x8];
  87. u32 fmbm_cgm[0x8]; /* congestion group map */
  88. u32 fmbm_mpd; /* BMan pool depletion */
  89. u32 res4[0x1F];
  90. u32 fmbm_rstc; /* Rx statistics counters */
  91. u32 fmbm_rfrc; /* Rx frame counters */
  92. u32 fmbm_rfbc; /* Rx bad frames counter */
  93. u32 fmbm_rlfc; /* Rx large frames counter */
  94. u32 fmbm_rffc; /* Rx filter frames counter */
  95. u32 fmbm_rfdc; /* Rx frame discard counter */
  96. u32 fmbm_rfldec; /* Rx frames list DMA error counter */
  97. u32 fmbm_rodc; /* Rx out of buffers discard counter */
  98. u32 fmbm_rbdc; /* Rx buffers deallocate counter */
  99. u32 res5[0x17];
  100. u32 fmbm_rpc; /* Rx performance counters */
  101. u32 fmbm_rpcp; /* Rx performance count parameters */
  102. u32 fmbm_rccn; /* Rx cycle counter */
  103. u32 fmbm_rtuc; /* Rx tasks utilization counter */
  104. u32 fmbm_rrquc; /* Rx receive queue utilization counter */
  105. u32 fmbm_rduc; /* Rx DMA utilization counter */
  106. u32 fmbm_rfuc; /* Rx FIFO utilization counter */
  107. u32 fmbm_rpac; /* Rx pause activation counter */
  108. u32 res6[0x18];
  109. u32 fmbm_rdbg; /* Rx debug configuration */
  110. };
  111. /* FMBM_RCFG - Rx configuration */
  112. #define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */
  113. #define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */
  114. #define FMBM_RCFG_IM 0x01000000 /* independent mode */
  115. /* FMBM_RST - Rx status */
  116. #define FMBM_RST_BSY 0x80000000 /* Rx port is busy */
  117. /* FMBM_RFCA - Rx frame command attributes */
  118. #define FMBM_RFCA_ORDER 0x80000000
  119. #define FMBM_RFCA_MR_MASK 0x003f0000
  120. #define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK)
  121. /* FMBM_RSTC - Rx statistics */
  122. #define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */
  123. struct fm_bmi_tx_port {
  124. u32 fmbm_tcfg; /* Tx configuration */
  125. u32 fmbm_tst; /* Tx status */
  126. u32 fmbm_tda; /* Tx DMA attributes */
  127. u32 fmbm_tfp; /* Tx FIFO parameters */
  128. u32 fmbm_tfed; /* Tx frame end data */
  129. u32 fmbm_ticp; /* Tx internal context parameters */
  130. u32 fmbm_tfne; /* Tx frame next engine */
  131. u32 fmbm_tfca; /* Tx frame command attributes */
  132. u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
  133. u32 fmbm_tfeqid;/* Tx error frame queue ID */
  134. u32 fmbm_tfene; /* Tx frame enqueue next engine */
  135. u32 fmbm_trlmts;/* Tx rate limiter scale */
  136. u32 fmbm_trlmt; /* Tx rate limiter */
  137. u32 res0[0x73];
  138. u32 fmbm_tstc; /* Tx statistics counters */
  139. u32 fmbm_tfrc; /* Tx frame counter */
  140. u32 fmbm_tfdc; /* Tx frames discard counter */
  141. u32 fmbm_tfledc;/* Tx frame length error discard counter */
  142. u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
  143. u32 fmbm_tbdc; /* Tx buffers deallocate counter */
  144. u32 res1[0x1a];
  145. u32 fmbm_tpc; /* Tx performance counters */
  146. u32 fmbm_tpcp; /* Tx performance count parameters */
  147. u32 fmbm_tccn; /* Tx cycle counter */
  148. u32 fmbm_ttuc; /* Tx tasks utilization counter */
  149. u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
  150. u32 fmbm_tduc; /* Tx DMA utilization counter */
  151. u32 fmbm_tfuc; /* Tx FIFO utilization counter */
  152. u32 res2[0x19];
  153. u32 fmbm_tdcfg; /* Tx debug configuration */
  154. };
  155. /* FMBM_TCFG - Tx configuration */
  156. #define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */
  157. #define FMBM_TCFG_IM 0x01000000 /* independent mode enable */
  158. /* FMBM_TST - Tx status */
  159. #define FMBM_TST_BSY 0x80000000 /* Tx port is busy */
  160. /* FMBM_TFCA - Tx frame command attributes */
  161. #define FMBM_TFCA_ORDER 0x80000000
  162. #define FMBM_TFCA_MR_MASK 0x003f0000
  163. #define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK)
  164. /* FMBM_TSTC - Tx statistics counters */
  165. #define FMBM_TSTC_EN 0x80000000
  166. /* FMBM_INIT - BMI initialization register */
  167. #define FMBM_INIT_START 0x80000000 /* init internal buffers */
  168. /* FMBM_CFG1 - BMI configuration 1 */
  169. #define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */
  170. #define FMBM_CFG1_FBPS_SHIFT 16
  171. #define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */
  172. /* FMBM_IEVR - interrupt event */
  173. #define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */
  174. #define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */
  175. #define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */
  176. #define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
  177. /* FMBM_IER - interrupt enable */
  178. #define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */
  179. #define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */
  180. #define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */
  181. #define FMBM_IER_DISABLE_ALL 0x00000000
  182. /* FMBM_PP - BMI Port Parameters */
  183. #define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */
  184. #define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK)
  185. #define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */
  186. #define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK)
  187. /* FMBM_PFS - BMI Port FIFO Size */
  188. #define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */
  189. #define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK)
  190. /* FMQM_GC - global configuration */
  191. #define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */
  192. #define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */
  193. #define FMQM_GC_STEN 0x10000000 /* enable global stat counters */
  194. #define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */
  195. #define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS)
  196. #define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */
  197. #define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK)
  198. /* FMQM_EIE - error interrupt event register */
  199. #define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */
  200. #define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */
  201. #define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE)
  202. /* FMQM_EIEN - error interrupt enable register */
  203. #define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */
  204. #define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */
  205. #define FMQM_EIEN_DISABLE_ALL 0x00000000
  206. /* FMQM_IE - interrupt event register */
  207. #define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */
  208. #define FMQM_IE_CLEAR_ALL FMQM_IE_SEE
  209. /* FMQM_IEN - interrupt enable register */
  210. #define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */
  211. #define FMQM_IEN_DISABLE_ALL 0x00000000
  212. /* NIA - next invoked action */
  213. #define NIA_ENG_RISC 0x00000000
  214. #define NIA_ENG_MASK 0x007c0000
  215. /* action code */
  216. #define NIA_RISC_AC_CC 0x00000006
  217. #define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */
  218. #define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */
  219. #define NIA_RISC_AC_HC 0x0000000c
  220. typedef struct fm_parser {
  221. u8 res[1024];
  222. } fm_parser_t;
  223. typedef struct fm_policer {
  224. u8 res[4*1024];
  225. } fm_policer_t;
  226. typedef struct fm_keygen {
  227. u8 res[4*1024];
  228. } fm_keygen_t;
  229. typedef struct fm_dma {
  230. u32 fmdmsr; /* status register */
  231. u32 fmdmmr; /* mode register */
  232. u32 fmdmtr; /* bus threshold register */
  233. u32 fmdmhy; /* bus hysteresis register */
  234. u32 fmdmsetr; /* SOS emergency threshold register */
  235. u32 fmdmtah; /* transfer bus address high register */
  236. u32 fmdmtal; /* transfer bus address low register */
  237. u32 fmdmtcid; /* transfer bus communication ID register */
  238. u32 fmdmra; /* DMA bus internal ram address register */
  239. u32 fmdmrd; /* DMA bus internal ram data register */
  240. u32 res0[0xb];
  241. u32 fmdmdcr; /* debug counter */
  242. u32 fmdmemsr; /* emrgency smoother register */
  243. u32 res1;
  244. u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */
  245. u32 res[0x3c8];
  246. } fm_dma_t;
  247. /* FMDMSR - Fman DMA status register */
  248. #define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */
  249. #define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */
  250. #define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */
  251. #define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */
  252. #define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */
  253. #define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */
  254. #define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */
  255. #define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */
  256. #define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */
  257. #define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */
  258. #define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \
  259. | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
  260. | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
  261. | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
  262. | FMDMSR_SPDAT_FECC)
  263. /* FMDMMR - FMan DMA mode register */
  264. #define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */
  265. typedef struct fm_fpm {
  266. u32 fpmtnc; /* TNUM control */
  267. u32 fpmprc; /* Port_ID control */
  268. u32 res0;
  269. u32 fpmflc; /* flush control */
  270. u32 fpmdis1; /* dispatch thresholds1 */
  271. u32 fpmdis2; /* dispatch thresholds2 */
  272. u32 fmepi; /* error pending interrupts */
  273. u32 fmrie; /* rams interrupt enable */
  274. u32 fpmfcevent[0x4];/* FMan controller event 0-3 */
  275. u32 res1[0x4];
  276. u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */
  277. u32 res2[0x4];
  278. u32 fpmtsc1; /* timestamp control1 */
  279. u32 fpmtsc2; /* timestamp control2 */
  280. u32 fpmtsp; /* time stamp */
  281. u32 fpmtsf; /* time stamp fraction */
  282. u32 fpmrcr; /* rams control and event */
  283. u32 res3[0x3];
  284. u32 fpmdrd[0x4]; /* data_ram data 0-3 */
  285. u32 res4[0xc];
  286. u32 fpmdra; /* data ram access */
  287. u32 fm_ip_rev_1; /* IP block revision 1 */
  288. u32 fm_ip_rev_2; /* IP block revision 2 */
  289. u32 fmrstc; /* reset command */
  290. u32 fmcld; /* classifier debug control */
  291. u32 fmnpi; /* normal pending interrupts */
  292. u32 res5;
  293. u32 fmfpee; /* event and enable */
  294. u32 fpmcev[0x4]; /* CPU event 0-3 */
  295. u32 res6[0x4];
  296. u32 fmfp_ps[0x40]; /* port status */
  297. u32 res7[0x260];
  298. u32 fpmts[0x80]; /* task status */
  299. u32 res8[0xa0];
  300. } fm_fpm_t;
  301. /* FMFP_PRC - FPM Port_ID Control Register */
  302. #define FMFPPRC_PORTID_MASK 0x3f000000
  303. #define FMFPPRC_PORTID_SHIFT 24
  304. #define FMFPPRC_ORA_SHIFT 16
  305. #define FMFPPRC_RISC1 0x00000001
  306. #define FMFPPRC_RISC2 0x00000002
  307. #define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2)
  308. /* FPM Flush Control Register */
  309. #define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */
  310. /* FMFP_EE - FPM event and enable register */
  311. #define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */
  312. #define FMFPEE_STL 0x40000000 /* stall of task ... */
  313. #define FMFPEE_SECC 0x20000000 /* single ECC error */
  314. #define FMFPEE_RFM 0x00010000 /* release FMan */
  315. #define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */
  316. #define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */
  317. #define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */
  318. #define FMFPEE_EHM 0x00000008 /* external halt enable */
  319. #define FMFPEE_UEC 0x00000004 /* FMan is not halted */
  320. #define FMFPEE_CER 0x00000002 /* only errornous task stalled */
  321. #define FMFPEE_DER 0x00000001 /* DMA error is just reported */
  322. #define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
  323. FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
  324. FMFPEE_DER | FMFPEE_RFM)
  325. /* FMFP_RCR - FMan Rams Control and Event */
  326. #define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */
  327. #define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */
  328. typedef struct fm_imem {
  329. u32 iadd; /* instruction address register */
  330. u32 idata; /* instruction data register */
  331. u32 itcfg; /* timing config register */
  332. u32 iready; /* ready register */
  333. u8 res[0xff0];
  334. } fm_imem_t;
  335. #define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */
  336. #define IRAM_READY 0x80000000 /* ready to use */
  337. typedef struct fm_soft_parser {
  338. u8 res[4*1024];
  339. } fm_soft_parser_t;
  340. typedef struct fm_dtesc {
  341. u8 res[4*1024];
  342. } fm_dtsec_t;
  343. typedef struct fm_mdio {
  344. u8 res0[0x120];
  345. u32 miimcfg; /* MII management configuration reg */
  346. u32 miimcom; /* MII management command reg */
  347. u32 miimadd; /* MII management address reg */
  348. u32 miimcon; /* MII management control reg */
  349. u32 miimstat; /* MII management status reg */
  350. u32 miimind; /* MII management indication reg */
  351. u8 res1[0x1000 - 0x138];
  352. } fm_mdio_t;
  353. typedef struct fm_10gec {
  354. u8 res[4*1024];
  355. } fm_10gec_t;
  356. typedef struct fm_10gec_mdio {
  357. u8 res[4*1024];
  358. } fm_10gec_mdio_t;
  359. typedef struct fm_memac {
  360. u8 res[4*1024];
  361. } fm_memac_t;
  362. typedef struct fm_memac_mdio {
  363. u8 res[4*1024];
  364. } fm_memac_mdio_t;
  365. typedef struct fm_1588 {
  366. u8 res[4*1024];
  367. } fm_1588_t;
  368. typedef struct ccsr_fman {
  369. u8 muram[0x80000];
  370. fm_bmi_common_t fm_bmi_common;
  371. fm_qmi_common_t fm_qmi_common;
  372. u8 res0[2048];
  373. struct {
  374. fm_bmi_t fm_bmi;
  375. fm_qmi_t fm_qmi;
  376. fm_parser_t fm_parser;
  377. u8 res[1024];
  378. } port[63];
  379. fm_policer_t fm_policer;
  380. fm_keygen_t fm_keygen;
  381. fm_dma_t fm_dma;
  382. fm_fpm_t fm_fpm;
  383. fm_imem_t fm_imem;
  384. u8 res1[8*1024];
  385. fm_soft_parser_t fm_soft_parser;
  386. u8 res2[96*1024];
  387. #ifdef CONFIG_SYS_FMAN_V3
  388. struct {
  389. fm_memac_t fm_memac;
  390. fm_memac_mdio_t fm_memac_mdio;
  391. } memac[10];
  392. u8 res4[32*1024];
  393. fm_memac_mdio_t fm_dedicated_mdio[2];
  394. #else
  395. struct {
  396. fm_dtsec_t fm_dtesc;
  397. fm_mdio_t fm_mdio;
  398. } mac_1g[8]; /* support up to 8 1g controllers */
  399. struct {
  400. fm_10gec_t fm_10gec;
  401. fm_10gec_mdio_t fm_10gec_mdio;
  402. } mac_10g[1];
  403. u8 res4[48*1024];
  404. #endif
  405. fm_1588_t fm_1588;
  406. u8 res5[4*1024];
  407. } ccsr_fman_t;
  408. void fdt_fixup_fman_firmware(void *blob);
  409. #endif /*__FSL_FMAN_H__*/