fsl_esdhc_imx.h 8.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * FSL SD/MMC Defines
  4. *-------------------------------------------------------------------
  5. *
  6. * Copyright 2019 NXP
  7. * Yangbo Lu <yangbo.lu@nxp.com>
  8. *
  9. * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
  10. */
  11. #ifndef __FSL_ESDHC_IMX_H__
  12. #define __FSL_ESDHC_IMX_H__
  13. #include <linux/bitops.h>
  14. #include <linux/errno.h>
  15. #include <asm/byteorder.h>
  16. /* needed for the mmc_cfg definition */
  17. #include <mmc.h>
  18. /* FSL eSDHC-specific constants */
  19. #define SYSCTL 0x0002e02c
  20. #define SYSCTL_INITA 0x08000000
  21. #define SYSCTL_TIMEOUT_MASK 0x000f0000
  22. #define SYSCTL_CLOCK_MASK 0x0000fff0
  23. #if !defined(CONFIG_FSL_USDHC)
  24. #define SYSCTL_CKEN 0x00000008
  25. #define SYSCTL_PEREN 0x00000004
  26. #define SYSCTL_HCKEN 0x00000002
  27. #define SYSCTL_IPGEN 0x00000001
  28. #endif
  29. #define SYSCTL_RSTA 0x01000000
  30. #define SYSCTL_RSTC 0x02000000
  31. #define SYSCTL_RSTD 0x04000000
  32. #define VENDORSPEC_CKEN 0x00004000
  33. #define VENDORSPEC_PEREN 0x00002000
  34. #define VENDORSPEC_HCKEN 0x00001000
  35. #define VENDORSPEC_IPGEN 0x00000800
  36. #define VENDORSPEC_INIT 0x20007809
  37. #define IRQSTAT 0x0002e030
  38. #define IRQSTAT_DMAE (0x10000000)
  39. #define IRQSTAT_AC12E (0x01000000)
  40. #define IRQSTAT_DEBE (0x00400000)
  41. #define IRQSTAT_DCE (0x00200000)
  42. #define IRQSTAT_DTOE (0x00100000)
  43. #define IRQSTAT_CIE (0x00080000)
  44. #define IRQSTAT_CEBE (0x00040000)
  45. #define IRQSTAT_CCE (0x00020000)
  46. #define IRQSTAT_CTOE (0x00010000)
  47. #define IRQSTAT_CINT (0x00000100)
  48. #define IRQSTAT_CRM (0x00000080)
  49. #define IRQSTAT_CINS (0x00000040)
  50. #define IRQSTAT_BRR (0x00000020)
  51. #define IRQSTAT_BWR (0x00000010)
  52. #define IRQSTAT_DINT (0x00000008)
  53. #define IRQSTAT_BGE (0x00000004)
  54. #define IRQSTAT_TC (0x00000002)
  55. #define IRQSTAT_CC (0x00000001)
  56. #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
  57. #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
  58. IRQSTAT_DMAE)
  59. #define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
  60. #define IRQSTATEN 0x0002e034
  61. #define IRQSTATEN_DMAE (0x10000000)
  62. #define IRQSTATEN_AC12E (0x01000000)
  63. #define IRQSTATEN_DEBE (0x00400000)
  64. #define IRQSTATEN_DCE (0x00200000)
  65. #define IRQSTATEN_DTOE (0x00100000)
  66. #define IRQSTATEN_CIE (0x00080000)
  67. #define IRQSTATEN_CEBE (0x00040000)
  68. #define IRQSTATEN_CCE (0x00020000)
  69. #define IRQSTATEN_CTOE (0x00010000)
  70. #define IRQSTATEN_CINT (0x00000100)
  71. #define IRQSTATEN_CRM (0x00000080)
  72. #define IRQSTATEN_CINS (0x00000040)
  73. #define IRQSTATEN_BRR (0x00000020)
  74. #define IRQSTATEN_BWR (0x00000010)
  75. #define IRQSTATEN_DINT (0x00000008)
  76. #define IRQSTATEN_BGE (0x00000004)
  77. #define IRQSTATEN_TC (0x00000002)
  78. #define IRQSTATEN_CC (0x00000001)
  79. #define ESDHCCTL 0x0002e40c
  80. #define ESDHCCTL_PCS (0x00080000)
  81. #define PRSSTAT 0x0002e024
  82. #define PRSSTAT_DAT0 (0x01000000)
  83. #define PRSSTAT_CLSL (0x00800000)
  84. #define PRSSTAT_WPSPL (0x00080000)
  85. #define PRSSTAT_CDPL (0x00040000)
  86. #define PRSSTAT_CINS (0x00010000)
  87. #define PRSSTAT_BREN (0x00000800)
  88. #define PRSSTAT_BWEN (0x00000400)
  89. #define PRSSTAT_SDSTB (0X00000008)
  90. #define PRSSTAT_DLA (0x00000004)
  91. #define PRSSTAT_CICHB (0x00000002)
  92. #define PRSSTAT_CIDHB (0x00000001)
  93. #define PROCTL 0x0002e028
  94. #define PROCTL_INIT 0x00000020
  95. #define PROCTL_DTW_4 0x00000002
  96. #define PROCTL_DTW_8 0x00000004
  97. #define PROCTL_D3CD 0x00000008
  98. #define CMDARG 0x0002e008
  99. #define XFERTYP 0x0002e00c
  100. #define XFERTYP_CMD(x) ((x & 0x3f) << 24)
  101. #define XFERTYP_CMDTYP_NORMAL 0x0
  102. #define XFERTYP_CMDTYP_SUSPEND 0x00400000
  103. #define XFERTYP_CMDTYP_RESUME 0x00800000
  104. #define XFERTYP_CMDTYP_ABORT 0x00c00000
  105. #define XFERTYP_DPSEL 0x00200000
  106. #define XFERTYP_CICEN 0x00100000
  107. #define XFERTYP_CCCEN 0x00080000
  108. #define XFERTYP_RSPTYP_NONE 0
  109. #define XFERTYP_RSPTYP_136 0x00010000
  110. #define XFERTYP_RSPTYP_48 0x00020000
  111. #define XFERTYP_RSPTYP_48_BUSY 0x00030000
  112. #define XFERTYP_MSBSEL 0x00000020
  113. #define XFERTYP_DTDSEL 0x00000010
  114. #define XFERTYP_DDREN 0x00000008
  115. #define XFERTYP_AC12EN 0x00000004
  116. #define XFERTYP_BCEN 0x00000002
  117. #define XFERTYP_DMAEN 0x00000001
  118. #define CINS_TIMEOUT 1000
  119. #define PIO_TIMEOUT 500
  120. #define DSADDR 0x2e004
  121. #define CMDRSP0 0x2e010
  122. #define CMDRSP1 0x2e014
  123. #define CMDRSP2 0x2e018
  124. #define CMDRSP3 0x2e01c
  125. #define DATPORT 0x2e020
  126. #define WML 0x2e044
  127. #define WML_WRITE 0x00010000
  128. #ifdef CONFIG_FSL_SDHC_V2_3
  129. #define WML_RD_WML_MAX 0x80
  130. #define WML_WR_WML_MAX 0x80
  131. #define WML_RD_WML_MAX_VAL 0x0
  132. #define WML_WR_WML_MAX_VAL 0x0
  133. #define WML_RD_WML_MASK 0x7f
  134. #define WML_WR_WML_MASK 0x7f0000
  135. #else
  136. #define WML_RD_WML_MAX 0x10
  137. #define WML_WR_WML_MAX 0x80
  138. #define WML_RD_WML_MAX_VAL 0x10
  139. #define WML_WR_WML_MAX_VAL 0x80
  140. #define WML_RD_WML_MASK 0xff
  141. #define WML_WR_WML_MASK 0xff0000
  142. #endif
  143. #define BLKATTR 0x2e004
  144. #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
  145. #define BLKATTR_SIZE(x) (x & 0x1fff)
  146. #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
  147. #define ESDHC_HOSTCAPBLT_VS18 0x04000000
  148. #define ESDHC_HOSTCAPBLT_VS30 0x02000000
  149. #define ESDHC_HOSTCAPBLT_VS33 0x01000000
  150. #define ESDHC_HOSTCAPBLT_SRS 0x00800000
  151. #define ESDHC_HOSTCAPBLT_DMAS 0x00400000
  152. #define ESDHC_HOSTCAPBLT_HSS 0x00200000
  153. #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
  154. /* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
  155. #define MIX_CTRL_DDREN BIT(3)
  156. #define MIX_CTRL_DTDSEL_READ BIT(4)
  157. #define MIX_CTRL_AC23EN BIT(7)
  158. #define MIX_CTRL_EXE_TUNE BIT(22)
  159. #define MIX_CTRL_SMPCLK_SEL BIT(23)
  160. #define MIX_CTRL_AUTO_TUNE_EN BIT(24)
  161. #define MIX_CTRL_FBCLK_SEL BIT(25)
  162. #define MIX_CTRL_HS400_EN BIT(26)
  163. #define MIX_CTRL_HS400_ES BIT(27)
  164. /* Bits 3 and 6 are not SDHCI standard definitions */
  165. #define MIX_CTRL_SDHCI_MASK 0xb7
  166. /* Tuning bits */
  167. #define MIX_CTRL_TUNING_MASK 0x03c00000
  168. /* strobe dll register */
  169. #define ESDHC_STROBE_DLL_CTRL 0x70
  170. #define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
  171. #define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
  172. #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
  173. #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
  174. #define ESDHC_STROBE_DLL_STATUS 0x74
  175. #define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
  176. #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
  177. #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
  178. #define ESDHC_STD_TUNING_EN BIT(24)
  179. /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  180. #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
  181. #define ESDHC_TUNING_START_TAP_MASK 0xff
  182. #define ESDHC_TUNING_STEP_MASK 0x00070000
  183. #define ESDHC_TUNING_STEP_SHIFT 16
  184. #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
  185. #define ESDHC_FLAG_ENGCM07207 BIT(2)
  186. #define ESDHC_FLAG_USDHC BIT(3)
  187. #define ESDHC_FLAG_MAN_TUNING BIT(4)
  188. #define ESDHC_FLAG_STD_TUNING BIT(5)
  189. #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
  190. #define ESDHC_FLAG_ERR004536 BIT(7)
  191. #define ESDHC_FLAG_HS200 BIT(8)
  192. #define ESDHC_FLAG_HS400 BIT(9)
  193. #define ESDHC_FLAG_ERR010450 BIT(10)
  194. #define ESDHC_FLAG_HS400_ES BIT(11)
  195. struct fsl_esdhc_cfg {
  196. phys_addr_t esdhc_base;
  197. u32 sdhc_clk;
  198. u8 max_bus_width;
  199. int wp_enable;
  200. int vs18_enable; /* Use 1.8V if set to 1 */
  201. struct mmc_config cfg;
  202. };
  203. /* Select the correct accessors depending on endianess */
  204. #if defined CONFIG_SYS_FSL_ESDHC_LE
  205. #define esdhc_read32 in_le32
  206. #define esdhc_write32 out_le32
  207. #define esdhc_clrsetbits32 clrsetbits_le32
  208. #define esdhc_clrbits32 clrbits_le32
  209. #define esdhc_setbits32 setbits_le32
  210. #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
  211. #define esdhc_read32 in_be32
  212. #define esdhc_write32 out_be32
  213. #define esdhc_clrsetbits32 clrsetbits_be32
  214. #define esdhc_clrbits32 clrbits_be32
  215. #define esdhc_setbits32 setbits_be32
  216. #elif __BYTE_ORDER == __LITTLE_ENDIAN
  217. #define esdhc_read32 in_le32
  218. #define esdhc_write32 out_le32
  219. #define esdhc_clrsetbits32 clrsetbits_le32
  220. #define esdhc_clrbits32 clrbits_le32
  221. #define esdhc_setbits32 setbits_le32
  222. #elif __BYTE_ORDER == __BIG_ENDIAN
  223. #define esdhc_read32 in_be32
  224. #define esdhc_write32 out_be32
  225. #define esdhc_clrsetbits32 clrsetbits_be32
  226. #define esdhc_clrbits32 clrbits_be32
  227. #define esdhc_setbits32 setbits_be32
  228. #else
  229. #error "Endianess is not defined: please fix to continue"
  230. #endif
  231. #ifdef CONFIG_FSL_ESDHC_IMX
  232. int fsl_esdhc_mmc_init(bd_t *bis);
  233. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
  234. void fdt_fixup_esdhc(void *blob, bd_t *bd);
  235. #else
  236. static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
  237. static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
  238. #endif /* CONFIG_FSL_ESDHC_IMX */
  239. void __noreturn mmc_boot(void);
  240. void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
  241. #endif /* __FSL_ESDHC_IMX_H__ */