fsl_esdhc.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * FSL SD/MMC Defines
  4. *-------------------------------------------------------------------
  5. *
  6. * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
  7. */
  8. #ifndef __FSL_ESDHC_H__
  9. #define __FSL_ESDHC_H__
  10. #include <linux/errno.h>
  11. #include <asm/byteorder.h>
  12. /* needed for the mmc_cfg definition */
  13. #include <mmc.h>
  14. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  15. #include "../board/freescale/common/qixis.h"
  16. #endif
  17. /* FSL eSDHC-specific constants */
  18. #define SYSCTL 0x0002e02c
  19. #define SYSCTL_INITA 0x08000000
  20. #define SYSCTL_TIMEOUT_MASK 0x000f0000
  21. #define SYSCTL_CLOCK_MASK 0x0000fff0
  22. #define SYSCTL_CKEN 0x00000008
  23. #define SYSCTL_PEREN 0x00000004
  24. #define SYSCTL_HCKEN 0x00000002
  25. #define SYSCTL_IPGEN 0x00000001
  26. #define SYSCTL_RSTA 0x01000000
  27. #define SYSCTL_RSTC 0x02000000
  28. #define SYSCTL_RSTD 0x04000000
  29. #define IRQSTAT 0x0002e030
  30. #define IRQSTAT_DMAE (0x10000000)
  31. #define IRQSTAT_AC12E (0x01000000)
  32. #define IRQSTAT_DEBE (0x00400000)
  33. #define IRQSTAT_DCE (0x00200000)
  34. #define IRQSTAT_DTOE (0x00100000)
  35. #define IRQSTAT_CIE (0x00080000)
  36. #define IRQSTAT_CEBE (0x00040000)
  37. #define IRQSTAT_CCE (0x00020000)
  38. #define IRQSTAT_CTOE (0x00010000)
  39. #define IRQSTAT_CINT (0x00000100)
  40. #define IRQSTAT_CRM (0x00000080)
  41. #define IRQSTAT_CINS (0x00000040)
  42. #define IRQSTAT_BRR (0x00000020)
  43. #define IRQSTAT_BWR (0x00000010)
  44. #define IRQSTAT_DINT (0x00000008)
  45. #define IRQSTAT_BGE (0x00000004)
  46. #define IRQSTAT_TC (0x00000002)
  47. #define IRQSTAT_CC (0x00000001)
  48. #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
  49. #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
  50. IRQSTAT_DMAE)
  51. #define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
  52. #define IRQSTATEN 0x0002e034
  53. #define IRQSTATEN_DMAE (0x10000000)
  54. #define IRQSTATEN_AC12E (0x01000000)
  55. #define IRQSTATEN_DEBE (0x00400000)
  56. #define IRQSTATEN_DCE (0x00200000)
  57. #define IRQSTATEN_DTOE (0x00100000)
  58. #define IRQSTATEN_CIE (0x00080000)
  59. #define IRQSTATEN_CEBE (0x00040000)
  60. #define IRQSTATEN_CCE (0x00020000)
  61. #define IRQSTATEN_CTOE (0x00010000)
  62. #define IRQSTATEN_CINT (0x00000100)
  63. #define IRQSTATEN_CRM (0x00000080)
  64. #define IRQSTATEN_CINS (0x00000040)
  65. #define IRQSTATEN_BRR (0x00000020)
  66. #define IRQSTATEN_BWR (0x00000010)
  67. #define IRQSTATEN_DINT (0x00000008)
  68. #define IRQSTATEN_BGE (0x00000004)
  69. #define IRQSTATEN_TC (0x00000002)
  70. #define IRQSTATEN_CC (0x00000001)
  71. #define ESDHCCTL 0x0002e40c
  72. #define ESDHCCTL_PCS (0x00080000)
  73. #define PRSSTAT 0x0002e024
  74. #define PRSSTAT_DAT0 (0x01000000)
  75. #define PRSSTAT_CLSL (0x00800000)
  76. #define PRSSTAT_WPSPL (0x00080000)
  77. #define PRSSTAT_CDPL (0x00040000)
  78. #define PRSSTAT_CINS (0x00010000)
  79. #define PRSSTAT_BREN (0x00000800)
  80. #define PRSSTAT_BWEN (0x00000400)
  81. #define PRSSTAT_SDSTB (0X00000008)
  82. #define PRSSTAT_DLA (0x00000004)
  83. #define PRSSTAT_CICHB (0x00000002)
  84. #define PRSSTAT_CIDHB (0x00000001)
  85. #define PROCTL 0x0002e028
  86. #define PROCTL_INIT 0x00000020
  87. #define PROCTL_DTW_4 0x00000002
  88. #define PROCTL_DTW_8 0x00000004
  89. #define PROCTL_D3CD 0x00000008
  90. #define CMDARG 0x0002e008
  91. #define XFERTYP 0x0002e00c
  92. #define XFERTYP_CMD(x) ((x & 0x3f) << 24)
  93. #define XFERTYP_CMDTYP_NORMAL 0x0
  94. #define XFERTYP_CMDTYP_SUSPEND 0x00400000
  95. #define XFERTYP_CMDTYP_RESUME 0x00800000
  96. #define XFERTYP_CMDTYP_ABORT 0x00c00000
  97. #define XFERTYP_DPSEL 0x00200000
  98. #define XFERTYP_CICEN 0x00100000
  99. #define XFERTYP_CCCEN 0x00080000
  100. #define XFERTYP_RSPTYP_NONE 0
  101. #define XFERTYP_RSPTYP_136 0x00010000
  102. #define XFERTYP_RSPTYP_48 0x00020000
  103. #define XFERTYP_RSPTYP_48_BUSY 0x00030000
  104. #define XFERTYP_MSBSEL 0x00000020
  105. #define XFERTYP_DTDSEL 0x00000010
  106. #define XFERTYP_DDREN 0x00000008
  107. #define XFERTYP_AC12EN 0x00000004
  108. #define XFERTYP_BCEN 0x00000002
  109. #define XFERTYP_DMAEN 0x00000001
  110. #define CINS_TIMEOUT 1000
  111. #define PIO_TIMEOUT 500
  112. #define DSADDR 0x2e004
  113. #define CMDRSP0 0x2e010
  114. #define CMDRSP1 0x2e014
  115. #define CMDRSP2 0x2e018
  116. #define CMDRSP3 0x2e01c
  117. #define DATPORT 0x2e020
  118. #define WML 0x2e044
  119. #define WML_WRITE 0x00010000
  120. #ifdef CONFIG_FSL_SDHC_V2_3
  121. #define WML_RD_WML_MAX 0x80
  122. #define WML_WR_WML_MAX 0x80
  123. #define WML_RD_WML_MAX_VAL 0x0
  124. #define WML_WR_WML_MAX_VAL 0x0
  125. #define WML_RD_WML_MASK 0x7f
  126. #define WML_WR_WML_MASK 0x7f0000
  127. #else
  128. #define WML_RD_WML_MAX 0x10
  129. #define WML_WR_WML_MAX 0x80
  130. #define WML_RD_WML_MAX_VAL 0x10
  131. #define WML_WR_WML_MAX_VAL 0x80
  132. #define WML_RD_WML_MASK 0xff
  133. #define WML_WR_WML_MASK 0xff0000
  134. #endif
  135. #define BLKATTR 0x2e004
  136. #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
  137. #define BLKATTR_SIZE(x) (x & 0x1fff)
  138. #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
  139. /* Host controller capabilities register */
  140. #define HOSTCAPBLT_VS18 0x04000000
  141. #define HOSTCAPBLT_VS30 0x02000000
  142. #define HOSTCAPBLT_VS33 0x01000000
  143. #define HOSTCAPBLT_SRS 0x00800000
  144. #define HOSTCAPBLT_DMAS 0x00400000
  145. #define HOSTCAPBLT_HSS 0x00200000
  146. struct fsl_esdhc_cfg {
  147. phys_addr_t esdhc_base;
  148. u32 sdhc_clk;
  149. u8 max_bus_width;
  150. int vs18_enable; /* Use 1.8V if set to 1 */
  151. struct mmc_config cfg;
  152. };
  153. /* Select the correct accessors depending on endianess */
  154. #if defined CONFIG_SYS_FSL_ESDHC_LE
  155. #define esdhc_read32 in_le32
  156. #define esdhc_write32 out_le32
  157. #define esdhc_clrsetbits32 clrsetbits_le32
  158. #define esdhc_clrbits32 clrbits_le32
  159. #define esdhc_setbits32 setbits_le32
  160. #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
  161. #define esdhc_read32 in_be32
  162. #define esdhc_write32 out_be32
  163. #define esdhc_clrsetbits32 clrsetbits_be32
  164. #define esdhc_clrbits32 clrbits_be32
  165. #define esdhc_setbits32 setbits_be32
  166. #elif __BYTE_ORDER == __LITTLE_ENDIAN
  167. #define esdhc_read32 in_le32
  168. #define esdhc_write32 out_le32
  169. #define esdhc_clrsetbits32 clrsetbits_le32
  170. #define esdhc_clrbits32 clrbits_le32
  171. #define esdhc_setbits32 setbits_le32
  172. #elif __BYTE_ORDER == __BIG_ENDIAN
  173. #define esdhc_read32 in_be32
  174. #define esdhc_write32 out_be32
  175. #define esdhc_clrsetbits32 clrsetbits_be32
  176. #define esdhc_clrbits32 clrbits_be32
  177. #define esdhc_setbits32 setbits_be32
  178. #else
  179. #error "Endianess is not defined: please fix to continue"
  180. #endif
  181. #ifdef CONFIG_FSL_ESDHC
  182. int fsl_esdhc_mmc_init(bd_t *bis);
  183. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
  184. void fdt_fixup_esdhc(void *blob, bd_t *bd);
  185. #ifdef MMC_SUPPORTS_TUNING
  186. static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
  187. uint32_t opcode) {return 0; }
  188. #endif
  189. #else
  190. static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
  191. static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
  192. #endif /* CONFIG_FSL_ESDHC */
  193. void __noreturn mmc_boot(void);
  194. void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
  195. #endif /* __FSL_ESDHC_H__ */