fsl_dspi.h 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale DSPI Module Defines
  4. *
  5. * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. * Chao Fu (B44548@freesacle.com)
  8. * Haikun Wang (B53464@freescale.com)
  9. */
  10. #ifndef _FSL_DSPI_H_
  11. #define _FSL_DSPI_H_
  12. /* DMA Serial Peripheral Interface (DSPI) */
  13. struct dspi {
  14. u32 mcr; /* 0x00 */
  15. u32 resv0; /* 0x04 */
  16. u32 tcr; /* 0x08 */
  17. u32 ctar[8]; /* 0x0C - 0x28 */
  18. u32 sr; /* 0x2C */
  19. u32 irsr; /* 0x30 */
  20. u32 tfr; /* 0x34 - PUSHR */
  21. u32 rfr; /* 0x38 - POPR */
  22. #ifdef CONFIG_MCF547x_8x
  23. u32 tfdr[4]; /* 0x3C */
  24. u8 resv2[0x30]; /* 0x40 */
  25. u32 rfdr[4]; /* 0x7C */
  26. #else
  27. u32 tfdr[16]; /* 0x3C */
  28. u32 rfdr[16]; /* 0x7C */
  29. #endif
  30. };
  31. /* Module configuration */
  32. #define DSPI_MCR_MSTR 0x80000000
  33. #define DSPI_MCR_CSCK 0x40000000
  34. #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28)
  35. #define DSPI_MCR_FRZ 0x08000000
  36. #define DSPI_MCR_MTFE 0x04000000
  37. #define DSPI_MCR_PCSSE 0x02000000
  38. #define DSPI_MCR_ROOE 0x01000000
  39. #define DSPI_MCR_PCSIS(x) (1 << (16 + (x)))
  40. #define DSPI_MCR_PCSIS_MASK (0xff << 16)
  41. #define DSPI_MCR_CSIS7 0x00800000
  42. #define DSPI_MCR_CSIS6 0x00400000
  43. #define DSPI_MCR_CSIS5 0x00200000
  44. #define DSPI_MCR_CSIS4 0x00100000
  45. #define DSPI_MCR_CSIS3 0x00080000
  46. #define DSPI_MCR_CSIS2 0x00040000
  47. #define DSPI_MCR_CSIS1 0x00020000
  48. #define DSPI_MCR_CSIS0 0x00010000
  49. #define DSPI_MCR_DOZE 0x00008000
  50. #define DSPI_MCR_MDIS 0x00004000
  51. #define DSPI_MCR_DTXF 0x00002000
  52. #define DSPI_MCR_DRXF 0x00001000
  53. #define DSPI_MCR_CTXF 0x00000800
  54. #define DSPI_MCR_CRXF 0x00000400
  55. #define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8)
  56. #define DSPI_MCR_FCPCS 0x00000001
  57. #define DSPI_MCR_PES 0x00000001
  58. #define DSPI_MCR_HALT 0x00000001
  59. /* Transfer count */
  60. #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
  61. /* Clock and transfer attributes */
  62. #define DSPI_CTAR(x) (0x0c + (x * 4))
  63. #define DSPI_CTAR_DBR 0x80000000
  64. #define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27)
  65. #define DSPI_CTAR_CPOL 0x04000000
  66. #define DSPI_CTAR_CPHA 0x02000000
  67. #define DSPI_CTAR_LSBFE 0x01000000
  68. #define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22)
  69. #define DSPI_CTAR_PCSSCK_7CLK 0x00A00000
  70. #define DSPI_CTAR_PCSSCK_5CLK 0x00800000
  71. #define DSPI_CTAR_PCSSCK_3CLK 0x00400000
  72. #define DSPI_CTAR_PCSSCK_1CLK 0x00000000
  73. #define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20)
  74. #define DSPI_CTAR_PASC_7CLK 0x00300000
  75. #define DSPI_CTAR_PASC_5CLK 0x00200000
  76. #define DSPI_CTAR_PASC_3CLK 0x00100000
  77. #define DSPI_CTAR_PASC_1CLK 0x00000000
  78. #define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18)
  79. #define DSPI_CTAR_PDT_7CLK 0x000A0000
  80. #define DSPI_CTAR_PDT_5CLK 0x00080000
  81. #define DSPI_CTAR_PDT_3CLK 0x00040000
  82. #define DSPI_CTAR_PDT_1CLK 0x00000000
  83. #define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16)
  84. #define DSPI_CTAR_PBR_7CLK 0x00030000
  85. #define DSPI_CTAR_PBR_5CLK 0x00020000
  86. #define DSPI_CTAR_PBR_3CLK 0x00010000
  87. #define DSPI_CTAR_PBR_1CLK 0x00000000
  88. #define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12)
  89. #define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
  90. #define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
  91. #define DSPI_CTAR_BR(x) ((x) & 0x0F)
  92. /* Status */
  93. #define DSPI_SR_TCF 0x80000000
  94. #define DSPI_SR_TXRXS 0x40000000
  95. #define DSPI_SR_EOQF 0x10000000
  96. #define DSPI_SR_TFUF 0x08000000
  97. #define DSPI_SR_TFFF 0x02000000
  98. #define DSPI_SR_RFOF 0x00080000
  99. #define DSPI_SR_RFDF 0x00020000
  100. #define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12)
  101. #define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8)
  102. #define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4)
  103. #define DSPI_SR_RXPTR(x) ((x) & 0x0000000F)
  104. /* DMA/interrupt request selct and enable */
  105. #define DSPI_IRSR_TCFE 0x80000000
  106. #define DSPI_IRSR_EOQFE 0x10000000
  107. #define DSPI_IRSR_TFUFE 0x08000000
  108. #define DSPI_IRSR_TFFFE 0x02000000
  109. #define DSPI_IRSR_TFFFS 0x01000000
  110. #define DSPI_IRSR_RFOFE 0x00080000
  111. #define DSPI_IRSR_RFDFE 0x00020000
  112. #define DSPI_IRSR_RFDFS 0x00010000
  113. /* Transfer control - 32-bit access */
  114. #define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16)
  115. #define DSPI_TFR_CONT 0x80000000
  116. #define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28)
  117. #define DSPI_TFR_EOQ 0x08000000
  118. #define DSPI_TFR_CTCNT 0x04000000
  119. #define DSPI_TFR_CS7 0x00800000
  120. #define DSPI_TFR_CS6 0x00400000
  121. #define DSPI_TFR_CS5 0x00200000
  122. #define DSPI_TFR_CS4 0x00100000
  123. #define DSPI_TFR_CS3 0x00080000
  124. #define DSPI_TFR_CS2 0x00040000
  125. #define DSPI_TFR_CS1 0x00020000
  126. #define DSPI_TFR_CS0 0x00010000
  127. /* Transfer Fifo */
  128. #define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF)
  129. /* Bit definitions and macros for DRFR */
  130. #define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF)
  131. /* Bit definitions and macros for DTFDR group */
  132. #define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF)
  133. #define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16)
  134. /* Bit definitions and macros for DRFDR group */
  135. #define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF)
  136. #endif /* _FSL_DSPI_H_ */