fsl_ddr_dimm_params.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017-2018 NXP Semiconductor
  5. */
  6. #ifndef DDR2_DIMM_PARAMS_H
  7. #define DDR2_DIMM_PARAMS_H
  8. #define EDC_DATA_PARITY 1
  9. #define EDC_ECC 2
  10. #define EDC_AC_PARITY 4
  11. /* Parameters for a DDR dimm computed from the SPD */
  12. typedef struct dimm_params_s {
  13. /* DIMM organization parameters */
  14. char mpart[19]; /* guaranteed null terminated */
  15. unsigned int n_ranks;
  16. unsigned int die_density;
  17. unsigned long long rank_density;
  18. unsigned long long capacity;
  19. unsigned int data_width;
  20. unsigned int primary_sdram_width;
  21. unsigned int ec_sdram_width;
  22. unsigned int registered_dimm;
  23. unsigned int package_3ds; /* number of dies in 3DS DIMM */
  24. unsigned int device_width; /* x4, x8, x16 components */
  25. /* SDRAM device parameters */
  26. unsigned int n_row_addr;
  27. unsigned int n_col_addr;
  28. unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
  29. #ifdef CONFIG_SYS_FSL_DDR4
  30. unsigned int bank_addr_bits;
  31. unsigned int bank_group_bits;
  32. #else
  33. unsigned int n_banks_per_sdram_device;
  34. #endif
  35. unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
  36. /* used in computing base address of DIMMs */
  37. unsigned long long base_address;
  38. /* mirrored DIMMs */
  39. unsigned int mirrored_dimm; /* only for ddr3 */
  40. /* DIMM timing parameters */
  41. int mtb_ps; /* medium timebase ps */
  42. int ftb_10th_ps; /* fine timebase, in 1/10 ps */
  43. int taa_ps; /* minimum CAS latency time */
  44. int tfaw_ps; /* four active window delay */
  45. /*
  46. * SDRAM clock periods
  47. * The range for these are 1000-10000 so a short should be sufficient
  48. */
  49. int tckmin_x_ps;
  50. int tckmin_x_minus_1_ps;
  51. int tckmin_x_minus_2_ps;
  52. int tckmax_ps;
  53. /* SPD-defined CAS latencies */
  54. unsigned int caslat_x;
  55. unsigned int caslat_x_minus_1;
  56. unsigned int caslat_x_minus_2;
  57. unsigned int caslat_lowest_derated; /* Derated CAS latency */
  58. /* basic timing parameters */
  59. int trcd_ps;
  60. int trp_ps;
  61. int tras_ps;
  62. #ifdef CONFIG_SYS_FSL_DDR4
  63. int trfc1_ps;
  64. int trfc2_ps;
  65. int trfc4_ps;
  66. int trrds_ps;
  67. int trrdl_ps;
  68. int tccdl_ps;
  69. int trfc_slr_ps;
  70. #else
  71. int twr_ps; /* maximum = 63750 ps */
  72. int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
  73. = 511750 ps */
  74. int trrd_ps; /* maximum = 63750 ps */
  75. int twtr_ps; /* maximum = 63750 ps */
  76. int trtp_ps; /* byte 38, spd->trtp */
  77. #endif
  78. int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
  79. int refresh_rate_ps;
  80. int extended_op_srt;
  81. #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
  82. int tis_ps; /* byte 32, spd->ca_setup */
  83. int tih_ps; /* byte 33, spd->ca_hold */
  84. int tds_ps; /* byte 34, spd->data_setup */
  85. int tdh_ps; /* byte 35, spd->data_hold */
  86. int tdqsq_max_ps; /* byte 44, spd->tdqsq */
  87. int tqhs_ps; /* byte 45, spd->tqhs */
  88. #endif
  89. /* DDR3 & DDR4 RDIMM */
  90. unsigned char rcw[16]; /* Register Control Word 0-15 */
  91. #ifdef CONFIG_SYS_FSL_DDR4
  92. unsigned int dq_mapping[18];
  93. unsigned int dq_mapping_ors;
  94. #endif
  95. } dimm_params_t;
  96. unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
  97. const generic_spd_eeprom_t *spd,
  98. dimm_params_t *pdimm,
  99. unsigned int dimm_number);
  100. #endif