fsl_ddr.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef FSL_DDR_MAIN_H
  6. #define FSL_DDR_MAIN_H
  7. #include <fsl_ddrc_version.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr_dimm_params.h>
  10. #include <common_timing_params.h>
  11. #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  12. /* All controllers are for main memory */
  13. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
  14. #endif
  15. #ifdef CONFIG_SYS_FSL_DDR_LE
  16. #define ddr_in32(a) in_le32(a)
  17. #define ddr_out32(a, v) out_le32(a, v)
  18. #define ddr_setbits32(a, v) setbits_le32(a, v)
  19. #define ddr_clrbits32(a, v) clrbits_le32(a, v)
  20. #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  21. #else
  22. #define ddr_in32(a) in_be32(a)
  23. #define ddr_out32(a, v) out_be32(a, v)
  24. #define ddr_setbits32(a, v) setbits_be32(a, v)
  25. #define ddr_clrbits32(a, v) clrbits_be32(a, v)
  26. #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  27. #endif
  28. u32 fsl_ddr_get_version(unsigned int ctrl_num);
  29. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  30. /*
  31. * Bind the main DDR setup driver's generic names
  32. * to this specific DDR technology.
  33. */
  34. static __inline__ int
  35. compute_dimm_parameters(const unsigned int ctrl_num,
  36. const generic_spd_eeprom_t *spd,
  37. dimm_params_t *pdimm,
  38. unsigned int dimm_number)
  39. {
  40. return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  41. }
  42. #endif
  43. /*
  44. * Data Structures
  45. *
  46. * All data structures have to be on the stack
  47. */
  48. #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  49. typedef struct {
  50. generic_spd_eeprom_t
  51. spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  52. struct dimm_params_s
  53. dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  54. memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  55. common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  56. fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  57. unsigned int first_ctrl;
  58. unsigned int num_ctrls;
  59. unsigned long long mem_base;
  60. unsigned int dimm_slots_per_ctrl;
  61. int (*board_need_mem_reset)(void);
  62. void (*board_mem_reset)(void);
  63. void (*board_mem_de_reset)(void);
  64. } fsl_ddr_info_t;
  65. /* Compute steps */
  66. #define STEP_GET_SPD (1 << 0)
  67. #define STEP_COMPUTE_DIMM_PARMS (1 << 1)
  68. #define STEP_COMPUTE_COMMON_PARMS (1 << 2)
  69. #define STEP_GATHER_OPTS (1 << 3)
  70. #define STEP_ASSIGN_ADDRESSES (1 << 4)
  71. #define STEP_COMPUTE_REGS (1 << 5)
  72. #define STEP_PROGRAM_REGS (1 << 6)
  73. #define STEP_ALL 0xFFF
  74. unsigned long long
  75. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  76. unsigned int size_only);
  77. const char *step_to_string(unsigned int step);
  78. unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  79. const memctl_options_t *popts,
  80. fsl_ddr_cfg_regs_t *ddr,
  81. const common_timing_params_t *common_dimm,
  82. const dimm_params_t *dimm_parameters,
  83. unsigned int dbw_capacity_adjust,
  84. unsigned int size_only);
  85. unsigned int compute_lowest_common_dimm_parameters(
  86. const unsigned int ctrl_num,
  87. const dimm_params_t *dimm_params,
  88. common_timing_params_t *outpdimm,
  89. unsigned int number_of_dimms);
  90. unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  91. memctl_options_t *popts,
  92. dimm_params_t *pdimm,
  93. unsigned int ctrl_num);
  94. void check_interleaving_options(fsl_ddr_info_t *pinfo);
  95. unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
  96. unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
  97. unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
  98. void fsl_ddr_set_lawbar(
  99. const common_timing_params_t *memctl_common_params,
  100. unsigned int memctl_interleaved,
  101. unsigned int ctrl_num);
  102. void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
  103. unsigned int last_ctrl);
  104. int fsl_ddr_interactive_env_var_exists(void);
  105. unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
  106. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  107. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  108. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
  109. unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
  110. void board_add_ram_info(int use_default);
  111. /* processor specific function */
  112. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  113. unsigned int ctrl_num, int step);
  114. void remove_unused_controllers(fsl_ddr_info_t *info);
  115. /* board specific function */
  116. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  117. unsigned int controller_number,
  118. unsigned int dimm_number);
  119. void update_spd_address(unsigned int ctrl_num,
  120. unsigned int slot,
  121. unsigned int *addr);
  122. void erratum_a009942_check_cpo(void);
  123. #endif