fm_eth.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __FM_ETH_H__
  7. #define __FM_ETH_H__
  8. #include <common.h>
  9. #include <phy.h>
  10. #include <asm/types.h>
  11. enum fm_port {
  12. FM1_DTSEC1,
  13. FM1_DTSEC2,
  14. FM1_DTSEC3,
  15. FM1_DTSEC4,
  16. FM1_DTSEC5,
  17. FM1_DTSEC6,
  18. FM1_DTSEC9,
  19. FM1_DTSEC10,
  20. FM1_10GEC1,
  21. FM1_10GEC2,
  22. FM1_10GEC3,
  23. FM1_10GEC4,
  24. FM2_DTSEC1,
  25. FM2_DTSEC2,
  26. FM2_DTSEC3,
  27. FM2_DTSEC4,
  28. FM2_DTSEC5,
  29. FM2_DTSEC6,
  30. FM2_DTSEC9,
  31. FM2_DTSEC10,
  32. FM2_10GEC1,
  33. FM2_10GEC2,
  34. NUM_FM_PORTS,
  35. };
  36. enum fm_eth_type {
  37. FM_ETH_1G_E,
  38. FM_ETH_10G_E,
  39. };
  40. /* Historically, on FMan v3 platforms, the first MDIO bus has been used for
  41. * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
  42. * TGEC name).
  43. *
  44. * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
  45. * and no TGEC ports are present on-board.
  46. */
  47. #ifdef CONFIG_SYS_FMAN_V3
  48. #ifdef CONFIG_TARGET_LS1046AFRWY
  49. #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
  50. #else
  51. #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
  52. #endif
  53. #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
  54. #if (CONFIG_SYS_NUM_FMAN == 2)
  55. #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
  56. #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
  57. #endif
  58. #else
  59. #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
  60. #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
  61. #endif
  62. #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
  63. #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
  64. /* Fman ethernet info struct */
  65. #define FM_ETH_INFO_INITIALIZER(idx, pregs) \
  66. .fm = idx, \
  67. .phy_regs = (void *)pregs, \
  68. .enet_if = PHY_INTERFACE_MODE_NONE, \
  69. #ifdef CONFIG_SYS_FMAN_V3
  70. #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
  71. { \
  72. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
  73. .index = idx, \
  74. .num = n - 1, \
  75. .type = FM_ETH_1G_E, \
  76. .port = FM##idx##_DTSEC##n, \
  77. .rx_port_id = RX_PORT_1G_BASE + n - 1, \
  78. .tx_port_id = TX_PORT_1G_BASE + n - 1, \
  79. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  80. offsetof(struct ccsr_fman, memac[n-1]),\
  81. }
  82. #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  83. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  84. { \
  85. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  86. .index = idx, \
  87. .num = n - 1, \
  88. .type = FM_ETH_10G_E, \
  89. .port = FM##idx##_10GEC##n, \
  90. .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
  91. .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
  92. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  93. offsetof(struct ccsr_fman, memac[n-1]),\
  94. }
  95. #else
  96. #if (CONFIG_SYS_NUM_FMAN == 2)
  97. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  98. { \
  99. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
  100. .index = idx, \
  101. .num = n - 1, \
  102. .type = FM_ETH_10G_E, \
  103. .port = FM##idx##_10GEC##n, \
  104. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  105. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  106. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  107. offsetof(struct ccsr_fman, memac[n-1+8]),\
  108. }
  109. #else
  110. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  111. { \
  112. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  113. .index = idx, \
  114. .num = n - 1, \
  115. .type = FM_ETH_10G_E, \
  116. .port = FM##idx##_10GEC##n, \
  117. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  118. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  119. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  120. offsetof(struct ccsr_fman, memac[n-1+8]),\
  121. }
  122. #endif
  123. #endif
  124. #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
  125. #define FM_TGEC_INFO_INITIALIZER2(idx, n) \
  126. { \
  127. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  128. .index = idx, \
  129. .num = n - 1, \
  130. .type = FM_ETH_10G_E, \
  131. .port = FM##idx##_10GEC##n, \
  132. .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
  133. .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
  134. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  135. offsetof(struct ccsr_fman, memac[n-1-2]),\
  136. }
  137. #endif
  138. #else
  139. #define FM_DTSEC_INFO_INITIALIZER(idx, n) \
  140. { \
  141. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
  142. .index = idx, \
  143. .num = n - 1, \
  144. .type = FM_ETH_1G_E, \
  145. .port = FM##idx##_DTSEC##n, \
  146. .rx_port_id = RX_PORT_1G_BASE + n - 1, \
  147. .tx_port_id = TX_PORT_1G_BASE + n - 1, \
  148. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  149. offsetof(struct ccsr_fman, mac_1g[n-1]),\
  150. }
  151. #define FM_TGEC_INFO_INITIALIZER(idx, n) \
  152. { \
  153. FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
  154. .index = idx, \
  155. .num = n - 1, \
  156. .type = FM_ETH_10G_E, \
  157. .port = FM##idx##_10GEC##n, \
  158. .rx_port_id = RX_PORT_10G_BASE + n - 1, \
  159. .tx_port_id = TX_PORT_10G_BASE + n - 1, \
  160. .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
  161. offsetof(struct ccsr_fman, mac_10g[n-1]),\
  162. }
  163. #endif
  164. struct fm_eth_info {
  165. u8 enabled;
  166. u8 fm;
  167. u8 num;
  168. u8 phy_addr;
  169. int index;
  170. u16 rx_port_id;
  171. u16 tx_port_id;
  172. enum fm_port port;
  173. enum fm_eth_type type;
  174. void *phy_regs;
  175. phy_interface_t enet_if;
  176. u32 compat_offset;
  177. struct mii_dev *bus;
  178. };
  179. struct tgec_mdio_info {
  180. struct tgec_mdio_controller *regs;
  181. char *name;
  182. };
  183. struct memac_mdio_info {
  184. struct memac_mdio_controller *regs;
  185. char *name;
  186. };
  187. int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
  188. int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
  189. int fm_standard_init(bd_t *bis);
  190. void fman_enet_init(void);
  191. void fdt_fixup_fman_ethernet(void *fdt);
  192. phy_interface_t fm_info_get_enet_if(enum fm_port port);
  193. void fm_info_set_phy_address(enum fm_port port, int address);
  194. int fm_info_get_phy_address(enum fm_port port);
  195. void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
  196. void fm_disable_port(enum fm_port port);
  197. void fm_enable_port(enum fm_port port);
  198. void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
  199. unsigned int port_num, int phy_base_addr);
  200. int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
  201. unsigned int port_num, unsigned regnum);
  202. #endif