exynos_lcd.h 2.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * exynos_lcd.h - Exynos LCD Controller structures
  4. *
  5. * (C) Copyright 2001
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #ifndef _EXYNOS_LCD_H_
  9. #define _EXYNOS_LCD_H_
  10. enum {
  11. FIMD_RGB_INTERFACE = 1,
  12. FIMD_CPU_INTERFACE = 2,
  13. };
  14. enum exynos_fb_rgb_mode_t {
  15. MODE_RGB_P = 0,
  16. MODE_BGR_P = 1,
  17. MODE_RGB_S = 2,
  18. MODE_BGR_S = 3,
  19. };
  20. typedef struct vidinfo {
  21. ushort vl_col; /* Number of columns (i.e. 640) */
  22. ushort vl_row; /* Number of rows (i.e. 480) */
  23. ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
  24. ushort vl_width; /* Width of display area in millimeters */
  25. ushort vl_height; /* Height of display area in millimeters */
  26. /* LCD configuration register */
  27. u_char vl_freq; /* Frequency */
  28. u_char vl_clkp; /* Clock polarity */
  29. u_char vl_oep; /* Output Enable polarity */
  30. u_char vl_hsp; /* Horizontal Sync polarity */
  31. u_char vl_vsp; /* Vertical Sync polarity */
  32. u_char vl_dp; /* Data polarity */
  33. u_char vl_bpix; /* Bits per pixel */
  34. /* Horizontal control register. Timing from data sheet */
  35. u_char vl_hspw; /* Horz sync pulse width */
  36. u_char vl_hfpd; /* Wait before of line */
  37. u_char vl_hbpd; /* Wait end of line */
  38. /* Vertical control register. */
  39. u_char vl_vspw; /* Vertical sync pulse width */
  40. u_char vl_vfpd; /* Wait before of frame */
  41. u_char vl_vbpd; /* Wait end of frame */
  42. u_char vl_cmd_allow_len; /* Wait end of frame */
  43. unsigned int win_id;
  44. unsigned int init_delay;
  45. unsigned int power_on_delay;
  46. unsigned int reset_delay;
  47. unsigned int interface_mode;
  48. unsigned int mipi_enabled;
  49. unsigned int dp_enabled;
  50. unsigned int cs_setup;
  51. unsigned int wr_setup;
  52. unsigned int wr_act;
  53. unsigned int wr_hold;
  54. unsigned int logo_on;
  55. unsigned int logo_width;
  56. unsigned int logo_height;
  57. int logo_x_offset;
  58. int logo_y_offset;
  59. unsigned long logo_addr;
  60. unsigned int rgb_mode;
  61. unsigned int resolution;
  62. /* parent clock name(MPLL, EPLL or VPLL) */
  63. unsigned int pclk_name;
  64. /* ratio value for source clock from parent clock. */
  65. unsigned int sclk_div;
  66. unsigned int dual_lcd_enabled;
  67. struct exynos_fb *reg;
  68. struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
  69. } vidinfo_t;
  70. #endif